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0001 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
0002 /* QLogic qede NIC Driver
0003  * Copyright (c) 2015-2017  QLogic Corporation
0004  * Copyright (c) 2019-2020 Marvell International Ltd.
0005  */
0006 
0007 #ifndef _QEDE_H_
0008 #define _QEDE_H_
0009 #include <linux/compiler.h>
0010 #include <linux/version.h>
0011 #include <linux/workqueue.h>
0012 #include <linux/netdevice.h>
0013 #include <linux/interrupt.h>
0014 #include <linux/bitmap.h>
0015 #include <linux/kernel.h>
0016 #include <linux/mutex.h>
0017 #include <linux/bpf.h>
0018 #include <net/xdp.h>
0019 #include <linux/qed/qede_rdma.h>
0020 #include <linux/io.h>
0021 #ifdef CONFIG_RFS_ACCEL
0022 #include <linux/cpu_rmap.h>
0023 #endif
0024 #include <linux/qed/common_hsi.h>
0025 #include <linux/qed/eth_common.h>
0026 #include <linux/qed/qed_if.h>
0027 #include <linux/qed/qed_chain.h>
0028 #include <linux/qed/qed_eth_if.h>
0029 
0030 #include <net/pkt_cls.h>
0031 #include <net/tc_act/tc_gact.h>
0032 
0033 #define DRV_MODULE_SYM      qede
0034 
0035 struct qede_stats_common {
0036     u64 no_buff_discards;
0037     u64 packet_too_big_discard;
0038     u64 ttl0_discard;
0039     u64 rx_ucast_bytes;
0040     u64 rx_mcast_bytes;
0041     u64 rx_bcast_bytes;
0042     u64 rx_ucast_pkts;
0043     u64 rx_mcast_pkts;
0044     u64 rx_bcast_pkts;
0045     u64 mftag_filter_discards;
0046     u64 mac_filter_discards;
0047     u64 gft_filter_drop;
0048     u64 tx_ucast_bytes;
0049     u64 tx_mcast_bytes;
0050     u64 tx_bcast_bytes;
0051     u64 tx_ucast_pkts;
0052     u64 tx_mcast_pkts;
0053     u64 tx_bcast_pkts;
0054     u64 tx_err_drop_pkts;
0055     u64 coalesced_pkts;
0056     u64 coalesced_events;
0057     u64 coalesced_aborts_num;
0058     u64 non_coalesced_pkts;
0059     u64 coalesced_bytes;
0060     u64 link_change_count;
0061     u64 ptp_skip_txts;
0062 
0063     /* port */
0064     u64 rx_64_byte_packets;
0065     u64 rx_65_to_127_byte_packets;
0066     u64 rx_128_to_255_byte_packets;
0067     u64 rx_256_to_511_byte_packets;
0068     u64 rx_512_to_1023_byte_packets;
0069     u64 rx_1024_to_1518_byte_packets;
0070     u64 rx_crc_errors;
0071     u64 rx_mac_crtl_frames;
0072     u64 rx_pause_frames;
0073     u64 rx_pfc_frames;
0074     u64 rx_align_errors;
0075     u64 rx_carrier_errors;
0076     u64 rx_oversize_packets;
0077     u64 rx_jabbers;
0078     u64 rx_undersize_packets;
0079     u64 rx_fragments;
0080     u64 tx_64_byte_packets;
0081     u64 tx_65_to_127_byte_packets;
0082     u64 tx_128_to_255_byte_packets;
0083     u64 tx_256_to_511_byte_packets;
0084     u64 tx_512_to_1023_byte_packets;
0085     u64 tx_1024_to_1518_byte_packets;
0086     u64 tx_pause_frames;
0087     u64 tx_pfc_frames;
0088     u64 brb_truncates;
0089     u64 brb_discards;
0090     u64 tx_mac_ctrl_frames;
0091 };
0092 
0093 struct qede_stats_bb {
0094     u64 rx_1519_to_1522_byte_packets;
0095     u64 rx_1519_to_2047_byte_packets;
0096     u64 rx_2048_to_4095_byte_packets;
0097     u64 rx_4096_to_9216_byte_packets;
0098     u64 rx_9217_to_16383_byte_packets;
0099     u64 tx_1519_to_2047_byte_packets;
0100     u64 tx_2048_to_4095_byte_packets;
0101     u64 tx_4096_to_9216_byte_packets;
0102     u64 tx_9217_to_16383_byte_packets;
0103     u64 tx_lpi_entry_count;
0104     u64 tx_total_collisions;
0105 };
0106 
0107 struct qede_stats_ah {
0108     u64 rx_1519_to_max_byte_packets;
0109     u64 tx_1519_to_max_byte_packets;
0110 };
0111 
0112 struct qede_stats {
0113     struct qede_stats_common common;
0114 
0115     union {
0116         struct qede_stats_bb bb;
0117         struct qede_stats_ah ah;
0118     };
0119 };
0120 
0121 struct qede_vlan {
0122     struct list_head list;
0123     u16 vid;
0124     bool configured;
0125 };
0126 
0127 struct qede_rdma_dev {
0128     struct qedr_dev *qedr_dev;
0129     struct list_head entry;
0130     struct list_head rdma_event_list;
0131     struct workqueue_struct *rdma_wq;
0132     struct kref refcnt;
0133     struct completion event_comp;
0134     bool exp_recovery;
0135 };
0136 
0137 struct qede_ptp;
0138 
0139 #define QEDE_RFS_MAX_FLTR   256
0140 
0141 enum qede_flags_bit {
0142     QEDE_FLAGS_IS_VF = 0,
0143     QEDE_FLAGS_LINK_REQUESTED,
0144     QEDE_FLAGS_PTP_TX_IN_PRORGESS,
0145     QEDE_FLAGS_TX_TIMESTAMPING_EN
0146 };
0147 
0148 #define QEDE_DUMP_MAX_ARGS 4
0149 enum qede_dump_cmd {
0150     QEDE_DUMP_CMD_NONE = 0,
0151     QEDE_DUMP_CMD_NVM_CFG,
0152     QEDE_DUMP_CMD_GRCDUMP,
0153     QEDE_DUMP_CMD_MAX
0154 };
0155 
0156 struct qede_dump_info {
0157     enum qede_dump_cmd cmd;
0158     u8 num_args;
0159     u32 args[QEDE_DUMP_MAX_ARGS];
0160 };
0161 
0162 struct qede_coalesce {
0163     bool isvalid;
0164     u16 rxc;
0165     u16 txc;
0166 };
0167 
0168 struct qede_dev {
0169     struct qed_dev          *cdev;
0170     struct net_device       *ndev;
0171     struct pci_dev          *pdev;
0172     struct devlink          *devlink;
0173 
0174     u32             dp_module;
0175     u8              dp_level;
0176 
0177     unsigned long           flags;
0178 #define IS_VF(edev)         test_bit(QEDE_FLAGS_IS_VF, \
0179                          &(edev)->flags)
0180 
0181     const struct qed_eth_ops    *ops;
0182     struct qede_ptp         *ptp;
0183     u64             ptp_skip_txts;
0184 
0185     struct qed_dev_eth_info     dev_info;
0186 #define QEDE_MAX_RSS_CNT(edev)      ((edev)->dev_info.num_queues)
0187 #define QEDE_MAX_TSS_CNT(edev)      ((edev)->dev_info.num_queues)
0188 #define QEDE_IS_BB(edev) \
0189     ((edev)->dev_info.common.dev_type == QED_DEV_TYPE_BB)
0190 #define QEDE_IS_AH(edev) \
0191     ((edev)->dev_info.common.dev_type == QED_DEV_TYPE_AH)
0192 
0193     struct qede_fastpath        *fp_array;
0194     struct qede_coalesce            *coal_entry;
0195     u8              req_num_tx;
0196     u8              fp_num_tx;
0197     u8              req_num_rx;
0198     u8              fp_num_rx;
0199     u16             req_queues;
0200     u16             num_queues;
0201     u16             total_xdp_queues;
0202 
0203 #define QEDE_QUEUE_CNT(edev)        ((edev)->num_queues)
0204 #define QEDE_RSS_COUNT(edev)        ((edev)->num_queues - (edev)->fp_num_tx)
0205 #define QEDE_RX_QUEUE_IDX(edev, i)  (i)
0206 #define QEDE_TSS_COUNT(edev)        ((edev)->num_queues - (edev)->fp_num_rx)
0207 
0208     struct qed_int_info     int_info;
0209 
0210     /* Smaller private variant of the RTNL lock */
0211     struct mutex            qede_lock;
0212     u32             state; /* Protected by qede_lock */
0213     u16             rx_buf_size;
0214     u32             rx_copybreak;
0215 
0216     /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
0217 #define ETH_OVERHEAD            (ETH_HLEN + 8 + 8)
0218     /* Max supported alignment is 256 (8 shift)
0219      * minimal alignment shift 6 is optimal for 57xxx HW performance
0220      */
0221 #define QEDE_RX_ALIGN_SHIFT     max(6, min(8, L1_CACHE_SHIFT))
0222     /* We assume skb_build() uses sizeof(struct skb_shared_info) bytes
0223      * at the end of skb->data, to avoid wasting a full cache line.
0224      * This reduces memory use (skb->truesize).
0225      */
0226 #define QEDE_FW_RX_ALIGN_END                    \
0227     max_t(u64, 1UL << QEDE_RX_ALIGN_SHIFT,          \
0228           SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
0229 
0230     struct qede_stats       stats;
0231 
0232     /* Bitfield to track initialized RSS params */
0233     u32             rss_params_inited;
0234 #define QEDE_RSS_INDIR_INITED       BIT(0)
0235 #define QEDE_RSS_KEY_INITED     BIT(1)
0236 #define QEDE_RSS_CAPS_INITED        BIT(2)
0237 
0238     u16             rss_ind_table[128];
0239     u32             rss_key[10];
0240     u8              rss_caps;
0241 
0242     /* Both must be a power of two */
0243     u16             q_num_rx_buffers;
0244     u16             q_num_tx_buffers;
0245 
0246     bool                gro_disable;
0247 
0248     struct list_head        vlan_list;
0249     u16             configured_vlans;
0250     u16             non_configured_vlans;
0251     bool                accept_any_vlan;
0252 
0253     struct delayed_work     sp_task;
0254     unsigned long           sp_flags;
0255     u16             vxlan_dst_port;
0256     u16             geneve_dst_port;
0257 
0258     struct qede_arfs        *arfs;
0259     bool                wol_enabled;
0260 
0261     struct qede_rdma_dev        rdma_info;
0262 
0263     struct bpf_prog         *xdp_prog;
0264 
0265     enum qed_hw_err_type        last_err_type;
0266     unsigned long           err_flags;
0267 #define QEDE_ERR_IS_HANDLED     31
0268 #define QEDE_ERR_ATTN_CLR_EN        0
0269 #define QEDE_ERR_GET_DBG_INFO       1
0270 #define QEDE_ERR_IS_RECOVERABLE     2
0271 #define QEDE_ERR_WARN           3
0272 
0273     struct qede_dump_info       dump_info;
0274 };
0275 
0276 enum QEDE_STATE {
0277     QEDE_STATE_CLOSED,
0278     QEDE_STATE_OPEN,
0279     QEDE_STATE_RECOVERY,
0280 };
0281 
0282 #define HILO_U64(hi, lo)        ((((u64)(hi)) << 32) + (lo))
0283 
0284 #define MAX_NUM_TC  8
0285 #define MAX_NUM_PRI 8
0286 
0287 /* The driver supports the new build_skb() API:
0288  * RX ring buffer contains pointer to kmalloc() data only,
0289  * skb are built only after the frame was DMA-ed.
0290  */
0291 struct sw_rx_data {
0292     struct page *data;
0293     dma_addr_t mapping;
0294     unsigned int page_offset;
0295 };
0296 
0297 enum qede_agg_state {
0298     QEDE_AGG_STATE_NONE  = 0,
0299     QEDE_AGG_STATE_START = 1,
0300     QEDE_AGG_STATE_ERROR = 2
0301 };
0302 
0303 struct qede_agg_info {
0304     /* rx_buf is a data buffer that can be placed / consumed from rx bd
0305      * chain. It has two purposes: We will preallocate the data buffer
0306      * for each aggregation when we open the interface and will place this
0307      * buffer on the rx-bd-ring when we receive TPA_START. We don't want
0308      * to be in a state where allocation fails, as we can't reuse the
0309      * consumer buffer in the rx-chain since FW may still be writing to it
0310      * (since header needs to be modified for TPA).
0311      * The second purpose is to keep a pointer to the bd buffer during
0312      * aggregation.
0313      */
0314     struct sw_rx_data buffer;
0315     struct sk_buff *skb;
0316 
0317     /* We need some structs from the start cookie until termination */
0318     u16 vlan_tag;
0319 
0320     bool tpa_start_fail;
0321     u8 state;
0322     u8 frag_id;
0323 
0324     u8 tunnel_type;
0325 };
0326 
0327 struct qede_rx_queue {
0328     __le16 *hw_cons_ptr;
0329     void __iomem *hw_rxq_prod_addr;
0330 
0331     /* Required for the allocation of replacement buffers */
0332     struct device *dev;
0333 
0334     struct bpf_prog *xdp_prog;
0335 
0336     u16 sw_rx_cons;
0337     u16 sw_rx_prod;
0338 
0339     u16 filled_buffers;
0340     u8 data_direction;
0341     u8 rxq_id;
0342 
0343     /* Used once per each NAPI run */
0344     u16 num_rx_buffers;
0345 
0346     u16 rx_headroom;
0347 
0348     u32 rx_buf_size;
0349     u32 rx_buf_seg_size;
0350 
0351     struct sw_rx_data *sw_rx_ring;
0352     struct qed_chain rx_bd_ring;
0353     struct qed_chain rx_comp_ring ____cacheline_aligned;
0354 
0355     /* GRO */
0356     struct qede_agg_info tpa_info[ETH_TPA_MAX_AGGS_NUM];
0357 
0358     /* Used once per each NAPI run */
0359     u64 rcv_pkts;
0360 
0361     u64 rx_hw_errors;
0362     u64 rx_alloc_errors;
0363     u64 rx_ip_frags;
0364 
0365     u64 xdp_no_pass;
0366 
0367     void *handle;
0368     struct xdp_rxq_info xdp_rxq;
0369 };
0370 
0371 union db_prod {
0372     struct eth_db_data data;
0373     u32     raw;
0374 };
0375 
0376 struct sw_tx_bd {
0377     struct sk_buff *skb;
0378     u8 flags;
0379 /* Set on the first BD descriptor when there is a split BD */
0380 #define QEDE_TSO_SPLIT_BD       BIT(0)
0381 };
0382 
0383 struct sw_tx_xdp {
0384     struct page         *page;
0385     struct xdp_frame        *xdpf;
0386     dma_addr_t          mapping;
0387 };
0388 
0389 struct qede_tx_queue {
0390     u8              is_xdp;
0391     bool                is_legacy;
0392     u16             sw_tx_cons;
0393     u16             sw_tx_prod;
0394     u16             num_tx_buffers; /* Slowpath only */
0395 
0396     u64             xmit_pkts;
0397     u64             stopped_cnt;
0398     u64             tx_mem_alloc_err;
0399 
0400     __le16              *hw_cons_ptr;
0401 
0402     /* Needed for the mapping of packets */
0403     struct device           *dev;
0404 
0405     void __iomem            *doorbell_addr;
0406     union db_prod           tx_db;
0407 
0408     /* Spinlock for XDP queues in case of XDP_REDIRECT */
0409     spinlock_t          xdp_tx_lock;
0410 
0411     int             index; /* Slowpath only */
0412 #define QEDE_TXQ_XDP_TO_IDX(edev, txq)  ((txq)->index - \
0413                      QEDE_MAX_TSS_CNT(edev))
0414 #define QEDE_TXQ_IDX_TO_XDP(edev, idx)  ((idx) + QEDE_MAX_TSS_CNT(edev))
0415 #define QEDE_NDEV_TXQ_ID_TO_FP_ID(edev, idx)    ((edev)->fp_num_rx + \
0416                          ((idx) % QEDE_TSS_COUNT(edev)))
0417 #define QEDE_NDEV_TXQ_ID_TO_TXQ_COS(edev, idx)  ((idx) / QEDE_TSS_COUNT(edev))
0418 #define QEDE_TXQ_TO_NDEV_TXQ_ID(edev, txq)  ((QEDE_TSS_COUNT(edev) * \
0419                          (txq)->cos) + (txq)->index)
0420 #define QEDE_NDEV_TXQ_ID_TO_TXQ(edev, idx)  \
0421     (&((edev)->fp_array[QEDE_NDEV_TXQ_ID_TO_FP_ID(edev, idx)].txq \
0422     [QEDE_NDEV_TXQ_ID_TO_TXQ_COS(edev, idx)]))
0423 #define QEDE_FP_TC0_TXQ(fp)     (&((fp)->txq[0]))
0424 
0425     /* Regular Tx requires skb + metadata for release purpose,
0426      * while XDP requires the pages and the mapped address.
0427      */
0428     union {
0429         struct sw_tx_bd     *skbs;
0430         struct sw_tx_xdp    *xdp;
0431     }               sw_tx_ring;
0432 
0433     struct qed_chain        tx_pbl;
0434 
0435     /* Slowpath; Should be kept in end [unless missing padding] */
0436     void                *handle;
0437     u16             cos;
0438     u16             ndev_txq_id;
0439 };
0440 
0441 #define BD_UNMAP_ADDR(bd)       HILO_U64(le32_to_cpu((bd)->addr.hi), \
0442                          le32_to_cpu((bd)->addr.lo))
0443 #define BD_SET_UNMAP_ADDR_LEN(bd, maddr, len)               \
0444     do {                                \
0445         (bd)->addr.hi = cpu_to_le32(upper_32_bits(maddr));  \
0446         (bd)->addr.lo = cpu_to_le32(lower_32_bits(maddr));  \
0447         (bd)->nbytes = cpu_to_le16(len);            \
0448     } while (0)
0449 #define BD_UNMAP_LEN(bd)        (le16_to_cpu((bd)->nbytes))
0450 
0451 struct qede_fastpath {
0452     struct qede_dev         *edev;
0453 
0454     u8              type;
0455 #define QEDE_FASTPATH_TX        BIT(0)
0456 #define QEDE_FASTPATH_RX        BIT(1)
0457 #define QEDE_FASTPATH_XDP       BIT(2)
0458 #define QEDE_FASTPATH_COMBINED      (QEDE_FASTPATH_TX | QEDE_FASTPATH_RX)
0459 
0460     u8              id;
0461 
0462     u8              xdp_xmit;
0463 #define QEDE_XDP_TX         BIT(0)
0464 #define QEDE_XDP_REDIRECT       BIT(1)
0465 
0466     struct napi_struct      napi;
0467     struct qed_sb_info      *sb_info;
0468     struct qede_rx_queue        *rxq;
0469     struct qede_tx_queue        *txq;
0470     struct qede_tx_queue        *xdp_tx;
0471 
0472     char                name[IFNAMSIZ + 8];
0473 };
0474 
0475 /* Debug print definitions */
0476 #define DP_NAME(edev)           netdev_name((edev)->ndev)
0477 
0478 #define XMIT_PLAIN          0
0479 #define XMIT_L4_CSUM            BIT(0)
0480 #define XMIT_LSO            BIT(1)
0481 #define XMIT_ENC            BIT(2)
0482 #define XMIT_ENC_GSO_L4_CSUM        BIT(3)
0483 
0484 #define QEDE_CSUM_ERROR         BIT(0)
0485 #define QEDE_CSUM_UNNECESSARY       BIT(1)
0486 #define QEDE_TUNN_CSUM_UNNECESSARY  BIT(2)
0487 
0488 #define QEDE_SP_RECOVERY        0
0489 #define QEDE_SP_RX_MODE         1
0490 #define QEDE_SP_RSVD1                   2
0491 #define QEDE_SP_RSVD2                   3
0492 #define QEDE_SP_HW_ERR                  4
0493 #define QEDE_SP_ARFS_CONFIG             5
0494 #define QEDE_SP_AER         7
0495 #define QEDE_SP_DISABLE         8
0496 
0497 #ifdef CONFIG_RFS_ACCEL
0498 int qede_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
0499                u16 rxq_index, u32 flow_id);
0500 #define QEDE_SP_TASK_POLL_DELAY (5 * HZ)
0501 #endif
0502 
0503 void qede_process_arfs_filters(struct qede_dev *edev, bool free_fltr);
0504 void qede_poll_for_freeing_arfs_filters(struct qede_dev *edev);
0505 void qede_arfs_filter_op(void *dev, void *filter, u8 fw_rc);
0506 void qede_free_arfs(struct qede_dev *edev);
0507 int qede_alloc_arfs(struct qede_dev *edev);
0508 int qede_add_cls_rule(struct qede_dev *edev, struct ethtool_rxnfc *info);
0509 int qede_delete_flow_filter(struct qede_dev *edev, u64 cookie);
0510 int qede_get_cls_rule_entry(struct qede_dev *edev, struct ethtool_rxnfc *cmd);
0511 int qede_get_cls_rule_all(struct qede_dev *edev, struct ethtool_rxnfc *info,
0512               u32 *rule_locs);
0513 int qede_get_arfs_filter_count(struct qede_dev *edev);
0514 
0515 struct qede_reload_args {
0516     void (*func)(struct qede_dev *edev, struct qede_reload_args *args);
0517     union {
0518         netdev_features_t features;
0519         struct bpf_prog *new_prog;
0520         u16 mtu;
0521     } u;
0522 };
0523 
0524 /* Datapath functions definition */
0525 netdev_tx_t qede_start_xmit(struct sk_buff *skb, struct net_device *ndev);
0526 int qede_xdp_transmit(struct net_device *dev, int n_frames,
0527               struct xdp_frame **frames, u32 flags);
0528 u16 qede_select_queue(struct net_device *dev, struct sk_buff *skb,
0529               struct net_device *sb_dev);
0530 netdev_features_t qede_features_check(struct sk_buff *skb,
0531                       struct net_device *dev,
0532                       netdev_features_t features);
0533 int qede_alloc_rx_buffer(struct qede_rx_queue *rxq, bool allow_lazy);
0534 int qede_free_tx_pkt(struct qede_dev *edev,
0535              struct qede_tx_queue *txq, int *len);
0536 int qede_poll(struct napi_struct *napi, int budget);
0537 irqreturn_t qede_msix_fp_int(int irq, void *fp_cookie);
0538 
0539 /* Filtering function definitions */
0540 void qede_force_mac(void *dev, u8 *mac, bool forced);
0541 void qede_udp_ports_update(void *dev, u16 vxlan_port, u16 geneve_port);
0542 int qede_set_mac_addr(struct net_device *ndev, void *p);
0543 
0544 int qede_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid);
0545 int qede_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid);
0546 void qede_vlan_mark_nonconfigured(struct qede_dev *edev);
0547 int qede_configure_vlan_filters(struct qede_dev *edev);
0548 
0549 netdev_features_t qede_fix_features(struct net_device *dev,
0550                     netdev_features_t features);
0551 int qede_set_features(struct net_device *dev, netdev_features_t features);
0552 void qede_set_rx_mode(struct net_device *ndev);
0553 void qede_config_rx_mode(struct net_device *ndev);
0554 void qede_fill_rss_params(struct qede_dev *edev,
0555               struct qed_update_vport_rss_params *rss, u8 *update);
0556 
0557 void qede_udp_tunnel_add(struct net_device *dev, struct udp_tunnel_info *ti);
0558 void qede_udp_tunnel_del(struct net_device *dev, struct udp_tunnel_info *ti);
0559 
0560 int qede_xdp(struct net_device *dev, struct netdev_bpf *xdp);
0561 
0562 #ifdef CONFIG_DCB
0563 void qede_set_dcbnl_ops(struct net_device *ndev);
0564 #endif
0565 
0566 void qede_config_debug(uint debug, u32 *p_dp_module, u8 *p_dp_level);
0567 void qede_set_ethtool_ops(struct net_device *netdev);
0568 void qede_set_udp_tunnels(struct qede_dev *edev);
0569 void qede_reload(struct qede_dev *edev,
0570          struct qede_reload_args *args, bool is_locked);
0571 int qede_change_mtu(struct net_device *dev, int new_mtu);
0572 void qede_fill_by_demand_stats(struct qede_dev *edev);
0573 void __qede_lock(struct qede_dev *edev);
0574 void __qede_unlock(struct qede_dev *edev);
0575 bool qede_has_rx_work(struct qede_rx_queue *rxq);
0576 int qede_txq_has_work(struct qede_tx_queue *txq);
0577 void qede_recycle_rx_bd_ring(struct qede_rx_queue *rxq, u8 count);
0578 void qede_update_rx_prod(struct qede_dev *edev, struct qede_rx_queue *rxq);
0579 int qede_add_tc_flower_fltr(struct qede_dev *edev, __be16 proto,
0580                 struct flow_cls_offload *f);
0581 
0582 void qede_forced_speed_maps_init(void);
0583 int qede_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal,
0584               struct kernel_ethtool_coalesce *kernel_coal,
0585               struct netlink_ext_ack *extack);
0586 int qede_set_per_coalesce(struct net_device *dev, u32 queue,
0587               struct ethtool_coalesce *coal);
0588 
0589 #define RX_RING_SIZE_POW    13
0590 #define RX_RING_SIZE        ((u16)BIT(RX_RING_SIZE_POW))
0591 #define NUM_RX_BDS_MAX      (RX_RING_SIZE - 1)
0592 #define NUM_RX_BDS_MIN      128
0593 #define NUM_RX_BDS_KDUMP_MIN    63
0594 #define NUM_RX_BDS_DEF      ((u16)BIT(10) - 1)
0595 
0596 #define TX_RING_SIZE_POW    13
0597 #define TX_RING_SIZE        ((u16)BIT(TX_RING_SIZE_POW))
0598 #define NUM_TX_BDS_MAX      (TX_RING_SIZE - 1)
0599 #define NUM_TX_BDS_MIN      128
0600 #define NUM_TX_BDS_KDUMP_MIN    63
0601 #define NUM_TX_BDS_DEF      NUM_TX_BDS_MAX
0602 
0603 #define QEDE_MIN_PKT_LEN        64
0604 #define QEDE_RX_HDR_SIZE        256
0605 #define QEDE_MAX_JUMBO_PACKET_SIZE  9600
0606 #define for_each_queue(i) for (i = 0; i < edev->num_queues; i++)
0607 #define for_each_cos_in_txq(edev, var) \
0608     for ((var) = 0; (var) < (edev)->dev_info.num_tc; (var)++)
0609 
0610 #endif /* _QEDE_H_ */
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