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0007 #ifndef _QED_RDMA_H
0008 #define _QED_RDMA_H
0009 #include <linux/types.h>
0010 #include <linux/bitops.h>
0011 #include <linux/kernel.h>
0012 #include <linux/list.h>
0013 #include <linux/slab.h>
0014 #include <linux/spinlock.h>
0015 #include <linux/qed/qed_if.h>
0016 #include <linux/qed/qed_rdma_if.h>
0017 #include "qed.h"
0018 #include "qed_dev_api.h"
0019 #include "qed_hsi.h"
0020 #include "qed_iwarp.h"
0021 #include "qed_roce.h"
0022
0023 #define QED_RDMA_MAX_P_KEY (1)
0024 #define QED_RDMA_MAX_WQE (0x7FFF)
0025 #define QED_RDMA_MAX_SRQ_WQE_ELEM (0x7FFF)
0026 #define QED_RDMA_PAGE_SIZE_CAPS (0xFFFFF000)
0027 #define QED_RDMA_ACK_DELAY (15)
0028 #define QED_RDMA_MAX_MR_SIZE (0x10000000000ULL)
0029 #define QED_RDMA_MAX_CQS (RDMA_MAX_CQS)
0030 #define QED_RDMA_MAX_MRS (RDMA_MAX_TIDS)
0031
0032 #define QED_RDMA_MAX_SRQ_ELEM_PER_WQE (RDMA_MAX_SGE_PER_RQ_WQE + 1)
0033 #define QED_RDMA_MAX_SGE_PER_SRQ_WQE (RDMA_MAX_SGE_PER_RQ_WQE)
0034 #define QED_RDMA_SRQ_WQE_ELEM_SIZE (16)
0035 #define QED_RDMA_MAX_SRQS (32 * 1024)
0036
0037 #define QED_RDMA_MAX_CQE_32_BIT (0x7FFFFFFF - 1)
0038 #define QED_RDMA_MAX_CQE_16_BIT (0x7FFF - 1)
0039
0040
0041
0042
0043 #define QED_RDMA_MAX_XRCDS (roundup_pow_of_two(RDMA_MAX_XRC_SRQS))
0044
0045 enum qed_rdma_toggle_bit {
0046 QED_RDMA_TOGGLE_BIT_CLEAR = 0,
0047 QED_RDMA_TOGGLE_BIT_SET = 1
0048 };
0049
0050 #define QED_RDMA_MAX_BMAP_NAME (10)
0051 struct qed_bmap {
0052 unsigned long *bitmap;
0053 u32 max_count;
0054 char name[QED_RDMA_MAX_BMAP_NAME];
0055 };
0056
0057 struct qed_rdma_info {
0058
0059 spinlock_t lock;
0060
0061 struct qed_bmap cq_map;
0062 struct qed_bmap pd_map;
0063 struct qed_bmap xrcd_map;
0064 struct qed_bmap tid_map;
0065 struct qed_bmap qp_map;
0066 struct qed_bmap srq_map;
0067 struct qed_bmap xrc_srq_map;
0068 struct qed_bmap cid_map;
0069 struct qed_bmap tcp_cid_map;
0070 struct qed_bmap real_cid_map;
0071 struct qed_bmap dpi_map;
0072 struct qed_bmap toggle_bits;
0073 struct qed_rdma_events events;
0074 struct qed_rdma_device *dev;
0075 struct qed_rdma_port *port;
0076 u32 last_tid;
0077 u8 num_cnqs;
0078 u32 num_qps;
0079 u32 num_mrs;
0080 u32 num_srqs;
0081 u16 srq_id_offset;
0082 u16 queue_zone_base;
0083 u16 max_queue_zones;
0084 enum protocol_type proto;
0085 struct qed_iwarp_info iwarp;
0086 u8 active:1;
0087 };
0088
0089 struct qed_rdma_qp {
0090 struct regpair qp_handle;
0091 struct regpair qp_handle_async;
0092 u32 qpid;
0093 u16 icid;
0094 enum qed_roce_qp_state cur_state;
0095 enum qed_rdma_qp_type qp_type;
0096 enum qed_iwarp_qp_state iwarp_state;
0097 bool use_srq;
0098 bool signal_all;
0099 bool fmr_and_reserved_lkey;
0100
0101 bool incoming_rdma_read_en;
0102 bool incoming_rdma_write_en;
0103 bool incoming_atomic_en;
0104 bool e2e_flow_control_en;
0105
0106 u16 pd;
0107 u16 pkey;
0108 u32 dest_qp;
0109 u16 mtu;
0110 u16 srq_id;
0111 u8 traffic_class_tos;
0112 u8 hop_limit_ttl;
0113 u16 dpi;
0114 u32 flow_label;
0115 bool lb_indication;
0116 u16 vlan_id;
0117 u32 ack_timeout;
0118 u8 retry_cnt;
0119 u8 rnr_retry_cnt;
0120 u8 min_rnr_nak_timer;
0121 bool sqd_async;
0122 union qed_gid sgid;
0123 union qed_gid dgid;
0124 enum roce_mode roce_mode;
0125 u16 udp_src_port;
0126 u8 stats_queue;
0127
0128
0129 u8 max_rd_atomic_req;
0130 u32 sq_psn;
0131 u16 sq_cq_id;
0132 u16 sq_num_pages;
0133 dma_addr_t sq_pbl_ptr;
0134 void *orq;
0135 dma_addr_t orq_phys_addr;
0136 u8 orq_num_pages;
0137 bool req_offloaded;
0138 bool has_req;
0139
0140
0141 u8 max_rd_atomic_resp;
0142 u32 rq_psn;
0143 u16 rq_cq_id;
0144 u16 rq_num_pages;
0145 u16 xrcd_id;
0146 dma_addr_t rq_pbl_ptr;
0147 void *irq;
0148 dma_addr_t irq_phys_addr;
0149 u8 irq_num_pages;
0150 bool resp_offloaded;
0151 u32 cq_prod;
0152 bool has_resp;
0153
0154 u8 remote_mac_addr[6];
0155 u8 local_mac_addr[6];
0156
0157 void *shared_queue;
0158 dma_addr_t shared_queue_phys_addr;
0159 struct qed_iwarp_ep *ep;
0160 u8 edpm_mode;
0161 };
0162
0163 static inline bool qed_rdma_is_xrc_qp(struct qed_rdma_qp *qp)
0164 {
0165 if (qp->qp_type == QED_RDMA_QP_TYPE_XRC_TGT ||
0166 qp->qp_type == QED_RDMA_QP_TYPE_XRC_INI)
0167 return true;
0168
0169 return false;
0170 }
0171
0172 #if IS_ENABLED(CONFIG_QED_RDMA)
0173 void qed_rdma_dpm_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
0174 void qed_rdma_dpm_conf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
0175 int qed_rdma_info_alloc(struct qed_hwfn *p_hwfn);
0176 void qed_rdma_info_free(struct qed_hwfn *p_hwfn);
0177 #else
0178 static inline void qed_rdma_dpm_conf(struct qed_hwfn *p_hwfn,
0179 struct qed_ptt *p_ptt) {}
0180 static inline void qed_rdma_dpm_bar(struct qed_hwfn *p_hwfn,
0181 struct qed_ptt *p_ptt) {}
0182 static inline int qed_rdma_info_alloc(struct qed_hwfn *p_hwfn)
0183 {return -EINVAL; }
0184 static inline void qed_rdma_info_free(struct qed_hwfn *p_hwfn) {}
0185 #endif
0186
0187 int
0188 qed_rdma_bmap_alloc(struct qed_hwfn *p_hwfn,
0189 struct qed_bmap *bmap, u32 max_count, char *name);
0190
0191 void
0192 qed_rdma_bmap_free(struct qed_hwfn *p_hwfn, struct qed_bmap *bmap, bool check);
0193
0194 int
0195 qed_rdma_bmap_alloc_id(struct qed_hwfn *p_hwfn,
0196 struct qed_bmap *bmap, u32 *id_num);
0197
0198 void
0199 qed_bmap_set_id(struct qed_hwfn *p_hwfn, struct qed_bmap *bmap, u32 id_num);
0200
0201 void
0202 qed_bmap_release_id(struct qed_hwfn *p_hwfn, struct qed_bmap *bmap, u32 id_num);
0203
0204 int
0205 qed_bmap_test_id(struct qed_hwfn *p_hwfn, struct qed_bmap *bmap, u32 id_num);
0206
0207 void qed_rdma_set_fw_mac(__le16 *p_fw_mac, const u8 *p_qed_mac);
0208
0209 bool qed_rdma_allocated_qps(struct qed_hwfn *p_hwfn);
0210 #endif