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0001 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
0002 /* QLogic qed NIC Driver
0003  * Copyright (c) 2019-2021 Marvell International Ltd.
0004  */
0005 
0006 #ifndef _QED_IRO_HSI_H
0007 #define _QED_IRO_HSI_H
0008 
0009 #include <linux/types.h>
0010 
0011 enum {
0012     IRO_YSTORM_FLOW_CONTROL_MODE_GTT,
0013     IRO_PSTORM_PKT_DUPLICATION_CFG,
0014     IRO_TSTORM_PORT_STAT,
0015     IRO_TSTORM_LL2_PORT_STAT,
0016     IRO_TSTORM_PKT_DUPLICATION_CFG,
0017     IRO_USTORM_VF_PF_CHANNEL_READY_GTT,
0018     IRO_USTORM_FLR_FINAL_ACK_GTT,
0019     IRO_USTORM_EQE_CONS_GTT,
0020     IRO_USTORM_ETH_QUEUE_ZONE_GTT,
0021     IRO_USTORM_COMMON_QUEUE_CONS_GTT,
0022     IRO_XSTORM_PQ_INFO,
0023     IRO_XSTORM_INTEG_TEST_DATA,
0024     IRO_YSTORM_INTEG_TEST_DATA,
0025     IRO_PSTORM_INTEG_TEST_DATA,
0026     IRO_TSTORM_INTEG_TEST_DATA,
0027     IRO_MSTORM_INTEG_TEST_DATA,
0028     IRO_USTORM_INTEG_TEST_DATA,
0029     IRO_XSTORM_OVERLAY_BUF_ADDR,
0030     IRO_YSTORM_OVERLAY_BUF_ADDR,
0031     IRO_PSTORM_OVERLAY_BUF_ADDR,
0032     IRO_TSTORM_OVERLAY_BUF_ADDR,
0033     IRO_MSTORM_OVERLAY_BUF_ADDR,
0034     IRO_USTORM_OVERLAY_BUF_ADDR,
0035     IRO_TSTORM_LL2_RX_PRODS_GTT,
0036     IRO_CORE_LL2_TSTORM_PER_QUEUE_STAT,
0037     IRO_CORE_LL2_USTORM_PER_QUEUE_STAT,
0038     IRO_CORE_LL2_PSTORM_PER_QUEUE_STAT,
0039     IRO_MSTORM_QUEUE_STAT,
0040     IRO_MSTORM_TPA_TIMEOUT_US,
0041     IRO_MSTORM_ETH_VF_PRODS,
0042     IRO_MSTORM_ETH_PF_PRODS_GTT,
0043     IRO_MSTORM_ETH_PF_STAT,
0044     IRO_USTORM_QUEUE_STAT,
0045     IRO_USTORM_ETH_PF_STAT,
0046     IRO_PSTORM_QUEUE_STAT,
0047     IRO_PSTORM_ETH_PF_STAT,
0048     IRO_PSTORM_CTL_FRAME_ETHTYPE_GTT,
0049     IRO_TSTORM_ETH_PRS_INPUT,
0050     IRO_ETH_RX_RATE_LIMIT,
0051     IRO_TSTORM_ETH_RSS_UPDATE_GTT,
0052     IRO_XSTORM_ETH_QUEUE_ZONE_GTT,
0053     IRO_YSTORM_TOE_CQ_PROD,
0054     IRO_USTORM_TOE_CQ_PROD,
0055     IRO_USTORM_TOE_GRQ_PROD,
0056     IRO_TSTORM_SCSI_CMDQ_CONS_GTT,
0057     IRO_TSTORM_SCSI_BDQ_EXT_PROD_GTT,
0058     IRO_MSTORM_SCSI_BDQ_EXT_PROD_GTT,
0059     IRO_TSTORM_ISCSI_RX_STATS,
0060     IRO_MSTORM_ISCSI_RX_STATS,
0061     IRO_USTORM_ISCSI_RX_STATS,
0062     IRO_XSTORM_ISCSI_TX_STATS,
0063     IRO_YSTORM_ISCSI_TX_STATS,
0064     IRO_PSTORM_ISCSI_TX_STATS,
0065     IRO_TSTORM_FCOE_RX_STATS,
0066     IRO_PSTORM_FCOE_TX_STATS,
0067     IRO_PSTORM_RDMA_QUEUE_STAT,
0068     IRO_TSTORM_RDMA_QUEUE_STAT,
0069     IRO_XSTORM_RDMA_ASSERT_LEVEL,
0070     IRO_YSTORM_RDMA_ASSERT_LEVEL,
0071     IRO_PSTORM_RDMA_ASSERT_LEVEL,
0072     IRO_TSTORM_RDMA_ASSERT_LEVEL,
0073     IRO_MSTORM_RDMA_ASSERT_LEVEL,
0074     IRO_USTORM_RDMA_ASSERT_LEVEL,
0075     IRO_XSTORM_IWARP_RXMIT_STATS,
0076     IRO_TSTORM_ROCE_EVENTS_STAT,
0077     IRO_YSTORM_ROCE_DCQCN_RECEIVED_STATS,
0078     IRO_YSTORM_ROCE_ERROR_STATS,
0079     IRO_PSTORM_ROCE_DCQCN_SENT_STATS,
0080     IRO_USTORM_ROCE_CQE_STATS,
0081 };
0082 
0083 /* Pstorm LiteL2 queue statistics */
0084 
0085 #define CORE_LL2_PSTORM_PER_QUEUE_STAT_OFFSET(core_tx_stats_id) \
0086     (IRO[IRO_CORE_LL2_PSTORM_PER_QUEUE_STAT].base           \
0087     + ((core_tx_stats_id) * IRO[IRO_CORE_LL2_PSTORM_PER_QUEUE_STAT].m1))
0088 #define CORE_LL2_PSTORM_PER_QUEUE_STAT_SIZE \
0089                 (IRO[IRO_CORE_LL2_PSTORM_PER_QUEUE_STAT].size)
0090 
0091 /* Tstorm LightL2 queue statistics */
0092 #define CORE_LL2_TSTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) \
0093     (IRO[IRO_CORE_LL2_TSTORM_PER_QUEUE_STAT].base           \
0094      + ((core_rx_queue_id) * IRO[IRO_CORE_LL2_TSTORM_PER_QUEUE_STAT].m1))
0095 #define CORE_LL2_TSTORM_PER_QUEUE_STAT_SIZE \
0096                 (IRO[IRO_CORE_LL2_TSTORM_PER_QUEUE_STAT].size)
0097 
0098 /* Ustorm LiteL2 queue statistics */
0099 #define CORE_LL2_USTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) \
0100     (IRO[IRO_CORE_LL2_USTORM_PER_QUEUE_STAT].base           \
0101      + ((core_rx_queue_id) * IRO[IRO_CORE_LL2_USTORM_PER_QUEUE_STAT].m1))
0102 #define CORE_LL2_USTORM_PER_QUEUE_STAT_SIZE \
0103                 (IRO[IRO_CORE_LL2_USTORM_PER_QUEUE_STAT].size)
0104 
0105 /* Tstorm Eth limit Rx rate */
0106 #define ETH_RX_RATE_LIMIT_OFFSET(pf_id)  \
0107     (IRO[IRO_ETH_RX_RATE_LIMIT].base \
0108      + ((pf_id) * IRO[IRO_ETH_RX_RATE_LIMIT].m1))
0109 #define ETH_RX_RATE_LIMIT_SIZE (IRO[IRO_ETH_RX_RATE_LIMIT].size)
0110 
0111 /* Mstorm ETH PF queues producers */
0112 #define MSTORM_ETH_PF_PRODS_GTT_OFFSET(queue_id) \
0113     (IRO[IRO_MSTORM_ETH_PF_PRODS_GTT].base   \
0114      + ((queue_id) * IRO[IRO_MSTORM_ETH_PF_PRODS_GTT].m1))
0115 #define MSTORM_ETH_PF_PRODS_GTT_SIZE (IRO[IRO_MSTORM_ETH_PF_PRODS_GTT].size)
0116 
0117 /* Mstorm pf statistics */
0118 #define MSTORM_ETH_PF_STAT_OFFSET(pf_id)  \
0119     (IRO[IRO_MSTORM_ETH_PF_STAT].base \
0120      + ((pf_id) * IRO[IRO_MSTORM_ETH_PF_STAT].m1))
0121 #define MSTORM_ETH_PF_STAT_SIZE (IRO[IRO_MSTORM_ETH_PF_STAT].size)
0122 
0123 /* Mstorm ETH VF queues producers offset in RAM. Used in default VF zone
0124  * size mode.
0125  */
0126 #define MSTORM_ETH_VF_PRODS_OFFSET(vf_id, vf_queue_id) \
0127     (IRO[IRO_MSTORM_ETH_VF_PRODS].base             \
0128      + ((vf_id) * IRO[IRO_MSTORM_ETH_VF_PRODS].m1) \
0129      + ((vf_queue_id) * IRO[IRO_MSTORM_ETH_VF_PRODS].m2))
0130 #define MSTORM_ETH_VF_PRODS_SIZE (IRO[IRO_MSTORM_ETH_VF_PRODS].size)
0131 
0132 /* Mstorm Integration Test Data */
0133 #define MSTORM_INTEG_TEST_DATA_OFFSET (IRO[IRO_MSTORM_INTEG_TEST_DATA].base)
0134 #define MSTORM_INTEG_TEST_DATA_SIZE (IRO[IRO_MSTORM_INTEG_TEST_DATA].size)
0135 
0136 /* Mstorm iSCSI RX stats */
0137 #define MSTORM_ISCSI_RX_STATS_OFFSET(storage_func_id) \
0138     (IRO[IRO_MSTORM_ISCSI_RX_STATS].base          \
0139      + ((storage_func_id) * IRO[IRO_MSTORM_ISCSI_RX_STATS].m1))
0140 #define MSTORM_ISCSI_RX_STATS_SIZE (IRO[IRO_MSTORM_ISCSI_RX_STATS].size)
0141 
0142 /* Mstorm overlay buffer host address */
0143 #define MSTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[IRO_MSTORM_OVERLAY_BUF_ADDR].base)
0144 #define MSTORM_OVERLAY_BUF_ADDR_SIZE (IRO[IRO_MSTORM_OVERLAY_BUF_ADDR].size)
0145 
0146 /* Mstorm queue statistics */
0147 #define MSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
0148     (IRO[IRO_MSTORM_QUEUE_STAT].base          \
0149      + ((stat_counter_id) * IRO[IRO_MSTORM_QUEUE_STAT].m1))
0150 #define MSTORM_QUEUE_STAT_SIZ (IRO[IRO_MSTORM_QUEUE_STAT].size)
0151 
0152 /* Mstorm error level for assert */
0153 #define MSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id)  \
0154     (IRO[IRO_MSTORM_RDMA_ASSERT_LEVEL].base \
0155      + ((pf_id) * IRO[IRO_MSTORM_RDMA_ASSERT_LEVEL].m1))
0156 #define MSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[IRO_MSTORM_RDMA_ASSERT_LEVEL].size)
0157 
0158 /* Mstorm bdq-external-producer of given BDQ resource ID, BDqueue-id */
0159 #define MSTORM_SCSI_BDQ_EXT_PROD_GTT_OFFSET(storage_func_id, bdq_id)      \
0160     (IRO[IRO_MSTORM_SCSI_BDQ_EXT_PROD_GTT].base                       \
0161      + ((storage_func_id) * IRO[IRO_MSTORM_SCSI_BDQ_EXT_PROD_GTT].m1) \
0162      + ((bdq_id) * IRO[IRO_MSTORM_SCSI_BDQ_EXT_PROD_GTT].m2))
0163 #define MSTORM_SCSI_BDQ_EXT_PROD_GTT_SIZE \
0164                 (IRO[IRO_MSTORM_SCSI_BDQ_EXT_PROD_GTT].size)
0165 
0166 /* TPA agregation timeout in us resolution (on ASIC) */
0167 #define MSTORM_TPA_TIMEOUT_US_OFFSET (IRO[IRO_MSTORM_TPA_TIMEOUT_US].base)
0168 #define MSTORM_TPA_TIMEOUT_US_SIZE (IRO[IRO_MSTORM_TPA_TIMEOUT_US].size)
0169 
0170 /* Control frame's EthType configuration for TX control frame security */
0171 #define PSTORM_CTL_FRAME_ETHTYPE_GTT_OFFSET(ethtype_id) \
0172     (IRO[IRO_PSTORM_CTL_FRAME_ETHTYPE_GTT].base     \
0173      + ((ethtype_id) * IRO[IRO_PSTORM_CTL_FRAME_ETHTYPE_GTT].m1))
0174 #define PSTORM_CTL_FRAME_ETHTYPE_GTT_SIZE \
0175                 (IRO[IRO_PSTORM_CTL_FRAME_ETHTYPE_GTT].size)
0176 
0177 /* Pstorm pf statistics */
0178 #define PSTORM_ETH_PF_STAT_OFFSET(pf_id)  \
0179     (IRO[IRO_PSTORM_ETH_PF_STAT].base \
0180      + ((pf_id) * IRO[IRO_PSTORM_ETH_PF_STAT].m1))
0181 #define PSTORM_ETH_PF_STAT_SIZE (IRO[IRO_PSTORM_ETH_PF_STAT].size)
0182 
0183 /* Pstorm FCoE TX stats */
0184 #define PSTORM_FCOE_TX_STATS_OFFSET(pf_id)  \
0185     (IRO[IRO_PSTORM_FCOE_TX_STATS].base \
0186      + ((pf_id) * IRO[IRO_PSTORM_FCOE_TX_STATS].m1))
0187 #define PSTORM_FCOE_TX_STATS_SIZE (IRO[IRO_PSTORM_FCOE_TX_STATS].size)
0188 
0189 /* Pstorm Integration Test Data */
0190 #define PSTORM_INTEG_TEST_DATA_OFFSET (IRO[IRO_PSTORM_INTEG_TEST_DATA].base)
0191 #define PSTORM_INTEG_TEST_DATA_SIZE (IRO[IRO_PSTORM_INTEG_TEST_DATA].size)
0192 
0193 /* Pstorm iSCSI TX stats */
0194 #define PSTORM_ISCSI_TX_STATS_OFFSET(storage_func_id) \
0195     (IRO[IRO_PSTORM_ISCSI_TX_STATS].base          \
0196      + ((storage_func_id) * IRO[IRO_PSTORM_ISCSI_TX_STATS].m1))
0197 #define PSTORM_ISCSI_TX_STATS_SIZE (IRO[IRO_PSTORM_ISCSI_TX_STATS].size)
0198 
0199 /* Pstorm overlay buffer host address */
0200 #define PSTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[IRO_PSTORM_OVERLAY_BUF_ADDR].base)
0201 #define PSTORM_OVERLAY_BUF_ADDR_SIZE (IRO[IRO_PSTORM_OVERLAY_BUF_ADDR].size)
0202 
0203 /* Pstorm LL2 packet duplication configuration. Use pstorm_pkt_dup_cfg
0204  * data type.
0205  */
0206 #define PSTORM_PKT_DUPLICATION_CFG_OFFSET(pf_id) \
0207     (IRO[IRO_PSTORM_PKT_DUPLICATION_CFG].base \
0208     + ((pf_id) * IRO[IRO_PSTORM_PKT_DUPLICATION_CFG].m1))
0209 #define PSTORM_PKT_DUPLICATION_CFG_SIZE \
0210                 (IRO[IRO_PSTORM_PKT_DUPLICATION_CFG].size)
0211 
0212 /* Pstorm queue statistics */
0213 #define PSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
0214     (IRO[IRO_PSTORM_QUEUE_STAT].base          \
0215      + ((stat_counter_id) * IRO[IRO_PSTORM_QUEUE_STAT].m1))
0216 #define PSTORM_QUEUE_STAT_SIZE (IRO[IRO_PSTORM_QUEUE_STAT].size)
0217 
0218 /* Pstorm error level for assert */
0219 #define PSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id)  \
0220     (IRO[IRO_PSTORM_RDMA_ASSERT_LEVEL].base \
0221      + ((pf_id) * IRO[IRO_PSTORM_RDMA_ASSERT_LEVEL].m1))
0222 #define PSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[IRO_PSTORM_RDMA_ASSERT_LEVEL].size)
0223 
0224 /* Pstorm RDMA queue statistics */
0225 #define PSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) \
0226     (IRO[IRO_PSTORM_RDMA_QUEUE_STAT].base               \
0227      + ((rdma_stat_counter_id) * IRO[IRO_PSTORM_RDMA_QUEUE_STAT].m1))
0228 #define PSTORM_RDMA_QUEUE_STAT_SIZE (IRO[IRO_PSTORM_RDMA_QUEUE_STAT].size)
0229 
0230 /* DCQCN Sent Statistics */
0231 #define PSTORM_ROCE_DCQCN_SENT_STATS_OFFSET(roce_pf_id) \
0232     (IRO[IRO_PSTORM_ROCE_DCQCN_SENT_STATS].base     \
0233      + ((roce_pf_id) * IRO[IRO_PSTORM_ROCE_DCQCN_SENT_STATS].m1))
0234 #define PSTORM_ROCE_DCQCN_SENT_STATS_SIZE \
0235                 (IRO[IRO_PSTORM_ROCE_DCQCN_SENT_STATS].size)
0236 
0237 /* Tstorm last parser message */
0238 #define TSTORM_ETH_PRS_INPUT_OFFSET (IRO[IRO_TSTORM_ETH_PRS_INPUT].base)
0239 #define TSTORM_ETH_PRS_INPUT_SIZE (IRO[IRO_TSTORM_ETH_PRS_INPUT].size)
0240 
0241 /* RSS indirection table entry update command per PF offset in TSTORM PF BAR0.
0242  * Use eth_tstorm_rss_update_data for update.
0243  */
0244 #define TSTORM_ETH_RSS_UPDATE_GTT_OFFSET(pf_id)  \
0245     (IRO[IRO_TSTORM_ETH_RSS_UPDATE_GTT].base \
0246      + ((pf_id) * IRO[IRO_TSTORM_ETH_RSS_UPDATE_GTT].m1))
0247 #define TSTORM_ETH_RSS_UPDATE_GTT_SIZE\
0248                 (IRO[IRO_TSTORM_ETH_RSS_UPDATE_GTT].size)
0249 
0250 /* Tstorm FCoE RX stats */
0251 #define TSTORM_FCOE_RX_STATS_OFFSET(pf_id)  \
0252     (IRO[IRO_TSTORM_FCOE_RX_STATS].base \
0253      + ((pf_id) * IRO[IRO_TSTORM_FCOE_RX_STATS].m1))
0254 #define TSTORM_FCOE_RX_STATS_SIZE (IRO[IRO_TSTORM_FCOE_RX_STATS].size)
0255 
0256 /* Tstorm Integration Test Data */
0257 #define TSTORM_INTEG_TEST_DATA_OFFSET (IRO[IRO_TSTORM_INTEG_TEST_DATA].base)
0258 #define TSTORM_INTEG_TEST_DATA_SIZE (IRO[IRO_TSTORM_INTEG_TEST_DATA].size)
0259 
0260 /* Tstorm iSCSI RX stats */
0261 #define TSTORM_ISCSI_RX_STATS_OFFSET(storage_func_id) \
0262     (IRO[IRO_TSTORM_ISCSI_RX_STATS].base          \
0263      + ((storage_func_id) * IRO[IRO_TSTORM_ISCSI_RX_STATS].m1))
0264 #define TSTORM_ISCSI_RX_STATS_SIZE (IRO[IRO_TSTORM_ISCSI_RX_STATS].size)
0265 
0266 /* Tstorm ll2 port statistics */
0267 #define TSTORM_LL2_PORT_STAT_OFFSET(port_id) \
0268     (IRO[IRO_TSTORM_LL2_PORT_STAT].base  \
0269      + ((port_id) * IRO[IRO_TSTORM_LL2_PORT_STAT].m1))
0270 #define TSTORM_LL2_PORT_STAT_SIZE (IRO[IRO_TSTORM_LL2_PORT_STAT].size)
0271 
0272 /* Tstorm producers */
0273 #define TSTORM_LL2_RX_PRODS_GTT_OFFSET(core_rx_queue_id) \
0274     (IRO[IRO_TSTORM_LL2_RX_PRODS_GTT].base           \
0275      + ((core_rx_queue_id) * IRO[IRO_TSTORM_LL2_RX_PRODS_GTT].m1))
0276 #define TSTORM_LL2_RX_PRODS_GTT_SIZE (IRO[IRO_TSTORM_LL2_RX_PRODS_GTT].size)
0277 
0278 /* Tstorm overlay buffer host address */
0279 #define TSTORM_OVERLAY_BUF_ADDR_OFFSET  (IRO[IRO_TSTORM_OVERLAY_BUF_ADDR].base)
0280 
0281 #define TSTORM_OVERLAY_BUF_ADDR_SIZE (IRO[IRO_TSTORM_OVERLAY_BUF_ADDR].size)
0282 
0283 /* Tstorm LL2 packet duplication configuration.
0284  * Use tstorm_pkt_dup_cfg data type.
0285  */
0286 #define TSTORM_PKT_DUPLICATION_CFG_OFFSET(pf_id)  \
0287     (IRO[IRO_TSTORM_PKT_DUPLICATION_CFG].base \
0288     + ((pf_id) * IRO[IRO_TSTORM_PKT_DUPLICATION_CFG].m1))
0289 #define TSTORM_PKT_DUPLICATION_CFG_SIZE \
0290                 (IRO[IRO_TSTORM_PKT_DUPLICATION_CFG].size)
0291 
0292 /* Tstorm port statistics */
0293 #define TSTORM_PORT_STAT_OFFSET(port_id) \
0294     (IRO[IRO_TSTORM_PORT_STAT].base  \
0295      + ((port_id) * IRO[IRO_TSTORM_PORT_STAT].m1))
0296 #define TSTORM_PORT_STAT_SIZE (IRO[IRO_TSTORM_PORT_STAT].size)
0297 
0298 /* Tstorm error level for assert */
0299 #define TSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id)  \
0300     (IRO[IRO_TSTORM_RDMA_ASSERT_LEVEL].base \
0301      + ((pf_id) * IRO[IRO_TSTORM_RDMA_ASSERT_LEVEL].m1))
0302 #define TSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[IRO_TSTORM_RDMA_ASSERT_LEVEL].size)
0303 
0304 /* Tstorm RDMA queue statistics */
0305 #define TSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) \
0306     (IRO[IRO_TSTORM_RDMA_QUEUE_STAT].base               \
0307      + ((rdma_stat_counter_id) * IRO[IRO_TSTORM_RDMA_QUEUE_STAT].m1))
0308 #define TSTORM_RDMA_QUEUE_STAT_SIZE (IRO[IRO_TSTORM_RDMA_QUEUE_STAT].size)
0309 
0310 /* Tstorm RoCE Event Statistics */
0311 #define TSTORM_ROCE_EVENTS_STAT_OFFSET(roce_pf_id) \
0312     (IRO[IRO_TSTORM_ROCE_EVENTS_STAT].base     \
0313      + ((roce_pf_id) * IRO[IRO_TSTORM_ROCE_EVENTS_STAT].m1))
0314 #define TSTORM_ROCE_EVENTS_STAT_SIZE (IRO[IRO_TSTORM_ROCE_EVENTS_STAT].size)
0315 
0316 /* Tstorm (reflects M-Storm) bdq-external-producer of given function ID,
0317  * BDqueue-id.
0318  */
0319 #define TSTORM_SCSI_BDQ_EXT_PROD_GTT_OFFSET(storage_func_id, bdq_id)      \
0320     (IRO[IRO_TSTORM_SCSI_BDQ_EXT_PROD_GTT].base                       \
0321      + ((storage_func_id) * IRO[IRO_TSTORM_SCSI_BDQ_EXT_PROD_GTT].m1) \
0322      + ((bdq_id) * IRO[IRO_TSTORM_SCSI_BDQ_EXT_PROD_GTT].m2))
0323 #define TSTORM_SCSI_BDQ_EXT_PROD_GTT_SIZE \
0324                 (IRO[IRO_TSTORM_SCSI_BDQ_EXT_PROD_GTT].size)
0325 
0326 /* Tstorm cmdq-cons of given command queue-id */
0327 #define TSTORM_SCSI_CMDQ_CONS_GTT_OFFSET(cmdq_queue_id) \
0328     (IRO[IRO_TSTORM_SCSI_CMDQ_CONS_GTT].base        \
0329      + ((cmdq_queue_id) * IRO[IRO_TSTORM_SCSI_CMDQ_CONS_GTT].m1))
0330 #define TSTORM_SCSI_CMDQ_CONS_GTT_SIZE \
0331                 (IRO[IRO_TSTORM_SCSI_CMDQ_CONS_GTT].size)
0332 
0333 /* Ustorm Common Queue ring consumer */
0334 #define USTORM_COMMON_QUEUE_CONS_GTT_OFFSET(queue_zone_id) \
0335     (IRO[IRO_USTORM_COMMON_QUEUE_CONS_GTT].base        \
0336      + ((queue_zone_id) * IRO[IRO_USTORM_COMMON_QUEUE_CONS_GTT].m1))
0337 #define USTORM_COMMON_QUEUE_CONS_GTT_SIZE \
0338                 (IRO[IRO_USTORM_COMMON_QUEUE_CONS_GTT].size)
0339 
0340 /* Ustorm Event ring consumer */
0341 #define USTORM_EQE_CONS_GTT_OFFSET(pf_id)  \
0342     (IRO[IRO_USTORM_EQE_CONS_GTT].base \
0343      + ((pf_id) * IRO[IRO_USTORM_EQE_CONS_GTT].m1))
0344 #define USTORM_EQE_CONS_GTT_SIZE (IRO[IRO_USTORM_EQE_CONS_GTT].size)
0345 
0346 /* Ustorm pf statistics */
0347 #define USTORM_ETH_PF_STAT_OFFSET(pf_id)  \
0348     (IRO[IRO_USTORM_ETH_PF_STAT].base \
0349      + ((pf_id) * IRO[IRO_USTORM_ETH_PF_STAT].m1))
0350 #define USTORM_ETH_PF_STAT_SIZE (IRO[IRO_USTORM_ETH_PF_STAT].size)
0351 
0352 /* Ustorm eth queue zone */
0353 #define USTORM_ETH_QUEUE_ZONE_GTT_OFFSET(queue_zone_id) \
0354     (IRO[IRO_USTORM_ETH_QUEUE_ZONE_GTT].base        \
0355      + ((queue_zone_id) * IRO[IRO_USTORM_ETH_QUEUE_ZONE_GTT].m1))
0356 #define USTORM_ETH_QUEUE_ZONE_GTT_SIZE (IRO[IRO_USTORM_ETH_QUEUE_ZONE_GTT].size)
0357 
0358 /* Ustorm Final flr cleanup ack */
0359 #define USTORM_FLR_FINAL_ACK_GTT_OFFSET(pf_id)  \
0360     (IRO[IRO_USTORM_FLR_FINAL_ACK_GTT].base \
0361      + ((pf_id) * IRO[IRO_USTORM_FLR_FINAL_ACK_GTT].m1))
0362 #define USTORM_FLR_FINAL_ACK_GTT_SIZE (IRO[IRO_USTORM_FLR_FINAL_ACK_GTT].size)
0363 
0364 /* Ustorm Integration Test Data */
0365 #define USTORM_INTEG_TEST_DATA_OFFSET (IRO[IRO_USTORM_INTEG_TEST_DATA].base)
0366 #define USTORM_INTEG_TEST_DATA_SIZE (IRO[IRO_USTORM_INTEG_TEST_DATA].size)
0367 
0368 /* Ustorm iSCSI RX stats */
0369 #define USTORM_ISCSI_RX_STATS_OFFSET(storage_func_id) \
0370     (IRO[IRO_USTORM_ISCSI_RX_STATS].base          \
0371      + ((storage_func_id) * IRO[IRO_USTORM_ISCSI_RX_STATS].m1))
0372 #define USTORM_ISCSI_RX_STATS_SIZE (IRO[IRO_USTORM_ISCSI_RX_STATS].size)
0373 
0374 /* Ustorm overlay buffer host address */
0375 #define USTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[IRO_USTORM_OVERLAY_BUF_ADDR].base)
0376 #define USTORM_OVERLAY_BUF_ADDR_SIZE (IRO[IRO_USTORM_OVERLAY_BUF_ADDR].size)
0377 
0378 /* Ustorm queue statistics */
0379 #define USTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
0380     (IRO[IRO_USTORM_QUEUE_STAT].base          \
0381      + ((stat_counter_id) * IRO[IRO_USTORM_QUEUE_STAT].m1))
0382 #define USTORM_QUEUE_STAT_SIZE (IRO[IRO_USTORM_QUEUE_STAT].size)
0383 
0384 /* Ustorm error level for assert */
0385 #define USTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id)  \
0386     (IRO[IRO_USTORM_RDMA_ASSERT_LEVEL].base \
0387      + ((pf_id) * IRO[IRO_USTORM_RDMA_ASSERT_LEVEL].m1))
0388 #define USTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[IRO_USTORM_RDMA_ASSERT_LEVEL].size)
0389 
0390 /* RoCE CQEs Statistics */
0391 #define USTORM_ROCE_CQE_STATS_OFFSET(roce_pf_id) \
0392     (IRO[IRO_USTORM_ROCE_CQE_STATS].base     \
0393      + ((roce_pf_id) * IRO[IRO_USTORM_ROCE_CQE_STATS].m1))
0394 #define USTORM_ROCE_CQE_STATS_SIZE (IRO[IRO_USTORM_ROCE_CQE_STATS].size)
0395 
0396 /* Ustorm cqe producer */
0397 #define USTORM_TOE_CQ_PROD_OFFSET(rss_id) \
0398     (IRO[IRO_USTORM_TOE_CQ_PROD].base \
0399      + ((rss_id) * IRO[IRO_USTORM_TOE_CQ_PROD].m1))
0400 #define USTORM_TOE_CQ_PROD_SIZE (IRO[IRO_USTORM_TOE_CQ_PROD].size)
0401 
0402 /* Ustorm grq producer */
0403 #define USTORM_TOE_GRQ_PROD_OFFSET(pf_id)  \
0404     (IRO[IRO_USTORM_TOE_GRQ_PROD].base \
0405      + ((pf_id) * IRO[IRO_USTORM_TOE_GRQ_PROD].m1))
0406 #define USTORM_TOE_GRQ_PROD_SIZE (IRO[IRO_USTORM_TOE_GRQ_PROD].size)
0407 
0408 /* Ustorm VF-PF Channel ready flag */
0409 #define USTORM_VF_PF_CHANNEL_READY_GTT_OFFSET(vf_id)  \
0410     (IRO[IRO_USTORM_VF_PF_CHANNEL_READY_GTT].base \
0411      + ((vf_id) * IRO[IRO_USTORM_VF_PF_CHANNEL_READY_GTT].m1))
0412 #define USTORM_VF_PF_CHANNEL_READY_GTT_SIZE \
0413                 (IRO[IRO_USTORM_VF_PF_CHANNEL_READY_GTT].size)
0414 
0415 /* Xstorm queue zone */
0416 #define XSTORM_ETH_QUEUE_ZONE_GTT_OFFSET(queue_id) \
0417     (IRO[IRO_XSTORM_ETH_QUEUE_ZONE_GTT].base   \
0418      + ((queue_id) * IRO[IRO_XSTORM_ETH_QUEUE_ZONE_GTT].m1))
0419 #define XSTORM_ETH_QUEUE_ZONE_GTT_SIZE (IRO[IRO_XSTORM_ETH_QUEUE_ZONE_GTT].size)
0420 
0421 /* Xstorm Integration Test Data */
0422 #define XSTORM_INTEG_TEST_DATA_OFFSET (IRO[IRO_XSTORM_INTEG_TEST_DATA].base)
0423 #define XSTORM_INTEG_TEST_DATA_SIZE (IRO[IRO_XSTORM_INTEG_TEST_DATA].size)
0424 
0425 /* Xstorm iSCSI TX stats */
0426 #define XSTORM_ISCSI_TX_STATS_OFFSET(storage_func_id) \
0427     (IRO[IRO_XSTORM_ISCSI_TX_STATS].base          \
0428      + ((storage_func_id) * IRO[IRO_XSTORM_ISCSI_TX_STATS].m1))
0429 #define XSTORM_ISCSI_TX_STATS_SIZE (IRO[IRO_XSTORM_ISCSI_TX_STATS].size)
0430 
0431 /* Xstorm iWARP rxmit stats */
0432 #define XSTORM_IWARP_RXMIT_STATS_OFFSET(pf_id)  \
0433     (IRO[IRO_XSTORM_IWARP_RXMIT_STATS].base \
0434      + ((pf_id) * IRO[IRO_XSTORM_IWARP_RXMIT_STATS].m1))
0435 #define XSTORM_IWARP_RXMIT_STATS_SIZE (IRO[IRO_XSTORM_IWARP_RXMIT_STATS].size)
0436 
0437 /* Xstorm overlay buffer host address */
0438 #define XSTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[IRO_XSTORM_OVERLAY_BUF_ADDR].base)
0439 #define XSTORM_OVERLAY_BUF_ADDR_SIZE (IRO[IRO_XSTORM_OVERLAY_BUF_ADDR].size)
0440 
0441 /* Xstorm common PQ info */
0442 #define XSTORM_PQ_INFO_OFFSET(pq_id)  \
0443     (IRO[IRO_XSTORM_PQ_INFO].base \
0444      + ((pq_id) * IRO[IRO_XSTORM_PQ_INFO].m1))
0445 #define XSTORM_PQ_INFO_SIZE (IRO[IRO_XSTORM_PQ_INFO].size)
0446 
0447 /* Xstorm error level for assert */
0448 #define XSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id)  \
0449     (IRO[IRO_XSTORM_RDMA_ASSERT_LEVEL].base \
0450      + ((pf_id) * IRO[IRO_XSTORM_RDMA_ASSERT_LEVEL].m1))
0451 #define XSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[IRO_XSTORM_RDMA_ASSERT_LEVEL].size)
0452 
0453 /* Ystorm flow control mode. Use enum fw_flow_ctrl_mode */
0454 #define YSTORM_FLOW_CONTROL_MODE_GTT_OFFSET \
0455                 (IRO[IRO_YSTORM_FLOW_CONTROL_MODE_GTT].base)
0456 #define YSTORM_FLOW_CONTROL_MODE_GTT_SIZE \
0457                 (IRO[IRO_YSTORM_FLOW_CONTROL_MODE_GTT].size)
0458 
0459 /* Ystorm Integration Test Data */
0460 #define YSTORM_INTEG_TEST_DATA_OFFSET (IRO[IRO_YSTORM_INTEG_TEST_DATA].base)
0461 #define YSTORM_INTEG_TEST_DATA_SIZE (IRO[IRO_YSTORM_INTEG_TEST_DATA].size)
0462 
0463 /* Ystorm iSCSI TX stats */
0464 #define YSTORM_ISCSI_TX_STATS_OFFSET(storage_func_id) \
0465     (IRO[IRO_YSTORM_ISCSI_TX_STATS].base          \
0466      + ((storage_func_id) * IRO[IRO_YSTORM_ISCSI_TX_STATS].m1))
0467 #define YSTORM_ISCSI_TX_STATS_SIZE (IRO[IRO_YSTORM_ISCSI_TX_STATS].size)
0468 
0469 /* Ystorm overlay buffer host address */
0470 #define YSTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[IRO_YSTORM_OVERLAY_BUF_ADDR].base)
0471 #define YSTORM_OVERLAY_BUF_ADDR_SIZE (IRO[IRO_YSTORM_OVERLAY_BUF_ADDR].size)
0472 
0473 /* Ystorm error level for assert */
0474 #define YSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id)  \
0475     (IRO[IRO_YSTORM_RDMA_ASSERT_LEVEL].base \
0476      + ((pf_id) * IRO[IRO_YSTORM_RDMA_ASSERT_LEVEL].m1))
0477 #define YSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[IRO_YSTORM_RDMA_ASSERT_LEVEL].size)
0478 
0479 /* DCQCN Received Statistics */
0480 #define YSTORM_ROCE_DCQCN_RECEIVED_STATS_OFFSET(roce_pf_id) \
0481     (IRO[IRO_YSTORM_ROCE_DCQCN_RECEIVED_STATS].base     \
0482      + ((roce_pf_id) * IRO[IRO_YSTORM_ROCE_DCQCN_RECEIVED_STATS].m1))
0483 #define YSTORM_ROCE_DCQCN_RECEIVED_STATS_SIZE \
0484             (IRO[IRO_YSTORM_ROCE_DCQCN_RECEIVED_STATS].size)
0485 
0486 /* RoCE Error Statistics */
0487 #define YSTORM_ROCE_ERROR_STATS_OFFSET(roce_pf_id) \
0488     (IRO[IRO_YSTORM_ROCE_ERROR_STATS].base     \
0489      + ((roce_pf_id) * IRO[IRO_YSTORM_ROCE_ERROR_STATS].m1))
0490 #define YSTORM_ROCE_ERROR_STATS_SIZE (IRO[IRO_YSTORM_ROCE_ERROR_STATS].size)
0491 
0492 /* Ystorm cqe producer */
0493 #define YSTORM_TOE_CQ_PROD_OFFSET(rss_id) \
0494     (IRO[IRO_YSTORM_TOE_CQ_PROD].base \
0495      + ((rss_id) * IRO[IRO_YSTORM_TOE_CQ_PROD].m1))
0496 #define YSTORM_TOE_CQ_PROD_SIZE (IRO[IRO_YSTORM_TOE_CQ_PROD].size)
0497 
0498 /* Per-chip offsets in iro_arr in dwords */
0499 #define E4_IRO_ARR_OFFSET    0
0500 #endif
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