qlogic/qed/qed_int.h

0001 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
0002 /* QLogic qed NIC Driver
0003  * Copyright (c) 2015-2017  QLogic Corporation
0004  * Copyright (c) 2019-2020 Marvell International Ltd.
0005  */
0006
0007 #ifndef _QED_INT_H
0008 #define _QED_INT_H
0009
0010 #include <linux/types.h>
0011 #include <linux/slab.h>
0012 #include "qed.h"
0013
0014 /* Fields of IGU PF CONFIGURATION REGISTER */
0015 #define IGU_PF_CONF_FUNC_EN       (0x1 << 0)    /* function enable        */
0016 #define IGU_PF_CONF_MSI_MSIX_EN   (0x1 << 1)    /* MSI/MSIX enable        */
0017 #define IGU_PF_CONF_INT_LINE_EN   (0x1 << 2)    /* INT enable             */
0018 #define IGU_PF_CONF_ATTN_BIT_EN   (0x1 << 3)    /* attention enable       */
0019 #define IGU_PF_CONF_SINGLE_ISR_EN (0x1 << 4)    /* single ISR mode enable */
0020 #define IGU_PF_CONF_SIMD_MODE     (0x1 << 5)    /* simd all ones mode     */
0021 /* Fields of IGU VF CONFIGURATION REGISTER */
0022 #define IGU_VF_CONF_FUNC_EN        (0x1 << 0)   /* function enable        */
0023 #define IGU_VF_CONF_MSI_MSIX_EN    (0x1 << 1)   /* MSI/MSIX enable        */
0024 #define IGU_VF_CONF_SINGLE_ISR_EN  (0x1 << 4)   /* single ISR mode enable */
0025 #define IGU_VF_CONF_PARENT_MASK    (0xF)    /* Parent PF              */
0026 #define IGU_VF_CONF_PARENT_SHIFT   5        /* Parent PF              */
0027
0028 /* Igu control commands
0029  */
0030 enum igu_ctrl_cmd {
0031     IGU_CTRL_CMD_TYPE_RD,
0032     IGU_CTRL_CMD_TYPE_WR,
0033     MAX_IGU_CTRL_CMD
0034 };
0035
0036 /* Control register for the IGU command register
0037  */
0038 struct igu_ctrl_reg {
0039     u32 ctrl_data;
0040 #define IGU_CTRL_REG_FID_MASK           0xFFFF  /* Opaque_FID    */
0041 #define IGU_CTRL_REG_FID_SHIFT          0
0042 #define IGU_CTRL_REG_PXP_ADDR_MASK      0xFFF   /* Command address */
0043 #define IGU_CTRL_REG_PXP_ADDR_SHIFT     16
0044 #define IGU_CTRL_REG_RESERVED_MASK      0x1
0045 #define IGU_CTRL_REG_RESERVED_SHIFT     28
0046 #define IGU_CTRL_REG_TYPE_MASK          0x1 /* use enum igu_ctrl_cmd */
0047 #define IGU_CTRL_REG_TYPE_SHIFT         31
0048 };
0049
0050 enum qed_coalescing_fsm {
0051     QED_COAL_RX_STATE_MACHINE,
0052     QED_COAL_TX_STATE_MACHINE
0053 };
0054
0055 /**
0056  * qed_int_igu_enable_int(): Enable device interrupts.
0057  *
0058  * @p_hwfn: HW device data.
0059  * @p_ptt: P_ptt.
0060  * @int_mode: Interrupt mode to use.
0061  *
0062  * Return: Void.
0063  */
0064 void qed_int_igu_enable_int(struct qed_hwfn *p_hwfn,
0065                 struct qed_ptt *p_ptt,
0066                 enum qed_int_mode int_mode);
0067
0068 /**
0069  * qed_int_igu_disable_int():  Disable device interrupts.
0070  *
0071  * @p_hwfn: HW device data.
0072  * @p_ptt: P_ptt.
0073  *
0074  * Return: Void.
0075  */
0076 void qed_int_igu_disable_int(struct qed_hwfn *p_hwfn,
0077                  struct qed_ptt *p_ptt);
0078
0079 /**
0080  * qed_int_igu_read_sisr_reg(): Reads the single isr multiple dpc
0081  *                             register from igu.
0082  *
0083  * @p_hwfn: HW device data.
0084  *
0085  * Return: u64.
0086  */
0087 u64 qed_int_igu_read_sisr_reg(struct qed_hwfn *p_hwfn);
0088
0089 #define QED_SP_SB_ID 0xffff
0090 /**
0091  * qed_int_sb_init(): Initializes the sb_info structure.
0092  *
0093  * @p_hwfn: HW device data.
0094  * @p_ptt: P_ptt.
0095  * @sb_info: points to an uninitialized (but allocated) sb_info structure
0096  * @sb_virt_addr: SB Virtual address.
0097  * @sb_phy_addr: SB Physial address.
0098  * @sb_id: the sb_id to be used (zero based in driver)
0099  *           should use QED_SP_SB_ID for SP Status block
0100  *
0101  * Return: int.
0102  *
0103  * Once the structure is initialized it can be passed to sb related functions.
0104  */
0105 int qed_int_sb_init(struct qed_hwfn *p_hwfn,
0106             struct qed_ptt *p_ptt,
0107             struct qed_sb_info *sb_info,
0108             void *sb_virt_addr,
0109             dma_addr_t sb_phy_addr,
0110             u16 sb_id);
0111 /**
0112  * qed_int_sb_setup(): Setup the sb.
0113  *
0114  * @p_hwfn: HW device data.
0115  * @p_ptt: P_ptt.
0116  * @sb_info: Initialized sb_info structure.
0117  *
0118  * Return: Void.
0119  */
0120 void qed_int_sb_setup(struct qed_hwfn *p_hwfn,
0121               struct qed_ptt *p_ptt,
0122               struct qed_sb_info *sb_info);
0123
0124 /**
0125  * qed_int_sb_release(): Releases the sb_info structure.
0126  *
0127  * @p_hwfn: HW device data.
0128  * @sb_info: Points to an allocated sb_info structure.
0129  * @sb_id: The sb_id to be used (zero based in driver)
0130  *         should never be equal to QED_SP_SB_ID
0131  *         (SP Status block).
0132  *
0133  * Return: int.
0134  *
0135  * Once the structure is released, it's memory can be freed.
0136  */
0137 int qed_int_sb_release(struct qed_hwfn *p_hwfn,
0138                struct qed_sb_info *sb_info,
0139                u16 sb_id);
0140
0141 /**
0142  * qed_int_sp_dpc(): To be called when an interrupt is received on the
0143  *                   default status block.
0144  *
0145  * @t: Tasklet.
0146  *
0147  * Return: Void.
0148  *
0149  */
0150 void qed_int_sp_dpc(struct tasklet_struct *t);
0151
0152 /**
0153  * qed_int_get_num_sbs(): Get the number of status blocks configured
0154  *                        for this funciton in the igu.
0155  *
0156  * @p_hwfn: HW device data.
0157  * @p_sb_cnt_info: Pointer to SB count info.
0158  *
0159  * Return: Void.
0160  */
0161 void qed_int_get_num_sbs(struct qed_hwfn    *p_hwfn,
0162              struct qed_sb_cnt_info *p_sb_cnt_info);
0163
0164 /**
0165  * qed_int_disable_post_isr_release(): Performs the cleanup post ISR
0166  *        release. The API need to be called after releasing all slowpath IRQs
0167  *        of the device.
0168  *
0169  * @cdev: Qed dev pointer.
0170  *
0171  * Return: Void.
0172  */
0173 void qed_int_disable_post_isr_release(struct qed_dev *cdev);
0174
0175 /**
0176  * qed_int_attn_clr_enable: Sets whether the general behavior is
0177  *        preventing attentions from being reasserted, or following the
0178  *        attributes of the specific attention.
0179  *
0180  * @cdev: Qed dev pointer.
0181  * @clr_enable: Clear enable
0182  *
0183  * Return: Void.
0184  *
0185  */
0186 void qed_int_attn_clr_enable(struct qed_dev *cdev, bool clr_enable);
0187
0188 /**
0189  * qed_int_get_sb_dbg: Read debug information regarding a given SB
0190  *
0191  * @p_hwfn: hw function pointer
0192  * @p_ptt: ptt resource
0193  * @p_sb: pointer to status block for which we want to get info
0194  * @p_info: pointer to struct to fill with information regarding SB
0195  *
0196  * Return: 0 with status block info filled on success, otherwise return error
0197  */
0198 int qed_int_get_sb_dbg(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
0199                struct qed_sb_info *p_sb, struct qed_sb_info_dbg *p_info);
0200
0201 /**
0202  * qed_db_rec_handler(): Doorbell Recovery handler.
0203  *          Run doorbell recovery in case of PF overflow (and flush DORQ if
0204  *          needed).
0205  *
0206  * @p_hwfn: HW device data.
0207  * @p_ptt: P_ptt.
0208  *
0209  * Return: Int.
0210  */
0211 int qed_db_rec_handler(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
0212
0213 #define QED_CAU_DEF_RX_TIMER_RES 0
0214 #define QED_CAU_DEF_TX_TIMER_RES 0
0215
0216 #define QED_SB_ATT_IDX  0x0001
0217 #define QED_SB_EVENT_MASK       0x0003
0218
0219 #define SB_ALIGNED_SIZE(p_hwfn) \
0220     ALIGNED_TYPE_SIZE(struct status_block, p_hwfn)
0221
0222 #define QED_SB_INVALID_IDX      0xffff
0223
0224 struct qed_igu_block {
0225     u8 status;
0226 #define QED_IGU_STATUS_FREE     0x01
0227 #define QED_IGU_STATUS_VALID    0x02
0228 #define QED_IGU_STATUS_PF       0x04
0229 #define QED_IGU_STATUS_DSB      0x08
0230
0231     u8 vector_number;
0232     u8 function_id;
0233     u8 is_pf;
0234
0235     /* Index inside IGU [meant for back reference] */
0236     u16 igu_sb_id;
0237
0238     struct qed_sb_info *sb_info;
0239 };
0240
0241 struct qed_igu_info {
0242     struct qed_igu_block entry[MAX_TOT_SB_PER_PATH];
0243     u16 igu_dsb_id;
0244
0245     struct qed_sb_cnt_info usage;
0246
0247     bool b_allow_pf_vf_change;
0248 };
0249
0250 /**
0251  * qed_int_igu_reset_cam(): Make sure the IGU CAM reflects the resources
0252  *                          provided by MFW.
0253  *
0254  * @p_hwfn: HW device data.
0255  * @p_ptt: P_ptt.
0256  *
0257  * Return: Void.
0258  */
0259 int qed_int_igu_reset_cam(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
0260
0261 /**
0262  * qed_get_igu_sb_id(): Translate the weakly-defined client sb-id into
0263  *                      an IGU sb-id
0264  *
0265  * @p_hwfn: HW device data.
0266  * @sb_id: user provided sb_id.
0267  *
0268  * Return: An index inside IGU CAM where the SB resides.
0269  */
0270 u16 qed_get_igu_sb_id(struct qed_hwfn *p_hwfn, u16 sb_id);
0271
0272 /**
0273  * qed_get_igu_free_sb(): Return a pointer to an unused valid SB
0274  *
0275  * @p_hwfn: HW device data.
0276  * @b_is_pf: True iff we want a SB belonging to a PF.
0277  *
0278  * Return: Point to an igu_block, NULL if none is available.
0279  */
0280 struct qed_igu_block *qed_get_igu_free_sb(struct qed_hwfn *p_hwfn,
0281                       bool b_is_pf);
0282
0283 void qed_int_igu_init_pure_rt(struct qed_hwfn *p_hwfn,
0284                   struct qed_ptt *p_ptt,
0285                   bool b_set,
0286                   bool b_slowpath);
0287
0288 void qed_int_igu_init_rt(struct qed_hwfn *p_hwfn);
0289
0290 /**
0291  * qed_int_igu_read_cam():  Reads the IGU CAM.
0292  *  This function needs to be called during hardware
0293  *  prepare. It reads the info from igu cam to know which
0294  *  status block is the default / base status block etc.
0295  *
0296  * @p_hwfn: HW device data.
0297  * @p_ptt: P_ptt.
0298  *
0299  * Return: Int.
0300  */
0301 int qed_int_igu_read_cam(struct qed_hwfn *p_hwfn,
0302              struct qed_ptt *p_ptt);
0303
0304 typedef int (*qed_int_comp_cb_t)(struct qed_hwfn *p_hwfn,
0305                  void *cookie);
0306 /**
0307  * qed_int_register_cb(): Register callback func for slowhwfn statusblock.
0308  *
0309  * @p_hwfn: HW device data.
0310  * @comp_cb: Function to be called when there is an
0311  *           interrupt on the sp sb
0312  * @cookie: Passed to the callback function
0313  * @sb_idx: (OUT) parameter which gives the chosen index
0314  *           for this protocol.
0315  * @p_fw_cons: Pointer to the actual address of the
0316  *             consumer for this protocol.
0317  *
0318  * Return: Int.
0319  *
0320  * Every protocol that uses the slowhwfn status block
0321  * should register a callback function that will be called
0322  * once there is an update of the sp status block.
0323  */
0324 int qed_int_register_cb(struct qed_hwfn *p_hwfn,
0325             qed_int_comp_cb_t comp_cb,
0326             void *cookie,
0327             u8 *sb_idx,
0328             __le16 **p_fw_cons);
0329
0330 /**
0331  * qed_int_unregister_cb(): Unregisters callback function from sp sb.
0332  *
0333  * @p_hwfn: HW device data.
0334  * @pi: Producer Index.
0335  *
0336  * Return: Int.
0337  *
0338  * Partner of qed_int_register_cb -> should be called
0339  * when no longer required.
0340  */
0341 int qed_int_unregister_cb(struct qed_hwfn *p_hwfn,
0342               u8 pi);
0343
0344 /**
0345  * qed_int_get_sp_sb_id(): Get the slowhwfn sb id.
0346  *
0347  * @p_hwfn: HW device data.
0348  *
0349  * Return: u16.
0350  */
0351 u16 qed_int_get_sp_sb_id(struct qed_hwfn *p_hwfn);
0352
0353 /**
0354  * qed_int_igu_init_pure_rt_single(): Status block cleanup.
0355  *                                    Should be called for each status
0356  *                                    block that will be used -> both PF / VF.
0357  *
0358  * @p_hwfn: HW device data.
0359  * @p_ptt: P_ptt.
0360  * @igu_sb_id: IGU status block id.
0361  * @opaque: Opaque fid of the sb owner.
0362  * @b_set: Set(1) / Clear(0).
0363  *
0364  * Return: Void.
0365  */
0366 void qed_int_igu_init_pure_rt_single(struct qed_hwfn *p_hwfn,
0367                      struct qed_ptt *p_ptt,
0368                      u16 igu_sb_id,
0369                      u16 opaque,
0370                      bool b_set);
0371
0372 /**
0373  * qed_int_cau_conf_sb(): Configure cau for a given status block.
0374  *
0375  * @p_hwfn: HW device data.
0376  * @p_ptt: P_ptt.
0377  * @sb_phys: SB Physical.
0378  * @igu_sb_id: IGU status block id.
0379  * @vf_number: VF number
0380  * @vf_valid: VF valid or not.
0381  *
0382  * Return: Void.
0383  */
0384 void qed_int_cau_conf_sb(struct qed_hwfn *p_hwfn,
0385              struct qed_ptt *p_ptt,
0386              dma_addr_t sb_phys,
0387              u16 igu_sb_id,
0388              u16 vf_number,
0389              u8 vf_valid);
0390
0391 /**
0392  * qed_int_alloc(): QED interrupt alloc.
0393  *
0394  * @p_hwfn: HW device data.
0395  * @p_ptt: P_ptt.
0396  *
0397  * Return: Int.
0398  */
0399 int qed_int_alloc(struct qed_hwfn *p_hwfn,
0400           struct qed_ptt *p_ptt);
0401
0402 /**
0403  * qed_int_free(): QED interrupt free.
0404  *
0405  * @p_hwfn: HW device data.
0406  *
0407  * Return: Void.
0408  */
0409 void qed_int_free(struct qed_hwfn *p_hwfn);
0410
0411 /**
0412  * qed_int_setup(): QED interrupt setup.
0413  *
0414  * @p_hwfn: HW device data.
0415  * @p_ptt: P_ptt.
0416  *
0417  * Return: Void.
0418  */
0419 void qed_int_setup(struct qed_hwfn *p_hwfn,
0420            struct qed_ptt *p_ptt);
0421
0422 /**
0423  * qed_int_igu_enable(): Enable Interrupt & Attention for hw function.
0424  *
0425  * @p_hwfn: HW device data.
0426  * @p_ptt: P_ptt.
0427  * @int_mode: Interrut mode
0428  *
0429  * Return: Int.
0430  */
0431 int qed_int_igu_enable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
0432                enum qed_int_mode int_mode);
0433
0434 /**
0435  * qed_init_cau_sb_entry(): Initialize CAU status block entry.
0436  *
0437  * @p_hwfn: HW device data.
0438  * @p_sb_entry: Pointer SB entry.
0439  * @pf_id: PF number
0440  * @vf_number: VF number
0441  * @vf_valid: VF valid or not.
0442  *
0443  * Return: Void.
0444  */
0445 void qed_init_cau_sb_entry(struct qed_hwfn *p_hwfn,
0446                struct cau_sb_entry *p_sb_entry,
0447                u8 pf_id,
0448                u16 vf_number,
0449                u8 vf_valid);
0450
0451 int qed_int_set_timer_res(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
0452               u8 timer_res, u16 sb_id, bool tx);
0453
0454 #define QED_MAPPING_MEMORY_SIZE(dev)    (NUM_OF_SBS(dev))
0455
0456 int qed_pglueb_rbc_attn_handler(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
0457                 bool hw_init);
0458
0459 #endif