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0001 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
0002 /* QLogic qed NIC Driver
0003  * Copyright (c) 2015-2017  QLogic Corporation
0004  * Copyright (c) 2019-2021 Marvell International Ltd.
0005  */
0006 
0007 #include <linux/types.h>
0008 #include <linux/crc8.h>
0009 #include <linux/delay.h>
0010 #include <linux/kernel.h>
0011 #include <linux/slab.h>
0012 #include <linux/string.h>
0013 #include "qed_hsi.h"
0014 #include "qed_hw.h"
0015 #include "qed_init_ops.h"
0016 #include "qed_iro_hsi.h"
0017 #include "qed_reg_addr.h"
0018 
0019 #define CDU_VALIDATION_DEFAULT_CFG CDU_CONTEXT_VALIDATION_DEFAULT_CFG
0020 
0021 static u16 con_region_offsets[3][NUM_OF_CONNECTION_TYPES] = {
0022     {400, 336, 352, 368, 304, 384, 416, 352},   /* region 3 offsets */
0023     {528, 496, 416, 512, 448, 512, 544, 480},   /* region 4 offsets */
0024     {608, 544, 496, 576, 576, 592, 624, 560}    /* region 5 offsets */
0025 };
0026 
0027 static u16 task_region_offsets[1][NUM_OF_CONNECTION_TYPES] = {
0028     {240, 240, 112, 0, 0, 0, 0, 96} /* region 1 offsets */
0029 };
0030 
0031 /* General constants */
0032 #define QM_PQ_MEM_4KB(pq_size)  (pq_size ? DIV_ROUND_UP((pq_size + 1) * \
0033                             QM_PQ_ELEMENT_SIZE, \
0034                             0x1000) : 0)
0035 #define QM_PQ_SIZE_256B(pq_size)    (pq_size ? DIV_ROUND_UP(pq_size, \
0036                                 0x100) - 1 : 0)
0037 #define QM_INVALID_PQ_ID        0xffff
0038 
0039 /* Max link speed (in Mbps) */
0040 #define QM_MAX_LINK_SPEED               100000
0041 
0042 /* Feature enable */
0043 #define QM_BYPASS_EN    1
0044 #define QM_BYTE_CRD_EN  1
0045 
0046 /* Initial VOQ byte credit */
0047 #define QM_INITIAL_VOQ_BYTE_CRD         98304
0048 /* Other PQ constants */
0049 #define QM_OTHER_PQS_PER_PF 4
0050 
0051 /* VOQ constants */
0052 #define MAX_NUM_VOQS    (MAX_NUM_PORTS_K2 * NUM_TCS_4PORT_K2)
0053 #define VOQS_BIT_MASK   (BIT(MAX_NUM_VOQS) - 1)
0054 
0055 /* WFQ constants */
0056 
0057 /* PF WFQ increment value, 0x9000 = 4*9*1024 */
0058 #define QM_PF_WFQ_INC_VAL(weight)       ((weight) * 0x9000)
0059 
0060 /* PF WFQ Upper bound, in MB, 10 * burst size of 1ms in 50Gbps */
0061 #define QM_PF_WFQ_UPPER_BOUND           62500000
0062 
0063 /* PF WFQ max increment value, 0.7 * upper bound */
0064 #define QM_PF_WFQ_MAX_INC_VAL           ((QM_PF_WFQ_UPPER_BOUND * 7) / 10)
0065 
0066 /* Number of VOQs in E5 PF WFQ credit register (QmWfqCrd) */
0067 #define QM_PF_WFQ_CRD_E5_NUM_VOQS       16
0068 
0069 /* VP WFQ increment value */
0070 #define QM_VP_WFQ_INC_VAL(weight)       ((weight) * QM_VP_WFQ_MIN_INC_VAL)
0071 
0072 /* VP WFQ min increment value */
0073 #define QM_VP_WFQ_MIN_INC_VAL           10800
0074 
0075 /* VP WFQ max increment value, 2^30 */
0076 #define QM_VP_WFQ_MAX_INC_VAL           0x40000000
0077 
0078 /* VP WFQ bypass threshold */
0079 #define QM_VP_WFQ_BYPASS_THRESH         (QM_VP_WFQ_MIN_INC_VAL - 100)
0080 
0081 /* VP RL credit task cost */
0082 #define QM_VP_RL_CRD_TASK_COST          9700
0083 
0084 /* Bit of VOQ in VP WFQ PQ map */
0085 #define QM_VP_WFQ_PQ_VOQ_SHIFT          0
0086 
0087 /* Bit of PF in VP WFQ PQ map */
0088 #define QM_VP_WFQ_PQ_PF_SHIFT   5
0089 
0090 /* RL constants */
0091 
0092 /* Period in us */
0093 #define QM_RL_PERIOD    5
0094 
0095 /* Period in 25MHz cycles */
0096 #define QM_RL_PERIOD_CLK_25M    (25 * QM_RL_PERIOD)
0097 
0098 /* RL increment value - rate is specified in mbps */
0099 #define QM_RL_INC_VAL(rate)                     ({  \
0100                         typeof(rate) __rate = (rate); \
0101                         max_t(u32,      \
0102                         (u32)(((__rate ? __rate : \
0103                         100000) *       \
0104                         QM_RL_PERIOD *      \
0105                         101) / (8 * 100)), 1); })
0106 
0107 /* PF RL Upper bound is set to 10 * burst size of 1ms in 50Gbps */
0108 #define QM_PF_RL_UPPER_BOUND    62500000
0109 
0110 /* Max PF RL increment value is 0.7 * upper bound */
0111 #define QM_PF_RL_MAX_INC_VAL    ((QM_PF_RL_UPPER_BOUND * 7) / 10)
0112 
0113 /* QCN RL Upper bound, speed is in Mpbs */
0114 #define QM_GLOBAL_RL_UPPER_BOUND(speed)         ((u32)max_t( \
0115         u32,                        \
0116         (u32)(((speed) *                \
0117                QM_RL_PERIOD * 101) / (8 * 100)),    \
0118         QM_VP_RL_CRD_TASK_COST              \
0119         + 1000))
0120 
0121 /* AFullOprtnstcCrdMask constants */
0122 #define QM_OPPOR_LINE_VOQ_DEF   1
0123 #define QM_OPPOR_FW_STOP_DEF    0
0124 #define QM_OPPOR_PQ_EMPTY_DEF   1
0125 
0126 /* Command Queue constants */
0127 
0128 /* Pure LB CmdQ lines (+spare) */
0129 #define PBF_CMDQ_PURE_LB_LINES  150
0130 
0131 #define PBF_CMDQ_LINES_RT_OFFSET(ext_voq) \
0132     (PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET + \
0133      (ext_voq) * (PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET - \
0134         PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET))
0135 
0136 #define PBF_BTB_GUARANTEED_RT_OFFSET(ext_voq) \
0137     (PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET + \
0138      (ext_voq) * (PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET - \
0139         PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET))
0140 
0141 /* Returns the VOQ line credit for the specified number of PBF command lines.
0142  * PBF lines are specified in 256b units.
0143  */
0144 #define QM_VOQ_LINE_CRD(pbf_cmd_lines) \
0145     ((((pbf_cmd_lines) - 4) * 2) | QM_LINE_CRD_REG_SIGN_BIT)
0146 
0147 /* BTB: blocks constants (block size = 256B) */
0148 
0149 /* 256B blocks in 9700B packet */
0150 #define BTB_JUMBO_PKT_BLOCKS    38
0151 
0152 /* Headroom per-port */
0153 #define BTB_HEADROOM_BLOCKS BTB_JUMBO_PKT_BLOCKS
0154 #define BTB_PURE_LB_FACTOR  10
0155 
0156 /* Factored (hence really 0.7) */
0157 #define BTB_PURE_LB_RATIO   7
0158 
0159 /* QM stop command constants */
0160 #define QM_STOP_PQ_MASK_WIDTH       32
0161 #define QM_STOP_CMD_ADDR        2
0162 #define QM_STOP_CMD_STRUCT_SIZE     2
0163 #define QM_STOP_CMD_PAUSE_MASK_OFFSET   0
0164 #define QM_STOP_CMD_PAUSE_MASK_SHIFT    0
0165 #define QM_STOP_CMD_PAUSE_MASK_MASK -1
0166 #define QM_STOP_CMD_GROUP_ID_OFFSET 1
0167 #define QM_STOP_CMD_GROUP_ID_SHIFT  16
0168 #define QM_STOP_CMD_GROUP_ID_MASK   15
0169 #define QM_STOP_CMD_PQ_TYPE_OFFSET  1
0170 #define QM_STOP_CMD_PQ_TYPE_SHIFT   24
0171 #define QM_STOP_CMD_PQ_TYPE_MASK    1
0172 #define QM_STOP_CMD_MAX_POLL_COUNT  100
0173 #define QM_STOP_CMD_POLL_PERIOD_US  500
0174 
0175 /* QM command macros */
0176 #define QM_CMD_STRUCT_SIZE(cmd) cmd ## _STRUCT_SIZE
0177 #define QM_CMD_SET_FIELD(var, cmd, field, value) \
0178     SET_FIELD(var[cmd ## _ ## field ## _OFFSET], \
0179           cmd ## _ ## field, \
0180           value)
0181 
0182 #define QM_INIT_TX_PQ_MAP(p_hwfn, map, pq_id, vp_pq_id, rl_valid,         \
0183               rl_id, ext_voq, wrr)                    \
0184     do {                                      \
0185         u32 __reg = 0;                            \
0186                                           \
0187         BUILD_BUG_ON(sizeof((map).reg) != sizeof(__reg));         \
0188         memset(&(map), 0, sizeof(map));                   \
0189         SET_FIELD(__reg, QM_RF_PQ_MAP_PQ_VALID, 1);       \
0190         SET_FIELD(__reg, QM_RF_PQ_MAP_RL_VALID,       \
0191               !!(rl_valid));                      \
0192         SET_FIELD(__reg, QM_RF_PQ_MAP_VP_PQ_ID, (vp_pq_id)); \
0193         SET_FIELD(__reg, QM_RF_PQ_MAP_RL_ID, (rl_id));        \
0194         SET_FIELD(__reg, QM_RF_PQ_MAP_VOQ, (ext_voq));        \
0195         SET_FIELD(__reg, QM_RF_PQ_MAP_WRR_WEIGHT_GROUP,      \
0196               (wrr));                         \
0197                                           \
0198         STORE_RT_REG((p_hwfn), QM_REG_TXPQMAP_RT_OFFSET + (pq_id),    \
0199                  __reg);                          \
0200         (map).reg = cpu_to_le32(__reg);                   \
0201     } while (0)
0202 
0203 #define WRITE_PQ_INFO_TO_RAM    1
0204 #define PQ_INFO_ELEMENT(vp, pf, tc, port, rl_valid, rl) \
0205     (((vp) << 0) | ((pf) << 12) | ((tc) << 16) | ((port) << 20) | \
0206     ((rl_valid ? 1 : 0) << 22) | (((rl) & 255) << 24) | \
0207     (((rl) >> 8) << 9))
0208 
0209 #define PQ_INFO_RAM_GRC_ADDRESS(pq_id) \
0210     (XSEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM + \
0211     XSTORM_PQ_INFO_OFFSET(pq_id))
0212 
0213 static const char * const s_protocol_types[] = {
0214     "PROTOCOLID_ISCSI", "PROTOCOLID_FCOE", "PROTOCOLID_ROCE",
0215     "PROTOCOLID_CORE", "PROTOCOLID_ETH", "PROTOCOLID_IWARP",
0216     "PROTOCOLID_TOE", "PROTOCOLID_PREROCE", "PROTOCOLID_COMMON",
0217     "PROTOCOLID_TCP", "PROTOCOLID_RDMA", "PROTOCOLID_SCSI",
0218 };
0219 
0220 static const char *s_ramrod_cmd_ids[][28] = {
0221     {
0222     "ISCSI_RAMROD_CMD_ID_UNUSED", "ISCSI_RAMROD_CMD_ID_INIT_FUNC",
0223      "ISCSI_RAMROD_CMD_ID_DESTROY_FUNC",
0224      "ISCSI_RAMROD_CMD_ID_OFFLOAD_CONN",
0225      "ISCSI_RAMROD_CMD_ID_UPDATE_CONN",
0226      "ISCSI_RAMROD_CMD_ID_TERMINATION_CONN",
0227      "ISCSI_RAMROD_CMD_ID_CLEAR_SQ", "ISCSI_RAMROD_CMD_ID_MAC_UPDATE",
0228      "ISCSI_RAMROD_CMD_ID_CONN_STATS", },
0229     { "FCOE_RAMROD_CMD_ID_INIT_FUNC", "FCOE_RAMROD_CMD_ID_DESTROY_FUNC",
0230      "FCOE_RAMROD_CMD_ID_STAT_FUNC",
0231      "FCOE_RAMROD_CMD_ID_OFFLOAD_CONN",
0232      "FCOE_RAMROD_CMD_ID_TERMINATE_CONN", },
0233     { "RDMA_RAMROD_UNUSED", "RDMA_RAMROD_FUNC_INIT",
0234      "RDMA_RAMROD_FUNC_CLOSE", "RDMA_RAMROD_REGISTER_MR",
0235      "RDMA_RAMROD_DEREGISTER_MR", "RDMA_RAMROD_CREATE_CQ",
0236      "RDMA_RAMROD_RESIZE_CQ", "RDMA_RAMROD_DESTROY_CQ",
0237      "RDMA_RAMROD_CREATE_SRQ", "RDMA_RAMROD_MODIFY_SRQ",
0238      "RDMA_RAMROD_DESTROY_SRQ", "RDMA_RAMROD_START_NS_TRACKING",
0239      "RDMA_RAMROD_STOP_NS_TRACKING", "ROCE_RAMROD_CREATE_QP",
0240      "ROCE_RAMROD_MODIFY_QP", "ROCE_RAMROD_QUERY_QP",
0241      "ROCE_RAMROD_DESTROY_QP", "ROCE_RAMROD_CREATE_UD_QP",
0242      "ROCE_RAMROD_DESTROY_UD_QP", "ROCE_RAMROD_FUNC_UPDATE",
0243      "ROCE_RAMROD_SUSPEND_QP", "ROCE_RAMROD_QUERY_SUSPENDED_QP",
0244      "ROCE_RAMROD_CREATE_SUSPENDED_QP", "ROCE_RAMROD_RESUME_QP",
0245      "ROCE_RAMROD_SUSPEND_UD_QP", "ROCE_RAMROD_RESUME_UD_QP",
0246      "ROCE_RAMROD_CREATE_SUSPENDED_UD_QP", "ROCE_RAMROD_FLUSH_DPT_QP", },
0247     { "CORE_RAMROD_UNUSED", "CORE_RAMROD_RX_QUEUE_START",
0248      "CORE_RAMROD_TX_QUEUE_START", "CORE_RAMROD_RX_QUEUE_STOP",
0249      "CORE_RAMROD_TX_QUEUE_STOP",
0250      "CORE_RAMROD_RX_QUEUE_FLUSH",
0251      "CORE_RAMROD_TX_QUEUE_UPDATE", "CORE_RAMROD_QUEUE_STATS_QUERY", },
0252     { "ETH_RAMROD_UNUSED", "ETH_RAMROD_VPORT_START",
0253      "ETH_RAMROD_VPORT_UPDATE", "ETH_RAMROD_VPORT_STOP",
0254      "ETH_RAMROD_RX_QUEUE_START", "ETH_RAMROD_RX_QUEUE_STOP",
0255      "ETH_RAMROD_TX_QUEUE_START", "ETH_RAMROD_TX_QUEUE_STOP",
0256      "ETH_RAMROD_FILTERS_UPDATE", "ETH_RAMROD_RX_QUEUE_UPDATE",
0257      "ETH_RAMROD_RX_CREATE_OPENFLOW_ACTION",
0258      "ETH_RAMROD_RX_ADD_OPENFLOW_FILTER",
0259      "ETH_RAMROD_RX_DELETE_OPENFLOW_FILTER",
0260      "ETH_RAMROD_RX_ADD_UDP_FILTER",
0261      "ETH_RAMROD_RX_DELETE_UDP_FILTER",
0262      "ETH_RAMROD_RX_CREATE_GFT_ACTION",
0263      "ETH_RAMROD_RX_UPDATE_GFT_FILTER", "ETH_RAMROD_TX_QUEUE_UPDATE",
0264      "ETH_RAMROD_RGFS_FILTER_ADD", "ETH_RAMROD_RGFS_FILTER_DEL",
0265      "ETH_RAMROD_TGFS_FILTER_ADD", "ETH_RAMROD_TGFS_FILTER_DEL",
0266      "ETH_RAMROD_GFS_COUNTERS_REPORT_REQUEST", },
0267     { "RDMA_RAMROD_UNUSED", "RDMA_RAMROD_FUNC_INIT",
0268      "RDMA_RAMROD_FUNC_CLOSE", "RDMA_RAMROD_REGISTER_MR",
0269      "RDMA_RAMROD_DEREGISTER_MR", "RDMA_RAMROD_CREATE_CQ",
0270      "RDMA_RAMROD_RESIZE_CQ", "RDMA_RAMROD_DESTROY_CQ",
0271      "RDMA_RAMROD_CREATE_SRQ", "RDMA_RAMROD_MODIFY_SRQ",
0272      "RDMA_RAMROD_DESTROY_SRQ", "RDMA_RAMROD_START_NS_TRACKING",
0273      "RDMA_RAMROD_STOP_NS_TRACKING",
0274      "IWARP_RAMROD_CMD_ID_TCP_OFFLOAD",
0275      "IWARP_RAMROD_CMD_ID_MPA_OFFLOAD",
0276      "IWARP_RAMROD_CMD_ID_MPA_OFFLOAD_SEND_RTR",
0277      "IWARP_RAMROD_CMD_ID_CREATE_QP", "IWARP_RAMROD_CMD_ID_QUERY_QP",
0278      "IWARP_RAMROD_CMD_ID_MODIFY_QP",
0279      "IWARP_RAMROD_CMD_ID_DESTROY_QP",
0280      "IWARP_RAMROD_CMD_ID_ABORT_TCP_OFFLOAD", },
0281     { NULL }, /*TOE*/
0282     { NULL }, /*PREROCE*/
0283     { "COMMON_RAMROD_UNUSED", "COMMON_RAMROD_PF_START",
0284          "COMMON_RAMROD_PF_STOP", "COMMON_RAMROD_VF_START",
0285          "COMMON_RAMROD_VF_STOP", "COMMON_RAMROD_PF_UPDATE",
0286          "COMMON_RAMROD_RL_UPDATE", "COMMON_RAMROD_EMPTY", }
0287 };
0288 
0289 /******************** INTERNAL IMPLEMENTATION *********************/
0290 
0291 /* Returns the external VOQ number */
0292 static u8 qed_get_ext_voq(struct qed_hwfn *p_hwfn,
0293               u8 port_id, u8 tc, u8 max_phys_tcs_per_port)
0294 {
0295     if (tc == PURE_LB_TC)
0296         return NUM_OF_PHYS_TCS * MAX_NUM_PORTS_BB + port_id;
0297     else
0298         return port_id * max_phys_tcs_per_port + tc;
0299 }
0300 
0301 /* Prepare PF RL enable/disable runtime init values */
0302 static void qed_enable_pf_rl(struct qed_hwfn *p_hwfn, bool pf_rl_en)
0303 {
0304     STORE_RT_REG(p_hwfn, QM_REG_RLPFENABLE_RT_OFFSET, pf_rl_en ? 1 : 0);
0305     if (pf_rl_en) {
0306         u8 num_ext_voqs = MAX_NUM_VOQS;
0307         u64 voq_bit_mask = ((u64)1 << num_ext_voqs) - 1;
0308 
0309         /* Enable RLs for all VOQs */
0310         STORE_RT_REG(p_hwfn,
0311                  QM_REG_RLPFVOQENABLE_RT_OFFSET,
0312                  (u32)voq_bit_mask);
0313 
0314         /* Write RL period */
0315         STORE_RT_REG(p_hwfn,
0316                  QM_REG_RLPFPERIOD_RT_OFFSET, QM_RL_PERIOD_CLK_25M);
0317         STORE_RT_REG(p_hwfn,
0318                  QM_REG_RLPFPERIODTIMER_RT_OFFSET,
0319                  QM_RL_PERIOD_CLK_25M);
0320 
0321         /* Set credit threshold for QM bypass flow */
0322         if (QM_BYPASS_EN)
0323             STORE_RT_REG(p_hwfn,
0324                      QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET,
0325                      QM_PF_RL_UPPER_BOUND);
0326     }
0327 }
0328 
0329 /* Prepare PF WFQ enable/disable runtime init values */
0330 static void qed_enable_pf_wfq(struct qed_hwfn *p_hwfn, bool pf_wfq_en)
0331 {
0332     STORE_RT_REG(p_hwfn, QM_REG_WFQPFENABLE_RT_OFFSET, pf_wfq_en ? 1 : 0);
0333 
0334     /* Set credit threshold for QM bypass flow */
0335     if (pf_wfq_en && QM_BYPASS_EN)
0336         STORE_RT_REG(p_hwfn,
0337                  QM_REG_AFULLQMBYPTHRPFWFQ_RT_OFFSET,
0338                  QM_PF_WFQ_UPPER_BOUND);
0339 }
0340 
0341 /* Prepare global RL enable/disable runtime init values */
0342 static void qed_enable_global_rl(struct qed_hwfn *p_hwfn, bool global_rl_en)
0343 {
0344     STORE_RT_REG(p_hwfn, QM_REG_RLGLBLENABLE_RT_OFFSET,
0345              global_rl_en ? 1 : 0);
0346     if (global_rl_en) {
0347         /* Write RL period (use timer 0 only) */
0348         STORE_RT_REG(p_hwfn,
0349                  QM_REG_RLGLBLPERIOD_0_RT_OFFSET,
0350                  QM_RL_PERIOD_CLK_25M);
0351         STORE_RT_REG(p_hwfn,
0352                  QM_REG_RLGLBLPERIODTIMER_0_RT_OFFSET,
0353                  QM_RL_PERIOD_CLK_25M);
0354 
0355         /* Set credit threshold for QM bypass flow */
0356         if (QM_BYPASS_EN)
0357             STORE_RT_REG(p_hwfn,
0358                      QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET,
0359                      QM_GLOBAL_RL_UPPER_BOUND(10000) - 1);
0360     }
0361 }
0362 
0363 /* Prepare VPORT WFQ enable/disable runtime init values */
0364 static void qed_enable_vport_wfq(struct qed_hwfn *p_hwfn, bool vport_wfq_en)
0365 {
0366     STORE_RT_REG(p_hwfn, QM_REG_WFQVPENABLE_RT_OFFSET,
0367              vport_wfq_en ? 1 : 0);
0368 
0369     /* Set credit threshold for QM bypass flow */
0370     if (vport_wfq_en && QM_BYPASS_EN)
0371         STORE_RT_REG(p_hwfn,
0372                  QM_REG_AFULLQMBYPTHRVPWFQ_RT_OFFSET,
0373                  QM_VP_WFQ_BYPASS_THRESH);
0374 }
0375 
0376 /* Prepare runtime init values to allocate PBF command queue lines for
0377  * the specified VOQ.
0378  */
0379 static void qed_cmdq_lines_voq_rt_init(struct qed_hwfn *p_hwfn,
0380                        u8 ext_voq, u16 cmdq_lines)
0381 {
0382     u32 qm_line_crd = QM_VOQ_LINE_CRD(cmdq_lines);
0383 
0384     OVERWRITE_RT_REG(p_hwfn, PBF_CMDQ_LINES_RT_OFFSET(ext_voq),
0385              (u32)cmdq_lines);
0386     STORE_RT_REG(p_hwfn, QM_REG_VOQCRDLINE_RT_OFFSET + ext_voq,
0387              qm_line_crd);
0388     STORE_RT_REG(p_hwfn, QM_REG_VOQINITCRDLINE_RT_OFFSET + ext_voq,
0389              qm_line_crd);
0390 }
0391 
0392 /* Prepare runtime init values to allocate PBF command queue lines. */
0393 static void
0394 qed_cmdq_lines_rt_init(struct qed_hwfn *p_hwfn,
0395                u8 max_ports_per_engine,
0396                u8 max_phys_tcs_per_port,
0397                struct init_qm_port_params port_params[MAX_NUM_PORTS])
0398 {
0399     u8 tc, ext_voq, port_id, num_tcs_in_port;
0400     u8 num_ext_voqs = MAX_NUM_VOQS;
0401 
0402     /* Clear PBF lines of all VOQs */
0403     for (ext_voq = 0; ext_voq < num_ext_voqs; ext_voq++)
0404         STORE_RT_REG(p_hwfn, PBF_CMDQ_LINES_RT_OFFSET(ext_voq), 0);
0405 
0406     for (port_id = 0; port_id < max_ports_per_engine; port_id++) {
0407         u16 phys_lines, phys_lines_per_tc;
0408 
0409         if (!port_params[port_id].active)
0410             continue;
0411 
0412         /* Find number of command queue lines to divide between the
0413          * active physical TCs.
0414          */
0415         phys_lines = port_params[port_id].num_pbf_cmd_lines;
0416         phys_lines -= PBF_CMDQ_PURE_LB_LINES;
0417 
0418         /* Find #lines per active physical TC */
0419         num_tcs_in_port = 0;
0420         for (tc = 0; tc < max_phys_tcs_per_port; tc++)
0421             if (((port_params[port_id].active_phys_tcs >>
0422                   tc) & 0x1) == 1)
0423                 num_tcs_in_port++;
0424         phys_lines_per_tc = phys_lines / num_tcs_in_port;
0425 
0426         /* Init registers per active TC */
0427         for (tc = 0; tc < max_phys_tcs_per_port; tc++) {
0428             ext_voq = qed_get_ext_voq(p_hwfn,
0429                           port_id,
0430                           tc, max_phys_tcs_per_port);
0431             if (((port_params[port_id].active_phys_tcs >>
0432                   tc) & 0x1) == 1)
0433                 qed_cmdq_lines_voq_rt_init(p_hwfn,
0434                                ext_voq,
0435                                phys_lines_per_tc);
0436         }
0437 
0438         /* Init registers for pure LB TC */
0439         ext_voq = qed_get_ext_voq(p_hwfn,
0440                       port_id,
0441                       PURE_LB_TC, max_phys_tcs_per_port);
0442         qed_cmdq_lines_voq_rt_init(p_hwfn, ext_voq,
0443                        PBF_CMDQ_PURE_LB_LINES);
0444     }
0445 }
0446 
0447 /* Prepare runtime init values to allocate guaranteed BTB blocks for the
0448  * specified port. The guaranteed BTB space is divided between the TCs as
0449  * follows (shared space Is currently not used):
0450  * 1. Parameters:
0451  *    B - BTB blocks for this port
0452  *    C - Number of physical TCs for this port
0453  * 2. Calculation:
0454  *    a. 38 blocks (9700B jumbo frame) are allocated for global per port
0455  *   headroom.
0456  *    b. B = B - 38 (remainder after global headroom allocation).
0457  *    c. MAX(38,B/(C+0.7)) blocks are allocated for the pure LB VOQ.
0458  *    d. B = B - MAX(38, B/(C+0.7)) (remainder after pure LB allocation).
0459  *    e. B/C blocks are allocated for each physical TC.
0460  * Assumptions:
0461  * - MTU is up to 9700 bytes (38 blocks)
0462  * - All TCs are considered symmetrical (same rate and packet size)
0463  * - No optimization for lossy TC (all are considered lossless). Shared space
0464  *   is not enabled and allocated for each TC.
0465  */
0466 static void
0467 qed_btb_blocks_rt_init(struct qed_hwfn *p_hwfn,
0468                u8 max_ports_per_engine,
0469                u8 max_phys_tcs_per_port,
0470                struct init_qm_port_params port_params[MAX_NUM_PORTS])
0471 {
0472     u32 usable_blocks, pure_lb_blocks, phys_blocks;
0473     u8 tc, ext_voq, port_id, num_tcs_in_port;
0474 
0475     for (port_id = 0; port_id < max_ports_per_engine; port_id++) {
0476         if (!port_params[port_id].active)
0477             continue;
0478 
0479         /* Subtract headroom blocks */
0480         usable_blocks = port_params[port_id].num_btb_blocks -
0481                 BTB_HEADROOM_BLOCKS;
0482 
0483         /* Find blocks per physical TC. Use factor to avoid floating
0484          * arithmethic.
0485          */
0486         num_tcs_in_port = 0;
0487         for (tc = 0; tc < NUM_OF_PHYS_TCS; tc++)
0488             if (((port_params[port_id].active_phys_tcs >>
0489                   tc) & 0x1) == 1)
0490                 num_tcs_in_port++;
0491 
0492         pure_lb_blocks = (usable_blocks * BTB_PURE_LB_FACTOR) /
0493                  (num_tcs_in_port * BTB_PURE_LB_FACTOR +
0494                   BTB_PURE_LB_RATIO);
0495         pure_lb_blocks = max_t(u32, BTB_JUMBO_PKT_BLOCKS,
0496                        pure_lb_blocks / BTB_PURE_LB_FACTOR);
0497         phys_blocks = (usable_blocks - pure_lb_blocks) /
0498                   num_tcs_in_port;
0499 
0500         /* Init physical TCs */
0501         for (tc = 0; tc < NUM_OF_PHYS_TCS; tc++) {
0502             if (((port_params[port_id].active_phys_tcs >>
0503                   tc) & 0x1) == 1) {
0504                 ext_voq =
0505                     qed_get_ext_voq(p_hwfn,
0506                             port_id,
0507                             tc,
0508                             max_phys_tcs_per_port);
0509                 STORE_RT_REG(p_hwfn,
0510                          PBF_BTB_GUARANTEED_RT_OFFSET
0511                          (ext_voq), phys_blocks);
0512             }
0513         }
0514 
0515         /* Init pure LB TC */
0516         ext_voq = qed_get_ext_voq(p_hwfn,
0517                       port_id,
0518                       PURE_LB_TC, max_phys_tcs_per_port);
0519         STORE_RT_REG(p_hwfn, PBF_BTB_GUARANTEED_RT_OFFSET(ext_voq),
0520                  pure_lb_blocks);
0521     }
0522 }
0523 
0524 /* Prepare runtime init values for the specified RL.
0525  * Set max link speed (100Gbps) per rate limiter.
0526  * Return -1 on error.
0527  */
0528 static int qed_global_rl_rt_init(struct qed_hwfn *p_hwfn)
0529 {
0530     u32 upper_bound = QM_GLOBAL_RL_UPPER_BOUND(QM_MAX_LINK_SPEED) |
0531               (u32)QM_RL_CRD_REG_SIGN_BIT;
0532     u32 inc_val;
0533     u16 rl_id;
0534 
0535     /* Go over all global RLs */
0536     for (rl_id = 0; rl_id < MAX_QM_GLOBAL_RLS; rl_id++) {
0537         inc_val = QM_RL_INC_VAL(QM_MAX_LINK_SPEED);
0538 
0539         STORE_RT_REG(p_hwfn,
0540                  QM_REG_RLGLBLCRD_RT_OFFSET + rl_id,
0541                  (u32)QM_RL_CRD_REG_SIGN_BIT);
0542         STORE_RT_REG(p_hwfn,
0543                  QM_REG_RLGLBLUPPERBOUND_RT_OFFSET + rl_id,
0544                  upper_bound);
0545         STORE_RT_REG(p_hwfn,
0546                  QM_REG_RLGLBLINCVAL_RT_OFFSET + rl_id, inc_val);
0547     }
0548 
0549     return 0;
0550 }
0551 
0552 /* Returns the upper bound for the specified Vport RL parameters.
0553  * link_speed is in Mbps.
0554  * Returns 0 in case of error.
0555  */
0556 static u32 qed_get_vport_rl_upper_bound(enum init_qm_rl_type vport_rl_type,
0557                     u32 link_speed)
0558 {
0559     switch (vport_rl_type) {
0560     case QM_RL_TYPE_NORMAL:
0561         return QM_INITIAL_VOQ_BYTE_CRD;
0562     case QM_RL_TYPE_QCN:
0563         return QM_GLOBAL_RL_UPPER_BOUND(link_speed);
0564     default:
0565         return 0;
0566     }
0567 }
0568 
0569 /* Prepare VPORT RL runtime init values.
0570  * Return -1 on error.
0571  */
0572 static int qed_vport_rl_rt_init(struct qed_hwfn *p_hwfn,
0573                 u16 start_rl,
0574                 u16 num_rls,
0575                 u32 link_speed,
0576                 struct init_qm_rl_params *rl_params)
0577 {
0578     u16 i, rl_id;
0579 
0580     if (num_rls && start_rl + num_rls >= MAX_QM_GLOBAL_RLS) {
0581         DP_NOTICE(p_hwfn, "Invalid rate limiter configuration\n");
0582         return -1;
0583     }
0584 
0585     /* Go over all PF VPORTs */
0586     for (i = 0, rl_id = start_rl; i < num_rls; i++, rl_id++) {
0587         u32 upper_bound, inc_val;
0588 
0589         upper_bound =
0590             qed_get_vport_rl_upper_bound((enum init_qm_rl_type)
0591                          rl_params[i].vport_rl_type,
0592                          link_speed);
0593 
0594         inc_val =
0595             QM_RL_INC_VAL(rl_params[i].vport_rl ?
0596                   rl_params[i].vport_rl : link_speed);
0597         if (inc_val > upper_bound) {
0598             DP_NOTICE(p_hwfn,
0599                   "Invalid RL rate - limit configuration\n");
0600             return -1;
0601         }
0602 
0603         STORE_RT_REG(p_hwfn, QM_REG_RLGLBLCRD_RT_OFFSET + rl_id,
0604                  (u32)QM_RL_CRD_REG_SIGN_BIT);
0605         STORE_RT_REG(p_hwfn, QM_REG_RLGLBLUPPERBOUND_RT_OFFSET + rl_id,
0606                  upper_bound | (u32)QM_RL_CRD_REG_SIGN_BIT);
0607         STORE_RT_REG(p_hwfn, QM_REG_RLGLBLINCVAL_RT_OFFSET + rl_id,
0608                  inc_val);
0609     }
0610 
0611     return 0;
0612 }
0613 
0614 /* Prepare Tx PQ mapping runtime init values for the specified PF */
0615 static int qed_tx_pq_map_rt_init(struct qed_hwfn *p_hwfn,
0616                  struct qed_ptt *p_ptt,
0617                  struct qed_qm_pf_rt_init_params *p_params,
0618                  u32 base_mem_addr_4kb)
0619 {
0620     u32 tx_pq_vf_mask[MAX_QM_TX_QUEUES / QM_PF_QUEUE_GROUP_SIZE] = { 0 };
0621     struct init_qm_vport_params *vport_params = p_params->vport_params;
0622     u32 num_tx_pq_vf_masks = MAX_QM_TX_QUEUES / QM_PF_QUEUE_GROUP_SIZE;
0623     u16 num_pqs, first_pq_group, last_pq_group, i, j, pq_id, pq_group;
0624     struct init_qm_pq_params *pq_params = p_params->pq_params;
0625     u32 pq_mem_4kb, vport_pq_mem_4kb, mem_addr_4kb;
0626 
0627     num_pqs = p_params->num_pf_pqs + p_params->num_vf_pqs;
0628 
0629     first_pq_group = p_params->start_pq / QM_PF_QUEUE_GROUP_SIZE;
0630     last_pq_group = (p_params->start_pq + num_pqs - 1) /
0631             QM_PF_QUEUE_GROUP_SIZE;
0632 
0633     pq_mem_4kb = QM_PQ_MEM_4KB(p_params->num_pf_cids);
0634     vport_pq_mem_4kb = QM_PQ_MEM_4KB(p_params->num_vf_cids);
0635     mem_addr_4kb = base_mem_addr_4kb;
0636 
0637     /* Set mapping from PQ group to PF */
0638     for (pq_group = first_pq_group; pq_group <= last_pq_group; pq_group++)
0639         STORE_RT_REG(p_hwfn, QM_REG_PQTX2PF_0_RT_OFFSET + pq_group,
0640                  (u32)(p_params->pf_id));
0641 
0642     /* Set PQ sizes */
0643     STORE_RT_REG(p_hwfn, QM_REG_MAXPQSIZE_0_RT_OFFSET,
0644              QM_PQ_SIZE_256B(p_params->num_pf_cids));
0645     STORE_RT_REG(p_hwfn, QM_REG_MAXPQSIZE_1_RT_OFFSET,
0646              QM_PQ_SIZE_256B(p_params->num_vf_cids));
0647 
0648     /* Go over all Tx PQs */
0649     for (i = 0, pq_id = p_params->start_pq; i < num_pqs; i++, pq_id++) {
0650         u16 *p_first_tx_pq_id, vport_id_in_pf;
0651         struct qm_rf_pq_map tx_pq_map;
0652         u8 tc_id = pq_params[i].tc_id;
0653         bool is_vf_pq;
0654         u8 ext_voq;
0655 
0656         ext_voq = qed_get_ext_voq(p_hwfn,
0657                       pq_params[i].port_id,
0658                       tc_id,
0659                       p_params->max_phys_tcs_per_port);
0660         is_vf_pq = (i >= p_params->num_pf_pqs);
0661 
0662         /* Update first Tx PQ of VPORT/TC */
0663         vport_id_in_pf = pq_params[i].vport_id - p_params->start_vport;
0664         p_first_tx_pq_id =
0665             &vport_params[vport_id_in_pf].first_tx_pq_id[tc_id];
0666         if (*p_first_tx_pq_id == QM_INVALID_PQ_ID) {
0667             u32 map_val =
0668                 (ext_voq << QM_VP_WFQ_PQ_VOQ_SHIFT) |
0669                 (p_params->pf_id << QM_VP_WFQ_PQ_PF_SHIFT);
0670 
0671             /* Create new VP PQ */
0672             *p_first_tx_pq_id = pq_id;
0673 
0674             /* Map VP PQ to VOQ and PF */
0675             STORE_RT_REG(p_hwfn,
0676                      QM_REG_WFQVPMAP_RT_OFFSET +
0677                      *p_first_tx_pq_id,
0678                      map_val);
0679         }
0680 
0681         /* Prepare PQ map entry */
0682         QM_INIT_TX_PQ_MAP(p_hwfn,
0683                   tx_pq_map,
0684                   pq_id,
0685                   *p_first_tx_pq_id,
0686                   pq_params[i].rl_valid,
0687                   pq_params[i].rl_id,
0688                   ext_voq, pq_params[i].wrr_group);
0689 
0690         /* Set PQ base address */
0691         STORE_RT_REG(p_hwfn,
0692                  QM_REG_BASEADDRTXPQ_RT_OFFSET + pq_id,
0693                  mem_addr_4kb);
0694 
0695         /* Clear PQ pointer table entry (64 bit) */
0696         if (p_params->is_pf_loading)
0697             for (j = 0; j < 2; j++)
0698                 STORE_RT_REG(p_hwfn,
0699                          QM_REG_PTRTBLTX_RT_OFFSET +
0700                          (pq_id * 2) + j, 0);
0701 
0702         /* Write PQ info to RAM */
0703         if (WRITE_PQ_INFO_TO_RAM != 0) {
0704             u32 pq_info = 0;
0705 
0706             pq_info = PQ_INFO_ELEMENT(*p_first_tx_pq_id,
0707                           p_params->pf_id,
0708                           tc_id,
0709                           pq_params[i].port_id,
0710                           pq_params[i].rl_valid,
0711                           pq_params[i].rl_id);
0712             qed_wr(p_hwfn, p_ptt, PQ_INFO_RAM_GRC_ADDRESS(pq_id),
0713                    pq_info);
0714         }
0715 
0716         /* If VF PQ, add indication to PQ VF mask */
0717         if (is_vf_pq) {
0718             tx_pq_vf_mask[pq_id /
0719                       QM_PF_QUEUE_GROUP_SIZE] |=
0720                 BIT((pq_id % QM_PF_QUEUE_GROUP_SIZE));
0721             mem_addr_4kb += vport_pq_mem_4kb;
0722         } else {
0723             mem_addr_4kb += pq_mem_4kb;
0724         }
0725     }
0726 
0727     /* Store Tx PQ VF mask to size select register */
0728     for (i = 0; i < num_tx_pq_vf_masks; i++)
0729         if (tx_pq_vf_mask[i])
0730             STORE_RT_REG(p_hwfn,
0731                      QM_REG_MAXPQSIZETXSEL_0_RT_OFFSET + i,
0732                      tx_pq_vf_mask[i]);
0733 
0734     return 0;
0735 }
0736 
0737 /* Prepare Other PQ mapping runtime init values for the specified PF */
0738 static void qed_other_pq_map_rt_init(struct qed_hwfn *p_hwfn,
0739                      u8 pf_id,
0740                      bool is_pf_loading,
0741                      u32 num_pf_cids,
0742                      u32 num_tids, u32 base_mem_addr_4kb)
0743 {
0744     u32 pq_size, pq_mem_4kb, mem_addr_4kb;
0745     u16 i, j, pq_id, pq_group;
0746 
0747     /* A single other PQ group is used in each PF, where PQ group i is used
0748      * in PF i.
0749      */
0750     pq_group = pf_id;
0751     pq_size = num_pf_cids + num_tids;
0752     pq_mem_4kb = QM_PQ_MEM_4KB(pq_size);
0753     mem_addr_4kb = base_mem_addr_4kb;
0754 
0755     /* Map PQ group to PF */
0756     STORE_RT_REG(p_hwfn, QM_REG_PQOTHER2PF_0_RT_OFFSET + pq_group,
0757              (u32)(pf_id));
0758 
0759     /* Set PQ sizes */
0760     STORE_RT_REG(p_hwfn, QM_REG_MAXPQSIZE_2_RT_OFFSET,
0761              QM_PQ_SIZE_256B(pq_size));
0762 
0763     for (i = 0, pq_id = pf_id * QM_PF_QUEUE_GROUP_SIZE;
0764          i < QM_OTHER_PQS_PER_PF; i++, pq_id++) {
0765         /* Set PQ base address */
0766         STORE_RT_REG(p_hwfn,
0767                  QM_REG_BASEADDROTHERPQ_RT_OFFSET + pq_id,
0768                  mem_addr_4kb);
0769 
0770         /* Clear PQ pointer table entry */
0771         if (is_pf_loading)
0772             for (j = 0; j < 2; j++)
0773                 STORE_RT_REG(p_hwfn,
0774                          QM_REG_PTRTBLOTHER_RT_OFFSET +
0775                          (pq_id * 2) + j, 0);
0776 
0777         mem_addr_4kb += pq_mem_4kb;
0778     }
0779 }
0780 
0781 /* Prepare PF WFQ runtime init values for the specified PF.
0782  * Return -1 on error.
0783  */
0784 static int qed_pf_wfq_rt_init(struct qed_hwfn *p_hwfn,
0785                   struct qed_qm_pf_rt_init_params *p_params)
0786 {
0787     u16 num_tx_pqs = p_params->num_pf_pqs + p_params->num_vf_pqs;
0788     struct init_qm_pq_params *pq_params = p_params->pq_params;
0789     u32 inc_val, crd_reg_offset;
0790     u8 ext_voq;
0791     u16 i;
0792 
0793     inc_val = QM_PF_WFQ_INC_VAL(p_params->pf_wfq);
0794     if (!inc_val || inc_val > QM_PF_WFQ_MAX_INC_VAL) {
0795         DP_NOTICE(p_hwfn, "Invalid PF WFQ weight configuration\n");
0796         return -1;
0797     }
0798 
0799     for (i = 0; i < num_tx_pqs; i++) {
0800         ext_voq = qed_get_ext_voq(p_hwfn,
0801                       pq_params[i].port_id,
0802                       pq_params[i].tc_id,
0803                       p_params->max_phys_tcs_per_port);
0804         crd_reg_offset =
0805             (p_params->pf_id < MAX_NUM_PFS_BB ?
0806              QM_REG_WFQPFCRD_RT_OFFSET :
0807              QM_REG_WFQPFCRD_MSB_RT_OFFSET) +
0808             ext_voq * MAX_NUM_PFS_BB +
0809             (p_params->pf_id % MAX_NUM_PFS_BB);
0810         OVERWRITE_RT_REG(p_hwfn,
0811                  crd_reg_offset, (u32)QM_WFQ_CRD_REG_SIGN_BIT);
0812     }
0813 
0814     STORE_RT_REG(p_hwfn,
0815              QM_REG_WFQPFUPPERBOUND_RT_OFFSET + p_params->pf_id,
0816              QM_PF_WFQ_UPPER_BOUND | (u32)QM_WFQ_CRD_REG_SIGN_BIT);
0817     STORE_RT_REG(p_hwfn, QM_REG_WFQPFWEIGHT_RT_OFFSET + p_params->pf_id,
0818              inc_val);
0819 
0820     return 0;
0821 }
0822 
0823 /* Prepare PF RL runtime init values for the specified PF.
0824  * Return -1 on error.
0825  */
0826 static int qed_pf_rl_rt_init(struct qed_hwfn *p_hwfn, u8 pf_id, u32 pf_rl)
0827 {
0828     u32 inc_val = QM_RL_INC_VAL(pf_rl);
0829 
0830     if (inc_val > QM_PF_RL_MAX_INC_VAL) {
0831         DP_NOTICE(p_hwfn, "Invalid PF rate limit configuration\n");
0832         return -1;
0833     }
0834 
0835     STORE_RT_REG(p_hwfn,
0836              QM_REG_RLPFCRD_RT_OFFSET + pf_id,
0837              (u32)QM_RL_CRD_REG_SIGN_BIT);
0838     STORE_RT_REG(p_hwfn,
0839              QM_REG_RLPFUPPERBOUND_RT_OFFSET + pf_id,
0840              QM_PF_RL_UPPER_BOUND | (u32)QM_RL_CRD_REG_SIGN_BIT);
0841     STORE_RT_REG(p_hwfn, QM_REG_RLPFINCVAL_RT_OFFSET + pf_id, inc_val);
0842 
0843     return 0;
0844 }
0845 
0846 /* Prepare VPORT WFQ runtime init values for the specified VPORTs.
0847  * Return -1 on error.
0848  */
0849 static int qed_vp_wfq_rt_init(struct qed_hwfn *p_hwfn,
0850                   u16 num_vports,
0851                   struct init_qm_vport_params *vport_params)
0852 {
0853     u16 vport_pq_id, wfq, i;
0854     u32 inc_val;
0855     u8 tc;
0856 
0857     /* Go over all PF VPORTs */
0858     for (i = 0; i < num_vports; i++) {
0859         /* Each VPORT can have several VPORT PQ IDs for various TCs */
0860         for (tc = 0; tc < NUM_OF_TCS; tc++) {
0861             /* Check if VPORT/TC is valid */
0862             vport_pq_id = vport_params[i].first_tx_pq_id[tc];
0863             if (vport_pq_id == QM_INVALID_PQ_ID)
0864                 continue;
0865 
0866             /* Find WFQ weight (per VPORT or per VPORT+TC) */
0867             wfq = vport_params[i].wfq;
0868             wfq = wfq ? wfq : vport_params[i].tc_wfq[tc];
0869             inc_val = QM_VP_WFQ_INC_VAL(wfq);
0870             if (inc_val > QM_VP_WFQ_MAX_INC_VAL) {
0871                 DP_NOTICE(p_hwfn,
0872                       "Invalid VPORT WFQ weight configuration\n");
0873                 return -1;
0874             }
0875 
0876             /* Config registers */
0877             STORE_RT_REG(p_hwfn, QM_REG_WFQVPCRD_RT_OFFSET +
0878                      vport_pq_id,
0879                      (u32)QM_WFQ_CRD_REG_SIGN_BIT);
0880             STORE_RT_REG(p_hwfn, QM_REG_WFQVPUPPERBOUND_RT_OFFSET +
0881                      vport_pq_id,
0882                      inc_val | QM_WFQ_CRD_REG_SIGN_BIT);
0883             STORE_RT_REG(p_hwfn, QM_REG_WFQVPWEIGHT_RT_OFFSET +
0884                      vport_pq_id, inc_val);
0885         }
0886     }
0887 
0888     return 0;
0889 }
0890 
0891 static bool qed_poll_on_qm_cmd_ready(struct qed_hwfn *p_hwfn,
0892                      struct qed_ptt *p_ptt)
0893 {
0894     u32 reg_val, i;
0895 
0896     for (i = 0, reg_val = 0; i < QM_STOP_CMD_MAX_POLL_COUNT && !reg_val;
0897          i++) {
0898         udelay(QM_STOP_CMD_POLL_PERIOD_US);
0899         reg_val = qed_rd(p_hwfn, p_ptt, QM_REG_SDMCMDREADY);
0900     }
0901 
0902     /* Check if timeout while waiting for SDM command ready */
0903     if (i == QM_STOP_CMD_MAX_POLL_COUNT) {
0904         DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
0905                "Timeout when waiting for QM SDM command ready signal\n");
0906         return false;
0907     }
0908 
0909     return true;
0910 }
0911 
0912 static bool qed_send_qm_cmd(struct qed_hwfn *p_hwfn,
0913                 struct qed_ptt *p_ptt,
0914                 u32 cmd_addr, u32 cmd_data_lsb, u32 cmd_data_msb)
0915 {
0916     if (!qed_poll_on_qm_cmd_ready(p_hwfn, p_ptt))
0917         return false;
0918 
0919     qed_wr(p_hwfn, p_ptt, QM_REG_SDMCMDADDR, cmd_addr);
0920     qed_wr(p_hwfn, p_ptt, QM_REG_SDMCMDDATALSB, cmd_data_lsb);
0921     qed_wr(p_hwfn, p_ptt, QM_REG_SDMCMDDATAMSB, cmd_data_msb);
0922     qed_wr(p_hwfn, p_ptt, QM_REG_SDMCMDGO, 1);
0923     qed_wr(p_hwfn, p_ptt, QM_REG_SDMCMDGO, 0);
0924 
0925     return qed_poll_on_qm_cmd_ready(p_hwfn, p_ptt);
0926 }
0927 
0928 /******************** INTERFACE IMPLEMENTATION *********************/
0929 
0930 u32 qed_qm_pf_mem_size(u32 num_pf_cids,
0931                u32 num_vf_cids,
0932                u32 num_tids, u16 num_pf_pqs, u16 num_vf_pqs)
0933 {
0934     return QM_PQ_MEM_4KB(num_pf_cids) * num_pf_pqs +
0935            QM_PQ_MEM_4KB(num_vf_cids) * num_vf_pqs +
0936            QM_PQ_MEM_4KB(num_pf_cids + num_tids) * QM_OTHER_PQS_PER_PF;
0937 }
0938 
0939 int qed_qm_common_rt_init(struct qed_hwfn *p_hwfn,
0940               struct qed_qm_common_rt_init_params *p_params)
0941 {
0942     u32 mask = 0;
0943 
0944     /* Init AFullOprtnstcCrdMask */
0945     SET_FIELD(mask, QM_RF_OPPORTUNISTIC_MASK_LINEVOQ,
0946           QM_OPPOR_LINE_VOQ_DEF);
0947     SET_FIELD(mask, QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ, QM_BYTE_CRD_EN);
0948     SET_FIELD(mask, QM_RF_OPPORTUNISTIC_MASK_PFWFQ,
0949           p_params->pf_wfq_en ? 1 : 0);
0950     SET_FIELD(mask, QM_RF_OPPORTUNISTIC_MASK_VPWFQ,
0951           p_params->vport_wfq_en ? 1 : 0);
0952     SET_FIELD(mask, QM_RF_OPPORTUNISTIC_MASK_PFRL,
0953           p_params->pf_rl_en ? 1 : 0);
0954     SET_FIELD(mask, QM_RF_OPPORTUNISTIC_MASK_VPQCNRL,
0955           p_params->global_rl_en ? 1 : 0);
0956     SET_FIELD(mask, QM_RF_OPPORTUNISTIC_MASK_FWPAUSE, QM_OPPOR_FW_STOP_DEF);
0957     SET_FIELD(mask,
0958           QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY, QM_OPPOR_PQ_EMPTY_DEF);
0959     STORE_RT_REG(p_hwfn, QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET, mask);
0960 
0961     /* Enable/disable PF RL */
0962     qed_enable_pf_rl(p_hwfn, p_params->pf_rl_en);
0963 
0964     /* Enable/disable PF WFQ */
0965     qed_enable_pf_wfq(p_hwfn, p_params->pf_wfq_en);
0966 
0967     /* Enable/disable global RL */
0968     qed_enable_global_rl(p_hwfn, p_params->global_rl_en);
0969 
0970     /* Enable/disable VPORT WFQ */
0971     qed_enable_vport_wfq(p_hwfn, p_params->vport_wfq_en);
0972 
0973     /* Init PBF CMDQ line credit */
0974     qed_cmdq_lines_rt_init(p_hwfn,
0975                    p_params->max_ports_per_engine,
0976                    p_params->max_phys_tcs_per_port,
0977                    p_params->port_params);
0978 
0979     /* Init BTB blocks in PBF */
0980     qed_btb_blocks_rt_init(p_hwfn,
0981                    p_params->max_ports_per_engine,
0982                    p_params->max_phys_tcs_per_port,
0983                    p_params->port_params);
0984 
0985     qed_global_rl_rt_init(p_hwfn);
0986 
0987     return 0;
0988 }
0989 
0990 int qed_qm_pf_rt_init(struct qed_hwfn *p_hwfn,
0991               struct qed_ptt *p_ptt,
0992               struct qed_qm_pf_rt_init_params *p_params)
0993 {
0994     struct init_qm_vport_params *vport_params = p_params->vport_params;
0995     u32 other_mem_size_4kb = QM_PQ_MEM_4KB(p_params->num_pf_cids +
0996                            p_params->num_tids) *
0997                  QM_OTHER_PQS_PER_PF;
0998     u16 i;
0999     u8 tc;
1000 
1001     /* Clear first Tx PQ ID array for each VPORT */
1002     for (i = 0; i < p_params->num_vports; i++)
1003         for (tc = 0; tc < NUM_OF_TCS; tc++)
1004             vport_params[i].first_tx_pq_id[tc] = QM_INVALID_PQ_ID;
1005 
1006     /* Map Other PQs (if any) */
1007     qed_other_pq_map_rt_init(p_hwfn,
1008                  p_params->pf_id,
1009                  p_params->is_pf_loading, p_params->num_pf_cids,
1010                  p_params->num_tids, 0);
1011 
1012     /* Map Tx PQs */
1013     if (qed_tx_pq_map_rt_init(p_hwfn, p_ptt, p_params, other_mem_size_4kb))
1014         return -1;
1015 
1016     /* Init PF WFQ */
1017     if (p_params->pf_wfq)
1018         if (qed_pf_wfq_rt_init(p_hwfn, p_params))
1019             return -1;
1020 
1021     /* Init PF RL */
1022     if (qed_pf_rl_rt_init(p_hwfn, p_params->pf_id, p_params->pf_rl))
1023         return -1;
1024 
1025     /* Init VPORT WFQ */
1026     if (qed_vp_wfq_rt_init(p_hwfn, p_params->num_vports, vport_params))
1027         return -1;
1028 
1029     /* Set VPORT RL */
1030     if (qed_vport_rl_rt_init(p_hwfn, p_params->start_rl,
1031                  p_params->num_rls, p_params->link_speed,
1032                  p_params->rl_params))
1033         return -1;
1034 
1035     return 0;
1036 }
1037 
1038 int qed_init_pf_wfq(struct qed_hwfn *p_hwfn,
1039             struct qed_ptt *p_ptt, u8 pf_id, u16 pf_wfq)
1040 {
1041     u32 inc_val = QM_PF_WFQ_INC_VAL(pf_wfq);
1042 
1043     if (!inc_val || inc_val > QM_PF_WFQ_MAX_INC_VAL) {
1044         DP_NOTICE(p_hwfn, "Invalid PF WFQ weight configuration\n");
1045         return -1;
1046     }
1047 
1048     qed_wr(p_hwfn, p_ptt, QM_REG_WFQPFWEIGHT + pf_id * 4, inc_val);
1049 
1050     return 0;
1051 }
1052 
1053 int qed_init_pf_rl(struct qed_hwfn *p_hwfn,
1054            struct qed_ptt *p_ptt, u8 pf_id, u32 pf_rl)
1055 {
1056     u32 inc_val = QM_RL_INC_VAL(pf_rl);
1057 
1058     if (inc_val > QM_PF_RL_MAX_INC_VAL) {
1059         DP_NOTICE(p_hwfn, "Invalid PF rate limit configuration\n");
1060         return -1;
1061     }
1062 
1063     qed_wr(p_hwfn,
1064            p_ptt, QM_REG_RLPFCRD + pf_id * 4, (u32)QM_RL_CRD_REG_SIGN_BIT);
1065     qed_wr(p_hwfn, p_ptt, QM_REG_RLPFINCVAL + pf_id * 4, inc_val);
1066 
1067     return 0;
1068 }
1069 
1070 int qed_init_vport_wfq(struct qed_hwfn *p_hwfn,
1071                struct qed_ptt *p_ptt,
1072                u16 first_tx_pq_id[NUM_OF_TCS], u16 wfq)
1073 {
1074     int result = 0;
1075     u16 vport_pq_id;
1076     u8 tc;
1077 
1078     for (tc = 0; tc < NUM_OF_TCS && !result; tc++) {
1079         vport_pq_id = first_tx_pq_id[tc];
1080         if (vport_pq_id != QM_INVALID_PQ_ID)
1081             result = qed_init_vport_tc_wfq(p_hwfn, p_ptt,
1082                                vport_pq_id, wfq);
1083     }
1084 
1085     return result;
1086 }
1087 
1088 int qed_init_vport_tc_wfq(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
1089               u16 first_tx_pq_id, u16 wfq)
1090 {
1091     u32 inc_val;
1092 
1093     if (first_tx_pq_id == QM_INVALID_PQ_ID)
1094         return -1;
1095 
1096     inc_val = QM_VP_WFQ_INC_VAL(wfq);
1097     if (!inc_val || inc_val > QM_VP_WFQ_MAX_INC_VAL) {
1098         DP_NOTICE(p_hwfn, "Invalid VPORT WFQ configuration.\n");
1099         return -1;
1100     }
1101 
1102     qed_wr(p_hwfn, p_ptt, QM_REG_WFQVPCRD + first_tx_pq_id * 4,
1103            (u32)QM_WFQ_CRD_REG_SIGN_BIT);
1104     qed_wr(p_hwfn, p_ptt, QM_REG_WFQVPUPPERBOUND + first_tx_pq_id * 4,
1105            inc_val | QM_WFQ_CRD_REG_SIGN_BIT);
1106     qed_wr(p_hwfn, p_ptt, QM_REG_WFQVPWEIGHT + first_tx_pq_id * 4,
1107            inc_val);
1108 
1109     return 0;
1110 }
1111 
1112 int qed_init_global_rl(struct qed_hwfn *p_hwfn,
1113                struct qed_ptt *p_ptt, u16 rl_id, u32 rate_limit,
1114                enum init_qm_rl_type vport_rl_type)
1115 {
1116     u32 inc_val, upper_bound;
1117 
1118     upper_bound =
1119         (vport_rl_type ==
1120          QM_RL_TYPE_QCN) ? QM_GLOBAL_RL_UPPER_BOUND(QM_MAX_LINK_SPEED) :
1121         QM_INITIAL_VOQ_BYTE_CRD;
1122     inc_val = QM_RL_INC_VAL(rate_limit);
1123     if (inc_val > upper_bound) {
1124         DP_NOTICE(p_hwfn, "Invalid VPORT rate limit configuration.\n");
1125         return -1;
1126     }
1127 
1128     qed_wr(p_hwfn, p_ptt,
1129            QM_REG_RLGLBLCRD + rl_id * 4, (u32)QM_RL_CRD_REG_SIGN_BIT);
1130     qed_wr(p_hwfn,
1131            p_ptt,
1132            QM_REG_RLGLBLUPPERBOUND + rl_id * 4,
1133            upper_bound | (u32)QM_RL_CRD_REG_SIGN_BIT);
1134     qed_wr(p_hwfn, p_ptt, QM_REG_RLGLBLINCVAL + rl_id * 4, inc_val);
1135 
1136     return 0;
1137 }
1138 
1139 bool qed_send_qm_stop_cmd(struct qed_hwfn *p_hwfn,
1140               struct qed_ptt *p_ptt,
1141               bool is_release_cmd,
1142               bool is_tx_pq, u16 start_pq, u16 num_pqs)
1143 {
1144     u32 cmd_arr[QM_CMD_STRUCT_SIZE(QM_STOP_CMD)] = { 0 };
1145     u32 pq_mask = 0, last_pq, pq_id;
1146 
1147     last_pq = start_pq + num_pqs - 1;
1148 
1149     /* Set command's PQ type */
1150     QM_CMD_SET_FIELD(cmd_arr, QM_STOP_CMD, PQ_TYPE, is_tx_pq ? 0 : 1);
1151 
1152     /* Go over requested PQs */
1153     for (pq_id = start_pq; pq_id <= last_pq; pq_id++) {
1154         /* Set PQ bit in mask (stop command only) */
1155         if (!is_release_cmd)
1156             pq_mask |= BIT((pq_id % QM_STOP_PQ_MASK_WIDTH));
1157 
1158         /* If last PQ or end of PQ mask, write command */
1159         if ((pq_id == last_pq) ||
1160             (pq_id % QM_STOP_PQ_MASK_WIDTH ==
1161              (QM_STOP_PQ_MASK_WIDTH - 1))) {
1162             QM_CMD_SET_FIELD(cmd_arr,
1163                      QM_STOP_CMD, PAUSE_MASK, pq_mask);
1164             QM_CMD_SET_FIELD(cmd_arr,
1165                      QM_STOP_CMD,
1166                      GROUP_ID,
1167                      pq_id / QM_STOP_PQ_MASK_WIDTH);
1168             if (!qed_send_qm_cmd(p_hwfn, p_ptt, QM_STOP_CMD_ADDR,
1169                          cmd_arr[0], cmd_arr[1]))
1170                 return false;
1171             pq_mask = 0;
1172         }
1173     }
1174 
1175     return true;
1176 }
1177 
1178 #define SET_TUNNEL_TYPE_ENABLE_BIT(var, offset, enable) \
1179     do { \
1180         typeof(var) *__p_var = &(var); \
1181         typeof(offset) __offset = offset; \
1182         *__p_var = (*__p_var & ~BIT(__offset)) | \
1183                ((enable) ? BIT(__offset) : 0); \
1184     } while (0)
1185 
1186 #define PRS_ETH_TUNN_OUTPUT_FORMAT     0xF4DAB910
1187 #define PRS_ETH_OUTPUT_FORMAT          0xFFFF4910
1188 
1189 #define ARR_REG_WR(dev, ptt, addr, arr, arr_size) \
1190     do { \
1191         u32 i; \
1192         \
1193         for (i = 0; i < (arr_size); i++) \
1194             qed_wr(dev, ptt, \
1195                    ((addr) + (4 * i)), \
1196                    ((u32 *)&(arr))[i]); \
1197     } while (0)
1198 
1199 /**
1200  * qed_dmae_to_grc() - Internal function for writing from host to
1201  * wide-bus registers (split registers are not supported yet).
1202  *
1203  * @p_hwfn: HW device data.
1204  * @p_ptt: PTT window used for writing the registers.
1205  * @p_data: Pointer to source data.
1206  * @addr: Destination register address.
1207  * @len_in_dwords: Data length in dwords (u32).
1208  *
1209  * Return: Length of the written data in dwords (u32) or -1 on invalid
1210  *         input.
1211  */
1212 static int qed_dmae_to_grc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
1213                __le32 *p_data, u32 addr, u32 len_in_dwords)
1214 {
1215     struct qed_dmae_params params = { 0 };
1216     u32 *data_cpu;
1217     int rc;
1218 
1219     if (!p_data)
1220         return -1;
1221 
1222     /* Set DMAE params */
1223     SET_FIELD(params.flags, QED_DMAE_PARAMS_COMPLETION_DST, 1);
1224 
1225     /* Execute DMAE command */
1226     rc = qed_dmae_host2grc(p_hwfn, p_ptt,
1227                    (u64)(uintptr_t)(p_data),
1228                    addr, len_in_dwords, &params);
1229 
1230     /* If not read using DMAE, read using GRC */
1231     if (rc) {
1232         DP_VERBOSE(p_hwfn,
1233                QED_MSG_DEBUG,
1234                "Failed writing to chip using DMAE, using GRC instead\n");
1235 
1236         /* Swap to CPU byteorder and write to registers using GRC */
1237         data_cpu = (__force u32 *)p_data;
1238         le32_to_cpu_array(data_cpu, len_in_dwords);
1239 
1240         ARR_REG_WR(p_hwfn, p_ptt, addr, data_cpu, len_in_dwords);
1241         cpu_to_le32_array(data_cpu, len_in_dwords);
1242     }
1243 
1244     return len_in_dwords;
1245 }
1246 
1247 void qed_set_vxlan_dest_port(struct qed_hwfn *p_hwfn,
1248                  struct qed_ptt *p_ptt, u16 dest_port)
1249 {
1250     /* Update PRS register */
1251     qed_wr(p_hwfn, p_ptt, PRS_REG_VXLAN_PORT, dest_port);
1252 
1253     /* Update NIG register */
1254     qed_wr(p_hwfn, p_ptt, NIG_REG_VXLAN_CTRL, dest_port);
1255 
1256     /* Update PBF register */
1257     qed_wr(p_hwfn, p_ptt, PBF_REG_VXLAN_PORT, dest_port);
1258 }
1259 
1260 void qed_set_vxlan_enable(struct qed_hwfn *p_hwfn,
1261               struct qed_ptt *p_ptt, bool vxlan_enable)
1262 {
1263     u32 reg_val;
1264     u8 shift;
1265 
1266     /* Update PRS register */
1267     reg_val = qed_rd(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN);
1268     SET_FIELD(reg_val,
1269           PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE, vxlan_enable);
1270     qed_wr(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN, reg_val);
1271     if (reg_val) {
1272         reg_val =
1273             qed_rd(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0);
1274 
1275         /* Update output  only if tunnel blocks not included. */
1276         if (reg_val == (u32)PRS_ETH_OUTPUT_FORMAT)
1277             qed_wr(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0,
1278                    (u32)PRS_ETH_TUNN_OUTPUT_FORMAT);
1279     }
1280 
1281     /* Update NIG register */
1282     reg_val = qed_rd(p_hwfn, p_ptt, NIG_REG_ENC_TYPE_ENABLE);
1283     shift = NIG_REG_ENC_TYPE_ENABLE_VXLAN_ENABLE_SHIFT;
1284     SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, shift, vxlan_enable);
1285     qed_wr(p_hwfn, p_ptt, NIG_REG_ENC_TYPE_ENABLE, reg_val);
1286 
1287     /* Update DORQ register */
1288     qed_wr(p_hwfn,
1289            p_ptt, DORQ_REG_L2_EDPM_TUNNEL_VXLAN_EN, vxlan_enable ? 1 : 0);
1290 }
1291 
1292 void qed_set_gre_enable(struct qed_hwfn *p_hwfn,
1293             struct qed_ptt *p_ptt,
1294             bool eth_gre_enable, bool ip_gre_enable)
1295 {
1296     u32 reg_val;
1297     u8 shift;
1298 
1299     /* Update PRS register */
1300     reg_val = qed_rd(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN);
1301     SET_FIELD(reg_val,
1302           PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE,
1303           eth_gre_enable);
1304     SET_FIELD(reg_val,
1305           PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE,
1306           ip_gre_enable);
1307     qed_wr(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN, reg_val);
1308     if (reg_val) {
1309         reg_val =
1310             qed_rd(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0);
1311 
1312         /* Update output  only if tunnel blocks not included. */
1313         if (reg_val == (u32)PRS_ETH_OUTPUT_FORMAT)
1314             qed_wr(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0,
1315                    (u32)PRS_ETH_TUNN_OUTPUT_FORMAT);
1316     }
1317 
1318     /* Update NIG register */
1319     reg_val = qed_rd(p_hwfn, p_ptt, NIG_REG_ENC_TYPE_ENABLE);
1320     shift = NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE_SHIFT;
1321     SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, shift, eth_gre_enable);
1322     shift = NIG_REG_ENC_TYPE_ENABLE_IP_OVER_GRE_ENABLE_SHIFT;
1323     SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, shift, ip_gre_enable);
1324     qed_wr(p_hwfn, p_ptt, NIG_REG_ENC_TYPE_ENABLE, reg_val);
1325 
1326     /* Update DORQ registers */
1327     qed_wr(p_hwfn,
1328            p_ptt,
1329            DORQ_REG_L2_EDPM_TUNNEL_GRE_ETH_EN, eth_gre_enable ? 1 : 0);
1330     qed_wr(p_hwfn,
1331            p_ptt, DORQ_REG_L2_EDPM_TUNNEL_GRE_IP_EN, ip_gre_enable ? 1 : 0);
1332 }
1333 
1334 void qed_set_geneve_dest_port(struct qed_hwfn *p_hwfn,
1335                   struct qed_ptt *p_ptt, u16 dest_port)
1336 {
1337     /* Update PRS register */
1338     qed_wr(p_hwfn, p_ptt, PRS_REG_NGE_PORT, dest_port);
1339 
1340     /* Update NIG register */
1341     qed_wr(p_hwfn, p_ptt, NIG_REG_NGE_PORT, dest_port);
1342 
1343     /* Update PBF register */
1344     qed_wr(p_hwfn, p_ptt, PBF_REG_NGE_PORT, dest_port);
1345 }
1346 
1347 void qed_set_geneve_enable(struct qed_hwfn *p_hwfn,
1348                struct qed_ptt *p_ptt,
1349                bool eth_geneve_enable, bool ip_geneve_enable)
1350 {
1351     u32 reg_val;
1352 
1353     /* Update PRS register */
1354     reg_val = qed_rd(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN);
1355     SET_FIELD(reg_val,
1356           PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE,
1357           eth_geneve_enable);
1358     SET_FIELD(reg_val,
1359           PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE,
1360           ip_geneve_enable);
1361     qed_wr(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN, reg_val);
1362     if (reg_val) {
1363         reg_val =
1364             qed_rd(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0);
1365 
1366         /* Update output  only if tunnel blocks not included. */
1367         if (reg_val == (u32)PRS_ETH_OUTPUT_FORMAT)
1368             qed_wr(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0,
1369                    (u32)PRS_ETH_TUNN_OUTPUT_FORMAT);
1370     }
1371 
1372     /* Update NIG register */
1373     qed_wr(p_hwfn, p_ptt, NIG_REG_NGE_ETH_ENABLE,
1374            eth_geneve_enable ? 1 : 0);
1375     qed_wr(p_hwfn, p_ptt, NIG_REG_NGE_IP_ENABLE, ip_geneve_enable ? 1 : 0);
1376 
1377     /* EDPM with geneve tunnel not supported in BB */
1378     if (QED_IS_BB_B0(p_hwfn->cdev))
1379         return;
1380 
1381     /* Update DORQ registers */
1382     qed_wr(p_hwfn,
1383            p_ptt,
1384            DORQ_REG_L2_EDPM_TUNNEL_NGE_ETH_EN_K2,
1385            eth_geneve_enable ? 1 : 0);
1386     qed_wr(p_hwfn,
1387            p_ptt,
1388            DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN_K2,
1389            ip_geneve_enable ? 1 : 0);
1390 }
1391 
1392 #define PRS_ETH_VXLAN_NO_L2_ENABLE_OFFSET      3
1393 #define PRS_ETH_VXLAN_NO_L2_OUTPUT_FORMAT   0xC8DAB910
1394 
1395 void qed_set_vxlan_no_l2_enable(struct qed_hwfn *p_hwfn,
1396                 struct qed_ptt *p_ptt, bool enable)
1397 {
1398     u32 reg_val, cfg_mask;
1399 
1400     /* read PRS config register */
1401     reg_val = qed_rd(p_hwfn, p_ptt, PRS_REG_MSG_INFO);
1402 
1403     /* set VXLAN_NO_L2_ENABLE mask */
1404     cfg_mask = BIT(PRS_ETH_VXLAN_NO_L2_ENABLE_OFFSET);
1405 
1406     if (enable) {
1407         /* set VXLAN_NO_L2_ENABLE flag */
1408         reg_val |= cfg_mask;
1409 
1410         /* update PRS FIC  register */
1411         qed_wr(p_hwfn,
1412                p_ptt,
1413                PRS_REG_OUTPUT_FORMAT_4_0,
1414                (u32)PRS_ETH_VXLAN_NO_L2_OUTPUT_FORMAT);
1415     } else {
1416         /* clear VXLAN_NO_L2_ENABLE flag */
1417         reg_val &= ~cfg_mask;
1418     }
1419 
1420     /* write PRS config register */
1421     qed_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, reg_val);
1422 }
1423 
1424 #define T_ETH_PACKET_ACTION_GFT_EVENTID  23
1425 #define PARSER_ETH_CONN_GFT_ACTION_CM_HDR  272
1426 #define T_ETH_PACKET_MATCH_RFS_EVENTID 25
1427 #define PARSER_ETH_CONN_CM_HDR 0
1428 #define CAM_LINE_SIZE sizeof(u32)
1429 #define RAM_LINE_SIZE sizeof(u64)
1430 #define REG_SIZE sizeof(u32)
1431 
1432 void qed_gft_disable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, u16 pf_id)
1433 {
1434     struct regpair ram_line = { 0 };
1435 
1436     /* Disable gft search for PF */
1437     qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_GFT, 0);
1438 
1439     /* Clean ram & cam for next gft session */
1440 
1441     /* Zero camline */
1442     qed_wr(p_hwfn, p_ptt, PRS_REG_GFT_CAM + CAM_LINE_SIZE * pf_id, 0);
1443 
1444     /* Zero ramline */
1445     qed_dmae_to_grc(p_hwfn, p_ptt, &ram_line.lo,
1446             PRS_REG_GFT_PROFILE_MASK_RAM + RAM_LINE_SIZE * pf_id,
1447             sizeof(ram_line) / REG_SIZE);
1448 }
1449 
1450 void qed_gft_config(struct qed_hwfn *p_hwfn,
1451             struct qed_ptt *p_ptt,
1452             u16 pf_id,
1453             bool tcp,
1454             bool udp,
1455             bool ipv4, bool ipv6, enum gft_profile_type profile_type)
1456 {
1457     struct regpair ram_line;
1458     u32 search_non_ip_as_gft;
1459     u32 reg_val, cam_line;
1460     u32 lo = 0, hi = 0;
1461 
1462     if (!ipv6 && !ipv4)
1463         DP_NOTICE(p_hwfn,
1464               "gft_config: must accept at least on of - ipv4 or ipv6'\n");
1465     if (!tcp && !udp)
1466         DP_NOTICE(p_hwfn,
1467               "gft_config: must accept at least on of - udp or tcp\n");
1468     if (profile_type >= MAX_GFT_PROFILE_TYPE)
1469         DP_NOTICE(p_hwfn, "gft_config: unsupported gft_profile_type\n");
1470 
1471     /* Set RFS event ID to be awakened i Tstorm By Prs */
1472     reg_val = T_ETH_PACKET_MATCH_RFS_EVENTID <<
1473           PRS_REG_CM_HDR_GFT_EVENT_ID_SHIFT;
1474     reg_val |= PARSER_ETH_CONN_CM_HDR << PRS_REG_CM_HDR_GFT_CM_HDR_SHIFT;
1475     qed_wr(p_hwfn, p_ptt, PRS_REG_CM_HDR_GFT, reg_val);
1476 
1477     /* Do not load context only cid in PRS on match. */
1478     qed_wr(p_hwfn, p_ptt, PRS_REG_LOAD_L2_FILTER, 0);
1479 
1480     /* Do not use tenant ID exist bit for gft search */
1481     qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TENANT_ID, 0);
1482 
1483     /* Set Cam */
1484     cam_line = 0;
1485     SET_FIELD(cam_line, GFT_CAM_LINE_MAPPED_VALID, 1);
1486 
1487     /* Filters are per PF!! */
1488     SET_FIELD(cam_line,
1489           GFT_CAM_LINE_MAPPED_PF_ID_MASK,
1490           GFT_CAM_LINE_MAPPED_PF_ID_MASK_MASK);
1491     SET_FIELD(cam_line, GFT_CAM_LINE_MAPPED_PF_ID, pf_id);
1492 
1493     if (!(tcp && udp)) {
1494         SET_FIELD(cam_line,
1495               GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK,
1496               GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_MASK);
1497         if (tcp)
1498             SET_FIELD(cam_line,
1499                   GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE,
1500                   GFT_PROFILE_TCP_PROTOCOL);
1501         else
1502             SET_FIELD(cam_line,
1503                   GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE,
1504                   GFT_PROFILE_UDP_PROTOCOL);
1505     }
1506 
1507     if (!(ipv4 && ipv6)) {
1508         SET_FIELD(cam_line, GFT_CAM_LINE_MAPPED_IP_VERSION_MASK, 1);
1509         if (ipv4)
1510             SET_FIELD(cam_line,
1511                   GFT_CAM_LINE_MAPPED_IP_VERSION,
1512                   GFT_PROFILE_IPV4);
1513         else
1514             SET_FIELD(cam_line,
1515                   GFT_CAM_LINE_MAPPED_IP_VERSION,
1516                   GFT_PROFILE_IPV6);
1517     }
1518 
1519     /* Write characteristics to cam */
1520     qed_wr(p_hwfn, p_ptt, PRS_REG_GFT_CAM + CAM_LINE_SIZE * pf_id,
1521            cam_line);
1522     cam_line =
1523         qed_rd(p_hwfn, p_ptt, PRS_REG_GFT_CAM + CAM_LINE_SIZE * pf_id);
1524 
1525     /* Write line to RAM - compare to filter 4 tuple */
1526 
1527     /* Search no IP as GFT */
1528     search_non_ip_as_gft = 0;
1529 
1530     /* Tunnel type */
1531     SET_FIELD(lo, GFT_RAM_LINE_TUNNEL_DST_PORT, 1);
1532     SET_FIELD(lo, GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL, 1);
1533 
1534     if (profile_type == GFT_PROFILE_TYPE_4_TUPLE) {
1535         SET_FIELD(hi, GFT_RAM_LINE_DST_IP, 1);
1536         SET_FIELD(hi, GFT_RAM_LINE_SRC_IP, 1);
1537         SET_FIELD(hi, GFT_RAM_LINE_OVER_IP_PROTOCOL, 1);
1538         SET_FIELD(lo, GFT_RAM_LINE_ETHERTYPE, 1);
1539         SET_FIELD(lo, GFT_RAM_LINE_SRC_PORT, 1);
1540         SET_FIELD(lo, GFT_RAM_LINE_DST_PORT, 1);
1541     } else if (profile_type == GFT_PROFILE_TYPE_L4_DST_PORT) {
1542         SET_FIELD(hi, GFT_RAM_LINE_OVER_IP_PROTOCOL, 1);
1543         SET_FIELD(lo, GFT_RAM_LINE_ETHERTYPE, 1);
1544         SET_FIELD(lo, GFT_RAM_LINE_DST_PORT, 1);
1545     } else if (profile_type == GFT_PROFILE_TYPE_IP_DST_ADDR) {
1546         SET_FIELD(hi, GFT_RAM_LINE_DST_IP, 1);
1547         SET_FIELD(lo, GFT_RAM_LINE_ETHERTYPE, 1);
1548     } else if (profile_type == GFT_PROFILE_TYPE_IP_SRC_ADDR) {
1549         SET_FIELD(hi, GFT_RAM_LINE_SRC_IP, 1);
1550         SET_FIELD(lo, GFT_RAM_LINE_ETHERTYPE, 1);
1551     } else if (profile_type == GFT_PROFILE_TYPE_TUNNEL_TYPE) {
1552         SET_FIELD(lo, GFT_RAM_LINE_TUNNEL_ETHERTYPE, 1);
1553 
1554         /* Allow tunneled traffic without inner IP */
1555         search_non_ip_as_gft = 1;
1556     }
1557 
1558     ram_line.lo = cpu_to_le32(lo);
1559     ram_line.hi = cpu_to_le32(hi);
1560 
1561     qed_wr(p_hwfn,
1562            p_ptt, PRS_REG_SEARCH_NON_IP_AS_GFT, search_non_ip_as_gft);
1563     qed_dmae_to_grc(p_hwfn, p_ptt, &ram_line.lo,
1564             PRS_REG_GFT_PROFILE_MASK_RAM + RAM_LINE_SIZE * pf_id,
1565             sizeof(ram_line) / REG_SIZE);
1566 
1567     /* Set default profile so that no filter match will happen */
1568     ram_line.lo = cpu_to_le32(0xffffffff);
1569     ram_line.hi = cpu_to_le32(0x3ff);
1570     qed_dmae_to_grc(p_hwfn, p_ptt, &ram_line.lo,
1571             PRS_REG_GFT_PROFILE_MASK_RAM + RAM_LINE_SIZE *
1572             PRS_GFT_CAM_LINES_NO_MATCH,
1573             sizeof(ram_line) / REG_SIZE);
1574 
1575     /* Enable gft search */
1576     qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_GFT, 1);
1577 }
1578 
1579 DECLARE_CRC8_TABLE(cdu_crc8_table);
1580 
1581 /* Calculate and return CDU validation byte per connection type/region/cid */
1582 static u8 qed_calc_cdu_validation_byte(u8 conn_type, u8 region, u32 cid)
1583 {
1584     const u8 validation_cfg = CDU_VALIDATION_DEFAULT_CFG;
1585     u8 crc, validation_byte = 0;
1586     static u8 crc8_table_valid; /* automatically initialized to 0 */
1587     u32 validation_string = 0;
1588     __be32 data_to_crc;
1589 
1590     if (!crc8_table_valid) {
1591         crc8_populate_msb(cdu_crc8_table, 0x07);
1592         crc8_table_valid = 1;
1593     }
1594 
1595     /* The CRC is calculated on the String-to-compress:
1596      * [31:8]  = {CID[31:20],CID[11:0]}
1597      * [7:4]   = Region
1598      * [3:0]   = Type
1599      */
1600     if ((validation_cfg >> CDU_CONTEXT_VALIDATION_CFG_USE_CID) & 1)
1601         validation_string |= (cid & 0xFFF00000) | ((cid & 0xFFF) << 8);
1602 
1603     if ((validation_cfg >> CDU_CONTEXT_VALIDATION_CFG_USE_REGION) & 1)
1604         validation_string |= ((region & 0xF) << 4);
1605 
1606     if ((validation_cfg >> CDU_CONTEXT_VALIDATION_CFG_USE_TYPE) & 1)
1607         validation_string |= (conn_type & 0xF);
1608 
1609     /* Convert to big-endian and calculate CRC8 */
1610     data_to_crc = cpu_to_be32(validation_string);
1611     crc = crc8(cdu_crc8_table, (u8 *)&data_to_crc, sizeof(data_to_crc),
1612            CRC8_INIT_VALUE);
1613 
1614     /* The validation byte [7:0] is composed:
1615      * for type A validation
1616      * [7]          = active configuration bit
1617      * [6:0]        = crc[6:0]
1618      *
1619      * for type B validation
1620      * [7]          = active configuration bit
1621      * [6:3]        = connection_type[3:0]
1622      * [2:0]        = crc[2:0]
1623      */
1624     validation_byte |=
1625         ((validation_cfg >>
1626           CDU_CONTEXT_VALIDATION_CFG_USE_ACTIVE) & 1) << 7;
1627 
1628     if ((validation_cfg >>
1629          CDU_CONTEXT_VALIDATION_CFG_VALIDATION_TYPE_SHIFT) & 1)
1630         validation_byte |= ((conn_type & 0xF) << 3) | (crc & 0x7);
1631     else
1632         validation_byte |= crc & 0x7F;
1633 
1634     return validation_byte;
1635 }
1636 
1637 /* Calcualte and set validation bytes for session context */
1638 void qed_calc_session_ctx_validation(void *p_ctx_mem,
1639                      u16 ctx_size, u8 ctx_type, u32 cid)
1640 {
1641     u8 *x_val_ptr, *t_val_ptr, *u_val_ptr, *p_ctx;
1642 
1643     p_ctx = (u8 * const)p_ctx_mem;
1644     x_val_ptr = &p_ctx[con_region_offsets[0][ctx_type]];
1645     t_val_ptr = &p_ctx[con_region_offsets[1][ctx_type]];
1646     u_val_ptr = &p_ctx[con_region_offsets[2][ctx_type]];
1647 
1648     memset(p_ctx, 0, ctx_size);
1649 
1650     *x_val_ptr = qed_calc_cdu_validation_byte(ctx_type, 3, cid);
1651     *t_val_ptr = qed_calc_cdu_validation_byte(ctx_type, 4, cid);
1652     *u_val_ptr = qed_calc_cdu_validation_byte(ctx_type, 5, cid);
1653 }
1654 
1655 /* Calcualte and set validation bytes for task context */
1656 void qed_calc_task_ctx_validation(void *p_ctx_mem,
1657                   u16 ctx_size, u8 ctx_type, u32 tid)
1658 {
1659     u8 *p_ctx, *region1_val_ptr;
1660 
1661     p_ctx = (u8 * const)p_ctx_mem;
1662     region1_val_ptr = &p_ctx[task_region_offsets[0][ctx_type]];
1663 
1664     memset(p_ctx, 0, ctx_size);
1665 
1666     *region1_val_ptr = qed_calc_cdu_validation_byte(ctx_type, 1, tid);
1667 }
1668 
1669 /* Memset session context to 0 while preserving validation bytes */
1670 void qed_memset_session_ctx(void *p_ctx_mem, u32 ctx_size, u8 ctx_type)
1671 {
1672     u8 *x_val_ptr, *t_val_ptr, *u_val_ptr, *p_ctx;
1673     u8 x_val, t_val, u_val;
1674 
1675     p_ctx = (u8 * const)p_ctx_mem;
1676     x_val_ptr = &p_ctx[con_region_offsets[0][ctx_type]];
1677     t_val_ptr = &p_ctx[con_region_offsets[1][ctx_type]];
1678     u_val_ptr = &p_ctx[con_region_offsets[2][ctx_type]];
1679 
1680     x_val = *x_val_ptr;
1681     t_val = *t_val_ptr;
1682     u_val = *u_val_ptr;
1683 
1684     memset(p_ctx, 0, ctx_size);
1685 
1686     *x_val_ptr = x_val;
1687     *t_val_ptr = t_val;
1688     *u_val_ptr = u_val;
1689 }
1690 
1691 /* Memset task context to 0 while preserving validation bytes */
1692 void qed_memset_task_ctx(void *p_ctx_mem, u32 ctx_size, u8 ctx_type)
1693 {
1694     u8 *p_ctx, *region1_val_ptr;
1695     u8 region1_val;
1696 
1697     p_ctx = (u8 * const)p_ctx_mem;
1698     region1_val_ptr = &p_ctx[task_region_offsets[0][ctx_type]];
1699 
1700     region1_val = *region1_val_ptr;
1701 
1702     memset(p_ctx, 0, ctx_size);
1703 
1704     *region1_val_ptr = region1_val;
1705 }
1706 
1707 /* Enable and configure context validation */
1708 void qed_enable_context_validation(struct qed_hwfn *p_hwfn,
1709                    struct qed_ptt *p_ptt)
1710 {
1711     u32 ctx_validation;
1712 
1713     /* Enable validation for connection region 3: CCFC_CTX_VALID0[31:24] */
1714     ctx_validation = CDU_VALIDATION_DEFAULT_CFG << 24;
1715     qed_wr(p_hwfn, p_ptt, CDU_REG_CCFC_CTX_VALID0, ctx_validation);
1716 
1717     /* Enable validation for connection region 5: CCFC_CTX_VALID1[15:8] */
1718     ctx_validation = CDU_VALIDATION_DEFAULT_CFG << 8;
1719     qed_wr(p_hwfn, p_ptt, CDU_REG_CCFC_CTX_VALID1, ctx_validation);
1720 
1721     /* Enable validation for connection region 1: TCFC_CTX_VALID0[15:8] */
1722     ctx_validation = CDU_VALIDATION_DEFAULT_CFG << 8;
1723     qed_wr(p_hwfn, p_ptt, CDU_REG_TCFC_CTX_VALID0, ctx_validation);
1724 }
1725 
1726 const char *qed_get_protocol_type_str(u32 protocol_type)
1727 {
1728     if (protocol_type >= ARRAY_SIZE(s_protocol_types))
1729         return "Invalid protocol type";
1730 
1731     return s_protocol_types[protocol_type];
1732 }
1733 
1734 const char *qed_get_ramrod_cmd_id_str(u32 protocol_type, u32 ramrod_cmd_id)
1735 {
1736     const char *ramrod_cmd_id_str;
1737 
1738     if (protocol_type >= ARRAY_SIZE(s_ramrod_cmd_ids))
1739         return "Invalid protocol type";
1740 
1741     if (ramrod_cmd_id >= ARRAY_SIZE(s_ramrod_cmd_ids[0]))
1742         return "Invalid Ramrod command ID";
1743 
1744     ramrod_cmd_id_str = s_ramrod_cmd_ids[protocol_type][ramrod_cmd_id];
1745 
1746     if (!ramrod_cmd_id_str)
1747         return "Invalid Ramrod command ID";
1748 
1749     return ramrod_cmd_id_str;
1750 }
1751 
1752 static u32 qed_get_rdma_assert_ram_addr(struct qed_hwfn *p_hwfn, u8 storm_id)
1753 {
1754     switch (storm_id) {
1755     case 0:
1756         return TSEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM +
1757             TSTORM_RDMA_ASSERT_LEVEL_OFFSET(p_hwfn->rel_pf_id);
1758     case 1:
1759         return MSEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM +
1760             MSTORM_RDMA_ASSERT_LEVEL_OFFSET(p_hwfn->rel_pf_id);
1761     case 2:
1762         return USEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM +
1763             USTORM_RDMA_ASSERT_LEVEL_OFFSET(p_hwfn->rel_pf_id);
1764     case 3:
1765         return XSEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM +
1766             XSTORM_RDMA_ASSERT_LEVEL_OFFSET(p_hwfn->rel_pf_id);
1767     case 4:
1768         return YSEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM +
1769             YSTORM_RDMA_ASSERT_LEVEL_OFFSET(p_hwfn->rel_pf_id);
1770     case 5:
1771         return PSEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM +
1772             PSTORM_RDMA_ASSERT_LEVEL_OFFSET(p_hwfn->rel_pf_id);
1773 
1774     default:
1775         return 0;
1776     }
1777 }
1778 
1779 void qed_set_rdma_error_level(struct qed_hwfn *p_hwfn,
1780                   struct qed_ptt *p_ptt,
1781                   u8 assert_level[NUM_STORMS])
1782 {
1783     u8 storm_id;
1784 
1785     for (storm_id = 0; storm_id < NUM_STORMS; storm_id++) {
1786         u32 ram_addr = qed_get_rdma_assert_ram_addr(p_hwfn, storm_id);
1787 
1788         qed_wr(p_hwfn, p_ptt, ram_addr, assert_level[storm_id]);
1789     }
1790 }
1791 
1792 #define PHYS_ADDR_DWORDS        DIV_ROUND_UP(sizeof(dma_addr_t), 4)
1793 #define OVERLAY_HDR_SIZE_DWORDS (sizeof(struct fw_overlay_buf_hdr) / 4)
1794 
1795 static u32 qed_get_overlay_addr_ram_addr(struct qed_hwfn *p_hwfn, u8 storm_id)
1796 {
1797     switch (storm_id) {
1798     case 0:
1799         return TSEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM +
1800             TSTORM_OVERLAY_BUF_ADDR_OFFSET;
1801     case 1:
1802         return MSEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM +
1803             MSTORM_OVERLAY_BUF_ADDR_OFFSET;
1804     case 2:
1805         return USEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM +
1806             USTORM_OVERLAY_BUF_ADDR_OFFSET;
1807     case 3:
1808         return XSEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM +
1809             XSTORM_OVERLAY_BUF_ADDR_OFFSET;
1810     case 4:
1811         return YSEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM +
1812             YSTORM_OVERLAY_BUF_ADDR_OFFSET;
1813     case 5:
1814         return PSEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM +
1815             PSTORM_OVERLAY_BUF_ADDR_OFFSET;
1816 
1817     default:
1818         return 0;
1819     }
1820 }
1821 
1822 struct phys_mem_desc *qed_fw_overlay_mem_alloc(struct qed_hwfn *p_hwfn,
1823                            const u32 * const
1824                            fw_overlay_in_buf,
1825                            u32 buf_size_in_bytes)
1826 {
1827     u32 buf_size = buf_size_in_bytes / sizeof(u32), buf_offset = 0;
1828     struct phys_mem_desc *allocated_mem;
1829 
1830     if (!buf_size)
1831         return NULL;
1832 
1833     allocated_mem = kcalloc(NUM_STORMS, sizeof(struct phys_mem_desc),
1834                 GFP_KERNEL);
1835     if (!allocated_mem)
1836         return NULL;
1837 
1838     /* For each Storm, set physical address in RAM */
1839     while (buf_offset < buf_size) {
1840         struct phys_mem_desc *storm_mem_desc;
1841         struct fw_overlay_buf_hdr *hdr;
1842         u32 storm_buf_size;
1843         u8 storm_id;
1844 
1845         hdr =
1846             (struct fw_overlay_buf_hdr *)&fw_overlay_in_buf[buf_offset];
1847         storm_buf_size = GET_FIELD(hdr->data,
1848                        FW_OVERLAY_BUF_HDR_BUF_SIZE);
1849         storm_id = GET_FIELD(hdr->data, FW_OVERLAY_BUF_HDR_STORM_ID);
1850         if (storm_id >= NUM_STORMS)
1851             break;
1852         storm_mem_desc = allocated_mem + storm_id;
1853         storm_mem_desc->size = storm_buf_size * sizeof(u32);
1854 
1855         /* Allocate physical memory for Storm's overlays buffer */
1856         storm_mem_desc->virt_addr =
1857             dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
1858                        storm_mem_desc->size,
1859                        &storm_mem_desc->phys_addr, GFP_KERNEL);
1860         if (!storm_mem_desc->virt_addr)
1861             break;
1862 
1863         /* Skip overlays buffer header */
1864         buf_offset += OVERLAY_HDR_SIZE_DWORDS;
1865 
1866         /* Copy Storm's overlays buffer to allocated memory */
1867         memcpy(storm_mem_desc->virt_addr,
1868                &fw_overlay_in_buf[buf_offset], storm_mem_desc->size);
1869 
1870         /* Advance to next Storm */
1871         buf_offset += storm_buf_size;
1872     }
1873 
1874     /* If memory allocation has failed, free all allocated memory */
1875     if (buf_offset < buf_size) {
1876         qed_fw_overlay_mem_free(p_hwfn, &allocated_mem);
1877         return NULL;
1878     }
1879 
1880     return allocated_mem;
1881 }
1882 
1883 void qed_fw_overlay_init_ram(struct qed_hwfn *p_hwfn,
1884                  struct qed_ptt *p_ptt,
1885                  struct phys_mem_desc *fw_overlay_mem)
1886 {
1887     u8 storm_id;
1888 
1889     for (storm_id = 0; storm_id < NUM_STORMS; storm_id++) {
1890         struct phys_mem_desc *storm_mem_desc =
1891             (struct phys_mem_desc *)fw_overlay_mem + storm_id;
1892         u32 ram_addr, i;
1893 
1894         /* Skip Storms with no FW overlays */
1895         if (!storm_mem_desc->virt_addr)
1896             continue;
1897 
1898         /* Calculate overlay RAM GRC address of current PF */
1899         ram_addr = qed_get_overlay_addr_ram_addr(p_hwfn, storm_id) +
1900                sizeof(dma_addr_t) * p_hwfn->rel_pf_id;
1901 
1902         /* Write Storm's overlay physical address to RAM */
1903         for (i = 0; i < PHYS_ADDR_DWORDS; i++, ram_addr += sizeof(u32))
1904             qed_wr(p_hwfn, p_ptt, ram_addr,
1905                    ((u32 *)&storm_mem_desc->phys_addr)[i]);
1906     }
1907 }
1908 
1909 void qed_fw_overlay_mem_free(struct qed_hwfn *p_hwfn,
1910                  struct phys_mem_desc **fw_overlay_mem)
1911 {
1912     u8 storm_id;
1913 
1914     if (!fw_overlay_mem || !(*fw_overlay_mem))
1915         return;
1916 
1917     for (storm_id = 0; storm_id < NUM_STORMS; storm_id++) {
1918         struct phys_mem_desc *storm_mem_desc =
1919             (struct phys_mem_desc *)*fw_overlay_mem + storm_id;
1920 
1921         /* Free Storm's physical memory */
1922         if (storm_mem_desc->virt_addr)
1923             dma_free_coherent(&p_hwfn->cdev->pdev->dev,
1924                       storm_mem_desc->size,
1925                       storm_mem_desc->virt_addr,
1926                       storm_mem_desc->phys_addr);
1927     }
1928 
1929     /* Free allocated virtual memory */
1930     kfree(*fw_overlay_mem);
1931     *fw_overlay_mem = NULL;
1932 }
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