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0001 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
0002 /* QLogic qed NIC Driver
0003  * Copyright (c) 2015-2017  QLogic Corporation
0004  * Copyright (c) 2019-2020 Marvell International Ltd.
0005  */
0006 
0007 #include <linux/types.h>
0008 #include <linux/io.h>
0009 #include <linux/delay.h>
0010 #include <linux/dma-mapping.h>
0011 #include <linux/errno.h>
0012 #include <linux/kernel.h>
0013 #include <linux/list.h>
0014 #include <linux/mutex.h>
0015 #include <linux/pci.h>
0016 #include <linux/slab.h>
0017 #include <linux/spinlock.h>
0018 #include <linux/string.h>
0019 #include <linux/qed/qed_chain.h>
0020 #include "qed.h"
0021 #include "qed_hsi.h"
0022 #include "qed_hw.h"
0023 #include "qed_reg_addr.h"
0024 #include "qed_sriov.h"
0025 
0026 #define QED_BAR_ACQUIRE_TIMEOUT 1000
0027 
0028 /* Invalid values */
0029 #define QED_BAR_INVALID_OFFSET          (cpu_to_le32(-1))
0030 
0031 struct qed_ptt {
0032     struct list_head    list_entry;
0033     unsigned int        idx;
0034     struct pxp_ptt_entry    pxp;
0035     u8          hwfn_id;
0036 };
0037 
0038 struct qed_ptt_pool {
0039     struct list_head    free_list;
0040     spinlock_t      lock; /* ptt synchronized access */
0041     struct qed_ptt      ptts[PXP_EXTERNAL_BAR_PF_WINDOW_NUM];
0042 };
0043 
0044 int qed_ptt_pool_alloc(struct qed_hwfn *p_hwfn)
0045 {
0046     struct qed_ptt_pool *p_pool = kmalloc(sizeof(*p_pool), GFP_KERNEL);
0047     int i;
0048 
0049     if (!p_pool)
0050         return -ENOMEM;
0051 
0052     INIT_LIST_HEAD(&p_pool->free_list);
0053     for (i = 0; i < PXP_EXTERNAL_BAR_PF_WINDOW_NUM; i++) {
0054         p_pool->ptts[i].idx = i;
0055         p_pool->ptts[i].pxp.offset = QED_BAR_INVALID_OFFSET;
0056         p_pool->ptts[i].pxp.pretend.control = 0;
0057         p_pool->ptts[i].hwfn_id = p_hwfn->my_id;
0058         if (i >= RESERVED_PTT_MAX)
0059             list_add(&p_pool->ptts[i].list_entry,
0060                  &p_pool->free_list);
0061     }
0062 
0063     p_hwfn->p_ptt_pool = p_pool;
0064     spin_lock_init(&p_pool->lock);
0065 
0066     return 0;
0067 }
0068 
0069 void qed_ptt_invalidate(struct qed_hwfn *p_hwfn)
0070 {
0071     struct qed_ptt *p_ptt;
0072     int i;
0073 
0074     for (i = 0; i < PXP_EXTERNAL_BAR_PF_WINDOW_NUM; i++) {
0075         p_ptt = &p_hwfn->p_ptt_pool->ptts[i];
0076         p_ptt->pxp.offset = QED_BAR_INVALID_OFFSET;
0077     }
0078 }
0079 
0080 void qed_ptt_pool_free(struct qed_hwfn *p_hwfn)
0081 {
0082     kfree(p_hwfn->p_ptt_pool);
0083     p_hwfn->p_ptt_pool = NULL;
0084 }
0085 
0086 struct qed_ptt *qed_ptt_acquire(struct qed_hwfn *p_hwfn)
0087 {
0088     struct qed_ptt *p_ptt;
0089     unsigned int i;
0090 
0091     /* Take the free PTT from the list */
0092     for (i = 0; i < QED_BAR_ACQUIRE_TIMEOUT; i++) {
0093         spin_lock_bh(&p_hwfn->p_ptt_pool->lock);
0094 
0095         if (!list_empty(&p_hwfn->p_ptt_pool->free_list)) {
0096             p_ptt = list_first_entry(&p_hwfn->p_ptt_pool->free_list,
0097                          struct qed_ptt, list_entry);
0098             list_del(&p_ptt->list_entry);
0099 
0100             spin_unlock_bh(&p_hwfn->p_ptt_pool->lock);
0101 
0102             DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
0103                    "allocated ptt %d\n", p_ptt->idx);
0104             return p_ptt;
0105         }
0106 
0107         spin_unlock_bh(&p_hwfn->p_ptt_pool->lock);
0108         usleep_range(1000, 2000);
0109     }
0110 
0111     DP_NOTICE(p_hwfn, "PTT acquire timeout - failed to allocate PTT\n");
0112     return NULL;
0113 }
0114 
0115 void qed_ptt_release(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
0116 {
0117     spin_lock_bh(&p_hwfn->p_ptt_pool->lock);
0118     list_add(&p_ptt->list_entry, &p_hwfn->p_ptt_pool->free_list);
0119     spin_unlock_bh(&p_hwfn->p_ptt_pool->lock);
0120 }
0121 
0122 u32 qed_ptt_get_hw_addr(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
0123 {
0124     /* The HW is using DWORDS and we need to translate it to Bytes */
0125     return le32_to_cpu(p_ptt->pxp.offset) << 2;
0126 }
0127 
0128 static u32 qed_ptt_config_addr(struct qed_ptt *p_ptt)
0129 {
0130     return PXP_PF_WINDOW_ADMIN_PER_PF_START +
0131            p_ptt->idx * sizeof(struct pxp_ptt_entry);
0132 }
0133 
0134 u32 qed_ptt_get_bar_addr(struct qed_ptt *p_ptt)
0135 {
0136     return PXP_EXTERNAL_BAR_PF_WINDOW_START +
0137            p_ptt->idx * PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE;
0138 }
0139 
0140 void qed_ptt_set_win(struct qed_hwfn *p_hwfn,
0141              struct qed_ptt *p_ptt, u32 new_hw_addr)
0142 {
0143     u32 prev_hw_addr;
0144 
0145     prev_hw_addr = qed_ptt_get_hw_addr(p_hwfn, p_ptt);
0146 
0147     if (new_hw_addr == prev_hw_addr)
0148         return;
0149 
0150     /* Update PTT entery in admin window */
0151     DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
0152            "Updating PTT entry %d to offset 0x%x\n",
0153            p_ptt->idx, new_hw_addr);
0154 
0155     /* The HW is using DWORDS and the address is in Bytes */
0156     p_ptt->pxp.offset = cpu_to_le32(new_hw_addr >> 2);
0157 
0158     REG_WR(p_hwfn,
0159            qed_ptt_config_addr(p_ptt) +
0160            offsetof(struct pxp_ptt_entry, offset),
0161            le32_to_cpu(p_ptt->pxp.offset));
0162 }
0163 
0164 static u32 qed_set_ptt(struct qed_hwfn *p_hwfn,
0165                struct qed_ptt *p_ptt, u32 hw_addr)
0166 {
0167     u32 win_hw_addr = qed_ptt_get_hw_addr(p_hwfn, p_ptt);
0168     u32 offset;
0169 
0170     offset = hw_addr - win_hw_addr;
0171 
0172     if (p_ptt->hwfn_id != p_hwfn->my_id)
0173         DP_NOTICE(p_hwfn,
0174               "ptt[%d] of hwfn[%02x] is used by hwfn[%02x]!\n",
0175               p_ptt->idx, p_ptt->hwfn_id, p_hwfn->my_id);
0176 
0177     /* Verify the address is within the window */
0178     if (hw_addr < win_hw_addr ||
0179         offset >= PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE) {
0180         qed_ptt_set_win(p_hwfn, p_ptt, hw_addr);
0181         offset = 0;
0182     }
0183 
0184     return qed_ptt_get_bar_addr(p_ptt) + offset;
0185 }
0186 
0187 struct qed_ptt *qed_get_reserved_ptt(struct qed_hwfn *p_hwfn,
0188                      enum reserved_ptts ptt_idx)
0189 {
0190     if (ptt_idx >= RESERVED_PTT_MAX) {
0191         DP_NOTICE(p_hwfn,
0192               "Requested PTT %d is out of range\n", ptt_idx);
0193         return NULL;
0194     }
0195 
0196     return &p_hwfn->p_ptt_pool->ptts[ptt_idx];
0197 }
0198 
0199 void qed_wr(struct qed_hwfn *p_hwfn,
0200         struct qed_ptt *p_ptt,
0201         u32 hw_addr, u32 val)
0202 {
0203     u32 bar_addr = qed_set_ptt(p_hwfn, p_ptt, hw_addr);
0204 
0205     REG_WR(p_hwfn, bar_addr, val);
0206     DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
0207            "bar_addr 0x%x, hw_addr 0x%x, val 0x%x\n",
0208            bar_addr, hw_addr, val);
0209 }
0210 
0211 u32 qed_rd(struct qed_hwfn *p_hwfn,
0212        struct qed_ptt *p_ptt,
0213        u32 hw_addr)
0214 {
0215     u32 bar_addr = qed_set_ptt(p_hwfn, p_ptt, hw_addr);
0216     u32 val = REG_RD(p_hwfn, bar_addr);
0217 
0218     DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
0219            "bar_addr 0x%x, hw_addr 0x%x, val 0x%x\n",
0220            bar_addr, hw_addr, val);
0221 
0222     return val;
0223 }
0224 
0225 static void qed_memcpy_hw(struct qed_hwfn *p_hwfn,
0226               struct qed_ptt *p_ptt,
0227               void *addr, u32 hw_addr, size_t n, bool to_device)
0228 {
0229     u32 dw_count, *host_addr, hw_offset;
0230     size_t quota, done = 0;
0231     u32 __iomem *reg_addr;
0232 
0233     while (done < n) {
0234         quota = min_t(size_t, n - done,
0235                   PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE);
0236 
0237         if (IS_PF(p_hwfn->cdev)) {
0238             qed_ptt_set_win(p_hwfn, p_ptt, hw_addr + done);
0239             hw_offset = qed_ptt_get_bar_addr(p_ptt);
0240         } else {
0241             hw_offset = hw_addr + done;
0242         }
0243 
0244         dw_count = quota / 4;
0245         host_addr = (u32 *)((u8 *)addr + done);
0246         reg_addr = (u32 __iomem *)REG_ADDR(p_hwfn, hw_offset);
0247         if (to_device)
0248             while (dw_count--)
0249                 DIRECT_REG_WR(reg_addr++, *host_addr++);
0250         else
0251             while (dw_count--)
0252                 *host_addr++ = DIRECT_REG_RD(reg_addr++);
0253 
0254         done += quota;
0255     }
0256 }
0257 
0258 void qed_memcpy_from(struct qed_hwfn *p_hwfn,
0259              struct qed_ptt *p_ptt, void *dest, u32 hw_addr, size_t n)
0260 {
0261     DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
0262            "hw_addr 0x%x, dest %p hw_addr 0x%x, size %lu\n",
0263            hw_addr, dest, hw_addr, (unsigned long)n);
0264 
0265     qed_memcpy_hw(p_hwfn, p_ptt, dest, hw_addr, n, false);
0266 }
0267 
0268 void qed_memcpy_to(struct qed_hwfn *p_hwfn,
0269            struct qed_ptt *p_ptt, u32 hw_addr, void *src, size_t n)
0270 {
0271     DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
0272            "hw_addr 0x%x, hw_addr 0x%x, src %p size %lu\n",
0273            hw_addr, hw_addr, src, (unsigned long)n);
0274 
0275     qed_memcpy_hw(p_hwfn, p_ptt, src, hw_addr, n, true);
0276 }
0277 
0278 void qed_fid_pretend(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, u16 fid)
0279 {
0280     u16 control = 0;
0281 
0282     SET_FIELD(control, PXP_PRETEND_CMD_IS_CONCRETE, 1);
0283     SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_FUNCTION, 1);
0284 
0285     /* Every pretend undos previous pretends, including
0286      * previous port pretend.
0287      */
0288     SET_FIELD(control, PXP_PRETEND_CMD_PORT, 0);
0289     SET_FIELD(control, PXP_PRETEND_CMD_USE_PORT, 0);
0290     SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_PORT, 1);
0291 
0292     if (!GET_FIELD(fid, PXP_CONCRETE_FID_VFVALID))
0293         fid = GET_FIELD(fid, PXP_CONCRETE_FID_PFID);
0294 
0295     p_ptt->pxp.pretend.control = cpu_to_le16(control);
0296     p_ptt->pxp.pretend.fid.concrete_fid.fid = cpu_to_le16(fid);
0297 
0298     REG_WR(p_hwfn,
0299            qed_ptt_config_addr(p_ptt) +
0300            offsetof(struct pxp_ptt_entry, pretend),
0301            *(u32 *)&p_ptt->pxp.pretend);
0302 }
0303 
0304 void qed_port_pretend(struct qed_hwfn *p_hwfn,
0305               struct qed_ptt *p_ptt, u8 port_id)
0306 {
0307     u16 control = 0;
0308 
0309     SET_FIELD(control, PXP_PRETEND_CMD_PORT, port_id);
0310     SET_FIELD(control, PXP_PRETEND_CMD_USE_PORT, 1);
0311     SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_PORT, 1);
0312 
0313     p_ptt->pxp.pretend.control = cpu_to_le16(control);
0314 
0315     REG_WR(p_hwfn,
0316            qed_ptt_config_addr(p_ptt) +
0317            offsetof(struct pxp_ptt_entry, pretend),
0318            *(u32 *)&p_ptt->pxp.pretend);
0319 }
0320 
0321 void qed_port_unpretend(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
0322 {
0323     u16 control = 0;
0324 
0325     SET_FIELD(control, PXP_PRETEND_CMD_PORT, 0);
0326     SET_FIELD(control, PXP_PRETEND_CMD_USE_PORT, 0);
0327     SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_PORT, 1);
0328 
0329     p_ptt->pxp.pretend.control = cpu_to_le16(control);
0330 
0331     REG_WR(p_hwfn,
0332            qed_ptt_config_addr(p_ptt) +
0333            offsetof(struct pxp_ptt_entry, pretend),
0334            *(u32 *)&p_ptt->pxp.pretend);
0335 }
0336 
0337 void qed_port_fid_pretend(struct qed_hwfn *p_hwfn,
0338               struct qed_ptt *p_ptt, u8 port_id, u16 fid)
0339 {
0340     u16 control = 0;
0341 
0342     SET_FIELD(control, PXP_PRETEND_CMD_PORT, port_id);
0343     SET_FIELD(control, PXP_PRETEND_CMD_USE_PORT, 1);
0344     SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_PORT, 1);
0345     SET_FIELD(control, PXP_PRETEND_CMD_IS_CONCRETE, 1);
0346     SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_FUNCTION, 1);
0347     if (!GET_FIELD(fid, PXP_CONCRETE_FID_VFVALID))
0348         fid = GET_FIELD(fid, PXP_CONCRETE_FID_PFID);
0349     p_ptt->pxp.pretend.control = cpu_to_le16(control);
0350     p_ptt->pxp.pretend.fid.concrete_fid.fid = cpu_to_le16(fid);
0351     REG_WR(p_hwfn,
0352            qed_ptt_config_addr(p_ptt) +
0353            offsetof(struct pxp_ptt_entry, pretend),
0354            *(u32 *)&p_ptt->pxp.pretend);
0355 }
0356 
0357 u32 qed_vfid_to_concrete(struct qed_hwfn *p_hwfn, u8 vfid)
0358 {
0359     u32 concrete_fid = 0;
0360 
0361     SET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID, p_hwfn->rel_pf_id);
0362     SET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID, vfid);
0363     SET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFVALID, 1);
0364 
0365     return concrete_fid;
0366 }
0367 
0368 /* DMAE */
0369 #define QED_DMAE_FLAGS_IS_SET(params, flag) \
0370     ((params) != NULL && GET_FIELD((params)->flags, QED_DMAE_PARAMS_##flag))
0371 
0372 static void qed_dmae_opcode(struct qed_hwfn *p_hwfn,
0373                 const u8 is_src_type_grc,
0374                 const u8 is_dst_type_grc,
0375                 struct qed_dmae_params *p_params)
0376 {
0377     u8 src_pfid, dst_pfid, port_id;
0378     u16 opcode_b = 0;
0379     u32 opcode = 0;
0380 
0381     /* Whether the source is the PCIe or the GRC.
0382      * 0- The source is the PCIe
0383      * 1- The source is the GRC.
0384      */
0385     SET_FIELD(opcode, DMAE_CMD_SRC,
0386           (is_src_type_grc ? dmae_cmd_src_grc : dmae_cmd_src_pcie));
0387     src_pfid = QED_DMAE_FLAGS_IS_SET(p_params, SRC_PF_VALID) ?
0388         p_params->src_pfid : p_hwfn->rel_pf_id;
0389     SET_FIELD(opcode, DMAE_CMD_SRC_PF_ID, src_pfid);
0390 
0391     /* The destination of the DMA can be: 0-None 1-PCIe 2-GRC 3-None */
0392     SET_FIELD(opcode, DMAE_CMD_DST,
0393           (is_dst_type_grc ? dmae_cmd_dst_grc : dmae_cmd_dst_pcie));
0394     dst_pfid = QED_DMAE_FLAGS_IS_SET(p_params, DST_PF_VALID) ?
0395         p_params->dst_pfid : p_hwfn->rel_pf_id;
0396     SET_FIELD(opcode, DMAE_CMD_DST_PF_ID, dst_pfid);
0397 
0398 
0399     /* Whether to write a completion word to the completion destination:
0400      * 0-Do not write a completion word
0401      * 1-Write the completion word
0402      */
0403     SET_FIELD(opcode, DMAE_CMD_COMP_WORD_EN, 1);
0404     SET_FIELD(opcode, DMAE_CMD_SRC_ADDR_RESET, 1);
0405 
0406     if (QED_DMAE_FLAGS_IS_SET(p_params, COMPLETION_DST))
0407         SET_FIELD(opcode, DMAE_CMD_COMP_FUNC, 1);
0408 
0409     /* swapping mode 3 - big endian */
0410     SET_FIELD(opcode, DMAE_CMD_ENDIANITY_MODE, DMAE_CMD_ENDIANITY);
0411 
0412     port_id = (QED_DMAE_FLAGS_IS_SET(p_params, PORT_VALID)) ?
0413         p_params->port_id : p_hwfn->port_id;
0414     SET_FIELD(opcode, DMAE_CMD_PORT_ID, port_id);
0415 
0416     /* reset source address in next go */
0417     SET_FIELD(opcode, DMAE_CMD_SRC_ADDR_RESET, 1);
0418 
0419     /* reset dest address in next go */
0420     SET_FIELD(opcode, DMAE_CMD_DST_ADDR_RESET, 1);
0421 
0422     /* SRC/DST VFID: all 1's - pf, otherwise VF id */
0423     if (QED_DMAE_FLAGS_IS_SET(p_params, SRC_VF_VALID)) {
0424         SET_FIELD(opcode, DMAE_CMD_SRC_VF_ID_VALID, 1);
0425         SET_FIELD(opcode_b, DMAE_CMD_SRC_VF_ID, p_params->src_vfid);
0426     } else {
0427         SET_FIELD(opcode_b, DMAE_CMD_SRC_VF_ID, 0xFF);
0428     }
0429     if (QED_DMAE_FLAGS_IS_SET(p_params, DST_VF_VALID)) {
0430         SET_FIELD(opcode, DMAE_CMD_DST_VF_ID_VALID, 1);
0431         SET_FIELD(opcode_b, DMAE_CMD_DST_VF_ID, p_params->dst_vfid);
0432     } else {
0433         SET_FIELD(opcode_b, DMAE_CMD_DST_VF_ID, 0xFF);
0434     }
0435 
0436     p_hwfn->dmae_info.p_dmae_cmd->opcode = cpu_to_le32(opcode);
0437     p_hwfn->dmae_info.p_dmae_cmd->opcode_b = cpu_to_le16(opcode_b);
0438 }
0439 
0440 u32 qed_dmae_idx_to_go_cmd(u8 idx)
0441 {
0442     /* All the DMAE 'go' registers form an array in internal memory */
0443     return DMAE_REG_GO_C0 + (idx << 2);
0444 }
0445 
0446 static int qed_dmae_post_command(struct qed_hwfn *p_hwfn,
0447                  struct qed_ptt *p_ptt)
0448 {
0449     struct dmae_cmd *p_command = p_hwfn->dmae_info.p_dmae_cmd;
0450     u8 idx_cmd = p_hwfn->dmae_info.channel, i;
0451     int qed_status = 0;
0452 
0453     /* verify address is not NULL */
0454     if ((((!p_command->dst_addr_lo) && (!p_command->dst_addr_hi)) ||
0455          ((!p_command->src_addr_lo) && (!p_command->src_addr_hi)))) {
0456         DP_NOTICE(p_hwfn,
0457               "source or destination address 0 idx_cmd=%d\n"
0458               "opcode = [0x%08x,0x%04x] len=0x%x src=0x%x:%x dst=0x%x:%x\n",
0459               idx_cmd,
0460               le32_to_cpu(p_command->opcode),
0461               le16_to_cpu(p_command->opcode_b),
0462               le16_to_cpu(p_command->length_dw),
0463               le32_to_cpu(p_command->src_addr_hi),
0464               le32_to_cpu(p_command->src_addr_lo),
0465               le32_to_cpu(p_command->dst_addr_hi),
0466               le32_to_cpu(p_command->dst_addr_lo));
0467 
0468         return -EINVAL;
0469     }
0470 
0471     DP_VERBOSE(p_hwfn,
0472            NETIF_MSG_HW,
0473            "Posting DMAE command [idx %d]: opcode = [0x%08x,0x%04x] len=0x%x src=0x%x:%x dst=0x%x:%x\n",
0474            idx_cmd,
0475            le32_to_cpu(p_command->opcode),
0476            le16_to_cpu(p_command->opcode_b),
0477            le16_to_cpu(p_command->length_dw),
0478            le32_to_cpu(p_command->src_addr_hi),
0479            le32_to_cpu(p_command->src_addr_lo),
0480            le32_to_cpu(p_command->dst_addr_hi),
0481            le32_to_cpu(p_command->dst_addr_lo));
0482 
0483     /* Copy the command to DMAE - need to do it before every call
0484      * for source/dest address no reset.
0485      * The first 9 DWs are the command registers, the 10 DW is the
0486      * GO register, and the rest are result registers
0487      * (which are read only by the client).
0488      */
0489     for (i = 0; i < DMAE_CMD_SIZE; i++) {
0490         u32 data = (i < DMAE_CMD_SIZE_TO_FILL) ?
0491                *(((u32 *)p_command) + i) : 0;
0492 
0493         qed_wr(p_hwfn, p_ptt,
0494                DMAE_REG_CMD_MEM +
0495                (idx_cmd * DMAE_CMD_SIZE * sizeof(u32)) +
0496                (i * sizeof(u32)), data);
0497     }
0498 
0499     qed_wr(p_hwfn, p_ptt, qed_dmae_idx_to_go_cmd(idx_cmd), DMAE_GO_VALUE);
0500 
0501     return qed_status;
0502 }
0503 
0504 int qed_dmae_info_alloc(struct qed_hwfn *p_hwfn)
0505 {
0506     dma_addr_t *p_addr = &p_hwfn->dmae_info.completion_word_phys_addr;
0507     struct dmae_cmd **p_cmd = &p_hwfn->dmae_info.p_dmae_cmd;
0508     u32 **p_buff = &p_hwfn->dmae_info.p_intermediate_buffer;
0509     u32 **p_comp = &p_hwfn->dmae_info.p_completion_word;
0510 
0511     *p_comp = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
0512                      sizeof(u32), p_addr, GFP_KERNEL);
0513     if (!*p_comp)
0514         goto err;
0515 
0516     p_addr = &p_hwfn->dmae_info.dmae_cmd_phys_addr;
0517     *p_cmd = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
0518                     sizeof(struct dmae_cmd),
0519                     p_addr, GFP_KERNEL);
0520     if (!*p_cmd)
0521         goto err;
0522 
0523     p_addr = &p_hwfn->dmae_info.intermediate_buffer_phys_addr;
0524     *p_buff = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
0525                      sizeof(u32) * DMAE_MAX_RW_SIZE,
0526                      p_addr, GFP_KERNEL);
0527     if (!*p_buff)
0528         goto err;
0529 
0530     p_hwfn->dmae_info.channel = p_hwfn->rel_pf_id;
0531 
0532     return 0;
0533 err:
0534     qed_dmae_info_free(p_hwfn);
0535     return -ENOMEM;
0536 }
0537 
0538 void qed_dmae_info_free(struct qed_hwfn *p_hwfn)
0539 {
0540     dma_addr_t p_phys;
0541 
0542     /* Just make sure no one is in the middle */
0543     mutex_lock(&p_hwfn->dmae_info.mutex);
0544 
0545     if (p_hwfn->dmae_info.p_completion_word) {
0546         p_phys = p_hwfn->dmae_info.completion_word_phys_addr;
0547         dma_free_coherent(&p_hwfn->cdev->pdev->dev,
0548                   sizeof(u32),
0549                   p_hwfn->dmae_info.p_completion_word, p_phys);
0550         p_hwfn->dmae_info.p_completion_word = NULL;
0551     }
0552 
0553     if (p_hwfn->dmae_info.p_dmae_cmd) {
0554         p_phys = p_hwfn->dmae_info.dmae_cmd_phys_addr;
0555         dma_free_coherent(&p_hwfn->cdev->pdev->dev,
0556                   sizeof(struct dmae_cmd),
0557                   p_hwfn->dmae_info.p_dmae_cmd, p_phys);
0558         p_hwfn->dmae_info.p_dmae_cmd = NULL;
0559     }
0560 
0561     if (p_hwfn->dmae_info.p_intermediate_buffer) {
0562         p_phys = p_hwfn->dmae_info.intermediate_buffer_phys_addr;
0563         dma_free_coherent(&p_hwfn->cdev->pdev->dev,
0564                   sizeof(u32) * DMAE_MAX_RW_SIZE,
0565                   p_hwfn->dmae_info.p_intermediate_buffer,
0566                   p_phys);
0567         p_hwfn->dmae_info.p_intermediate_buffer = NULL;
0568     }
0569 
0570     mutex_unlock(&p_hwfn->dmae_info.mutex);
0571 }
0572 
0573 static int qed_dmae_operation_wait(struct qed_hwfn *p_hwfn)
0574 {
0575     u32 wait_cnt_limit = 10000, wait_cnt = 0;
0576     int qed_status = 0;
0577 
0578     barrier();
0579     while (*p_hwfn->dmae_info.p_completion_word != DMAE_COMPLETION_VAL) {
0580         udelay(DMAE_MIN_WAIT_TIME);
0581         if (++wait_cnt > wait_cnt_limit) {
0582             DP_NOTICE(p_hwfn->cdev,
0583                   "Timed-out waiting for operation to complete. Completion word is 0x%08x expected 0x%08x.\n",
0584                   *p_hwfn->dmae_info.p_completion_word,
0585                  DMAE_COMPLETION_VAL);
0586             qed_status = -EBUSY;
0587             break;
0588         }
0589 
0590         /* to sync the completion_word since we are not
0591          * using the volatile keyword for p_completion_word
0592          */
0593         barrier();
0594     }
0595 
0596     if (qed_status == 0)
0597         *p_hwfn->dmae_info.p_completion_word = 0;
0598 
0599     return qed_status;
0600 }
0601 
0602 static int qed_dmae_execute_sub_operation(struct qed_hwfn *p_hwfn,
0603                       struct qed_ptt *p_ptt,
0604                       u64 src_addr,
0605                       u64 dst_addr,
0606                       u8 src_type,
0607                       u8 dst_type,
0608                       u32 length_dw)
0609 {
0610     dma_addr_t phys = p_hwfn->dmae_info.intermediate_buffer_phys_addr;
0611     struct dmae_cmd *cmd = p_hwfn->dmae_info.p_dmae_cmd;
0612     int qed_status = 0;
0613 
0614     switch (src_type) {
0615     case QED_DMAE_ADDRESS_GRC:
0616     case QED_DMAE_ADDRESS_HOST_PHYS:
0617         cmd->src_addr_hi = cpu_to_le32(upper_32_bits(src_addr));
0618         cmd->src_addr_lo = cpu_to_le32(lower_32_bits(src_addr));
0619         break;
0620     /* for virtual source addresses we use the intermediate buffer. */
0621     case QED_DMAE_ADDRESS_HOST_VIRT:
0622         cmd->src_addr_hi = cpu_to_le32(upper_32_bits(phys));
0623         cmd->src_addr_lo = cpu_to_le32(lower_32_bits(phys));
0624         memcpy(&p_hwfn->dmae_info.p_intermediate_buffer[0],
0625                (void *)(uintptr_t)src_addr,
0626                length_dw * sizeof(u32));
0627         break;
0628     default:
0629         return -EINVAL;
0630     }
0631 
0632     switch (dst_type) {
0633     case QED_DMAE_ADDRESS_GRC:
0634     case QED_DMAE_ADDRESS_HOST_PHYS:
0635         cmd->dst_addr_hi = cpu_to_le32(upper_32_bits(dst_addr));
0636         cmd->dst_addr_lo = cpu_to_le32(lower_32_bits(dst_addr));
0637         break;
0638     /* for virtual source addresses we use the intermediate buffer. */
0639     case QED_DMAE_ADDRESS_HOST_VIRT:
0640         cmd->dst_addr_hi = cpu_to_le32(upper_32_bits(phys));
0641         cmd->dst_addr_lo = cpu_to_le32(lower_32_bits(phys));
0642         break;
0643     default:
0644         return -EINVAL;
0645     }
0646 
0647     cmd->length_dw = cpu_to_le16((u16)length_dw);
0648 
0649     qed_dmae_post_command(p_hwfn, p_ptt);
0650 
0651     qed_status = qed_dmae_operation_wait(p_hwfn);
0652 
0653     if (qed_status) {
0654         DP_NOTICE(p_hwfn,
0655               "qed_dmae_host2grc: Wait Failed. source_addr 0x%llx, grc_addr 0x%llx, size_in_dwords 0x%x\n",
0656               src_addr, dst_addr, length_dw);
0657         return qed_status;
0658     }
0659 
0660     if (dst_type == QED_DMAE_ADDRESS_HOST_VIRT)
0661         memcpy((void *)(uintptr_t)(dst_addr),
0662                &p_hwfn->dmae_info.p_intermediate_buffer[0],
0663                length_dw * sizeof(u32));
0664 
0665     return 0;
0666 }
0667 
0668 static int qed_dmae_execute_command(struct qed_hwfn *p_hwfn,
0669                     struct qed_ptt *p_ptt,
0670                     u64 src_addr, u64 dst_addr,
0671                     u8 src_type, u8 dst_type,
0672                     u32 size_in_dwords,
0673                     struct qed_dmae_params *p_params)
0674 {
0675     dma_addr_t phys = p_hwfn->dmae_info.completion_word_phys_addr;
0676     u16 length_cur = 0, i = 0, cnt_split = 0, length_mod = 0;
0677     struct dmae_cmd *cmd = p_hwfn->dmae_info.p_dmae_cmd;
0678     u64 src_addr_split = 0, dst_addr_split = 0;
0679     u16 length_limit = DMAE_MAX_RW_SIZE;
0680     int qed_status = 0;
0681     u32 offset = 0;
0682 
0683     if (p_hwfn->cdev->recov_in_prog) {
0684         DP_VERBOSE(p_hwfn,
0685                NETIF_MSG_HW,
0686                "Recovery is in progress. Avoid DMAE transaction [{src: addr 0x%llx, type %d}, {dst: addr 0x%llx, type %d}, size %d].\n",
0687                src_addr, src_type, dst_addr, dst_type,
0688                size_in_dwords);
0689 
0690         /* Let the flow complete w/o any error handling */
0691         return 0;
0692     }
0693 
0694     qed_dmae_opcode(p_hwfn,
0695             (src_type == QED_DMAE_ADDRESS_GRC),
0696             (dst_type == QED_DMAE_ADDRESS_GRC),
0697             p_params);
0698 
0699     cmd->comp_addr_lo = cpu_to_le32(lower_32_bits(phys));
0700     cmd->comp_addr_hi = cpu_to_le32(upper_32_bits(phys));
0701     cmd->comp_val = cpu_to_le32(DMAE_COMPLETION_VAL);
0702 
0703     /* Check if the grc_addr is valid like < MAX_GRC_OFFSET */
0704     cnt_split = size_in_dwords / length_limit;
0705     length_mod = size_in_dwords % length_limit;
0706 
0707     src_addr_split = src_addr;
0708     dst_addr_split = dst_addr;
0709 
0710     for (i = 0; i <= cnt_split; i++) {
0711         offset = length_limit * i;
0712 
0713         if (!QED_DMAE_FLAGS_IS_SET(p_params, RW_REPL_SRC)) {
0714             if (src_type == QED_DMAE_ADDRESS_GRC)
0715                 src_addr_split = src_addr + offset;
0716             else
0717                 src_addr_split = src_addr + (offset * 4);
0718         }
0719 
0720         if (dst_type == QED_DMAE_ADDRESS_GRC)
0721             dst_addr_split = dst_addr + offset;
0722         else
0723             dst_addr_split = dst_addr + (offset * 4);
0724 
0725         length_cur = (cnt_split == i) ? length_mod : length_limit;
0726 
0727         /* might be zero on last iteration */
0728         if (!length_cur)
0729             continue;
0730 
0731         qed_status = qed_dmae_execute_sub_operation(p_hwfn,
0732                                 p_ptt,
0733                                 src_addr_split,
0734                                 dst_addr_split,
0735                                 src_type,
0736                                 dst_type,
0737                                 length_cur);
0738         if (qed_status) {
0739             qed_hw_err_notify(p_hwfn, p_ptt, QED_HW_ERR_DMAE_FAIL,
0740                       "qed_dmae_execute_sub_operation Failed with error 0x%x. source_addr 0x%llx, destination addr 0x%llx, size_in_dwords 0x%x\n",
0741                       qed_status, src_addr,
0742                       dst_addr, length_cur);
0743             break;
0744         }
0745     }
0746 
0747     return qed_status;
0748 }
0749 
0750 int qed_dmae_host2grc(struct qed_hwfn *p_hwfn,
0751               struct qed_ptt *p_ptt,
0752               u64 source_addr, u32 grc_addr, u32 size_in_dwords,
0753               struct qed_dmae_params *p_params)
0754 {
0755     u32 grc_addr_in_dw = grc_addr / sizeof(u32);
0756     int rc;
0757 
0758 
0759     mutex_lock(&p_hwfn->dmae_info.mutex);
0760 
0761     rc = qed_dmae_execute_command(p_hwfn, p_ptt, source_addr,
0762                       grc_addr_in_dw,
0763                       QED_DMAE_ADDRESS_HOST_VIRT,
0764                       QED_DMAE_ADDRESS_GRC,
0765                       size_in_dwords, p_params);
0766 
0767     mutex_unlock(&p_hwfn->dmae_info.mutex);
0768 
0769     return rc;
0770 }
0771 
0772 int qed_dmae_grc2host(struct qed_hwfn *p_hwfn,
0773               struct qed_ptt *p_ptt,
0774               u32 grc_addr,
0775               dma_addr_t dest_addr, u32 size_in_dwords,
0776               struct qed_dmae_params *p_params)
0777 {
0778     u32 grc_addr_in_dw = grc_addr / sizeof(u32);
0779     int rc;
0780 
0781 
0782     mutex_lock(&p_hwfn->dmae_info.mutex);
0783 
0784     rc = qed_dmae_execute_command(p_hwfn, p_ptt, grc_addr_in_dw,
0785                       dest_addr, QED_DMAE_ADDRESS_GRC,
0786                       QED_DMAE_ADDRESS_HOST_VIRT,
0787                       size_in_dwords, p_params);
0788 
0789     mutex_unlock(&p_hwfn->dmae_info.mutex);
0790 
0791     return rc;
0792 }
0793 
0794 int qed_dmae_host2host(struct qed_hwfn *p_hwfn,
0795                struct qed_ptt *p_ptt,
0796                dma_addr_t source_addr,
0797                dma_addr_t dest_addr,
0798                u32 size_in_dwords, struct qed_dmae_params *p_params)
0799 {
0800     int rc;
0801 
0802     mutex_lock(&(p_hwfn->dmae_info.mutex));
0803 
0804     rc = qed_dmae_execute_command(p_hwfn, p_ptt, source_addr,
0805                       dest_addr,
0806                       QED_DMAE_ADDRESS_HOST_PHYS,
0807                       QED_DMAE_ADDRESS_HOST_PHYS,
0808                       size_in_dwords, p_params);
0809 
0810     mutex_unlock(&(p_hwfn->dmae_info.mutex));
0811 
0812     return rc;
0813 }
0814 
0815 void qed_hw_err_notify(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
0816                enum qed_hw_err_type err_type, const char *fmt, ...)
0817 {
0818     char buf[QED_HW_ERR_MAX_STR_SIZE];
0819     va_list vl;
0820     int len;
0821 
0822     if (fmt) {
0823         va_start(vl, fmt);
0824         len = vsnprintf(buf, QED_HW_ERR_MAX_STR_SIZE, fmt, vl);
0825         va_end(vl);
0826 
0827         if (len > QED_HW_ERR_MAX_STR_SIZE - 1)
0828             len = QED_HW_ERR_MAX_STR_SIZE - 1;
0829 
0830         DP_NOTICE(p_hwfn, "%s", buf);
0831     }
0832 
0833     /* Fan failure cannot be masked by handling of another HW error */
0834     if (p_hwfn->cdev->recov_in_prog &&
0835         err_type != QED_HW_ERR_FAN_FAIL) {
0836         DP_VERBOSE(p_hwfn,
0837                NETIF_MSG_DRV,
0838                "Recovery is in progress. Avoid notifying about HW error %d.\n",
0839                err_type);
0840         return;
0841     }
0842 
0843     qed_hw_error_occurred(p_hwfn, err_type);
0844 
0845     if (fmt)
0846         qed_mcp_send_raw_debug_data(p_hwfn, p_ptt, buf, len);
0847 }
0848 
0849 int qed_dmae_sanity(struct qed_hwfn *p_hwfn,
0850             struct qed_ptt *p_ptt, const char *phase)
0851 {
0852     u32 size = PAGE_SIZE / 2, val;
0853     int rc = 0;
0854     dma_addr_t p_phys;
0855     void *p_virt;
0856     u32 *p_tmp;
0857 
0858     p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
0859                     2 * size, &p_phys, GFP_KERNEL);
0860     if (!p_virt) {
0861         DP_NOTICE(p_hwfn,
0862               "DMAE sanity [%s]: failed to allocate memory\n",
0863               phase);
0864         return -ENOMEM;
0865     }
0866 
0867     /* Fill the bottom half of the allocated memory with a known pattern */
0868     for (p_tmp = (u32 *)p_virt;
0869          p_tmp < (u32 *)((u8 *)p_virt + size); p_tmp++) {
0870         /* Save the address itself as the value */
0871         val = (u32)(uintptr_t)p_tmp;
0872         *p_tmp = val;
0873     }
0874 
0875     /* Zero the top half of the allocated memory */
0876     memset((u8 *)p_virt + size, 0, size);
0877 
0878     DP_VERBOSE(p_hwfn,
0879            QED_MSG_SP,
0880            "DMAE sanity [%s]: src_addr={phys 0x%llx, virt %p}, dst_addr={phys 0x%llx, virt %p}, size 0x%x\n",
0881            phase,
0882            (u64)p_phys,
0883            p_virt, (u64)(p_phys + size), (u8 *)p_virt + size, size);
0884 
0885     rc = qed_dmae_host2host(p_hwfn, p_ptt, p_phys, p_phys + size,
0886                 size / 4, NULL);
0887     if (rc) {
0888         DP_NOTICE(p_hwfn,
0889               "DMAE sanity [%s]: qed_dmae_host2host() failed. rc = %d.\n",
0890               phase, rc);
0891         goto out;
0892     }
0893 
0894     /* Verify that the top half of the allocated memory has the pattern */
0895     for (p_tmp = (u32 *)((u8 *)p_virt + size);
0896          p_tmp < (u32 *)((u8 *)p_virt + (2 * size)); p_tmp++) {
0897         /* The corresponding address in the bottom half */
0898         val = (u32)(uintptr_t)p_tmp - size;
0899 
0900         if (*p_tmp != val) {
0901             DP_NOTICE(p_hwfn,
0902                   "DMAE sanity [%s]: addr={phys 0x%llx, virt %p}, read_val 0x%08x, expected_val 0x%08x\n",
0903                   phase,
0904                   (u64)p_phys + ((u8 *)p_tmp - (u8 *)p_virt),
0905                   p_tmp, *p_tmp, val);
0906             rc = -EINVAL;
0907             goto out;
0908         }
0909     }
0910 
0911 out:
0912     dma_free_coherent(&p_hwfn->cdev->pdev->dev, 2 * size, p_virt, p_phys);
0913     return rc;
0914 }
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