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0001 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 0002 /* QLogic qed NIC Driver 0003 * Copyright (c) 2015-2017 QLogic Corporation 0004 * Copyright (c) 2019-2020 Marvell International Ltd. 0005 */ 0006 0007 #ifndef _QED_DEV_API_H 0008 #define _QED_DEV_API_H 0009 0010 #include <linux/types.h> 0011 #include <linux/kernel.h> 0012 #include <linux/slab.h> 0013 #include <linux/qed/qed_chain.h> 0014 #include <linux/qed/qed_if.h> 0015 #include "qed_int.h" 0016 0017 /** 0018 * qed_init_dp(): Initialize the debug level. 0019 * 0020 * @cdev: Qed dev pointer. 0021 * @dp_module: Module debug parameter. 0022 * @dp_level: Module debug level. 0023 * 0024 * Return: Void. 0025 */ 0026 void qed_init_dp(struct qed_dev *cdev, 0027 u32 dp_module, 0028 u8 dp_level); 0029 0030 /** 0031 * qed_init_struct(): Initialize the device structure to 0032 * its defaults. 0033 * 0034 * @cdev: Qed dev pointer. 0035 * 0036 * Return: Void. 0037 */ 0038 void qed_init_struct(struct qed_dev *cdev); 0039 0040 /** 0041 * qed_resc_free: Free device resources. 0042 * 0043 * @cdev: Qed dev pointer. 0044 * 0045 * Return: Void. 0046 */ 0047 void qed_resc_free(struct qed_dev *cdev); 0048 0049 /** 0050 * qed_resc_alloc(): Alloc device resources. 0051 * 0052 * @cdev: Qed dev pointer. 0053 * 0054 * Return: Int. 0055 */ 0056 int qed_resc_alloc(struct qed_dev *cdev); 0057 0058 /** 0059 * qed_resc_setup(): Setup device resources. 0060 * 0061 * @cdev: Qed dev pointer. 0062 * 0063 * Return: Void. 0064 */ 0065 void qed_resc_setup(struct qed_dev *cdev); 0066 0067 enum qed_override_force_load { 0068 QED_OVERRIDE_FORCE_LOAD_NONE, 0069 QED_OVERRIDE_FORCE_LOAD_ALWAYS, 0070 QED_OVERRIDE_FORCE_LOAD_NEVER, 0071 }; 0072 0073 struct qed_drv_load_params { 0074 /* Indicates whether the driver is running over a crash kernel. 0075 * As part of the load request, this will be used for providing the 0076 * driver role to the MFW. 0077 * In case of a crash kernel over PDA - this should be set to false. 0078 */ 0079 bool is_crash_kernel; 0080 0081 /* The timeout value that the MFW should use when locking the engine for 0082 * the driver load process. 0083 * A value of '0' means the default value, and '255' means no timeout. 0084 */ 0085 u8 mfw_timeout_val; 0086 #define QED_LOAD_REQ_LOCK_TO_DEFAULT 0 0087 #define QED_LOAD_REQ_LOCK_TO_NONE 255 0088 0089 /* Avoid engine reset when first PF loads on it */ 0090 bool avoid_eng_reset; 0091 0092 /* Allow overriding the default force load behavior */ 0093 enum qed_override_force_load override_force_load; 0094 }; 0095 0096 struct qed_hw_init_params { 0097 /* Tunneling parameters */ 0098 struct qed_tunnel_info *p_tunn; 0099 0100 bool b_hw_start; 0101 0102 /* Interrupt mode [msix, inta, etc.] to use */ 0103 enum qed_int_mode int_mode; 0104 0105 /* NPAR tx switching to be used for vports for tx-switching */ 0106 bool allow_npar_tx_switch; 0107 0108 /* Binary fw data pointer in binary fw file */ 0109 const u8 *bin_fw_data; 0110 0111 /* Driver load parameters */ 0112 struct qed_drv_load_params *p_drv_load_params; 0113 }; 0114 0115 /** 0116 * qed_hw_init(): Init Qed hardware. 0117 * 0118 * @cdev: Qed dev pointer. 0119 * @p_params: Pointers to params. 0120 * 0121 * Return: Int. 0122 */ 0123 int qed_hw_init(struct qed_dev *cdev, struct qed_hw_init_params *p_params); 0124 0125 /** 0126 * qed_hw_timers_stop_all(): Stop the timers HW block. 0127 * 0128 * @cdev: Qed dev pointer. 0129 * 0130 * Return: void. 0131 */ 0132 void qed_hw_timers_stop_all(struct qed_dev *cdev); 0133 0134 /** 0135 * qed_hw_stop(): Stop Qed hardware. 0136 * 0137 * @cdev: Qed dev pointer. 0138 * 0139 * Return: int. 0140 */ 0141 int qed_hw_stop(struct qed_dev *cdev); 0142 0143 /** 0144 * qed_hw_stop_fastpath(): Should be called incase 0145 * slowpath is still required for the device, 0146 * but fastpath is not. 0147 * 0148 * @cdev: Qed dev pointer. 0149 * 0150 * Return: Int. 0151 */ 0152 int qed_hw_stop_fastpath(struct qed_dev *cdev); 0153 0154 /** 0155 * qed_hw_start_fastpath(): Restart fastpath traffic, 0156 * only if hw_stop_fastpath was called. 0157 * 0158 * @p_hwfn: HW device data. 0159 * 0160 * Return: Int. 0161 */ 0162 int qed_hw_start_fastpath(struct qed_hwfn *p_hwfn); 0163 0164 /** 0165 * qed_hw_prepare(): Prepare Qed hardware. 0166 * 0167 * @cdev: Qed dev pointer. 0168 * @personality: Personality to initialize. 0169 * 0170 * Return: Int. 0171 */ 0172 int qed_hw_prepare(struct qed_dev *cdev, 0173 int personality); 0174 0175 /** 0176 * qed_hw_remove(): Remove Qed hardware. 0177 * 0178 * @cdev: Qed dev pointer. 0179 * 0180 * Return: Void. 0181 */ 0182 void qed_hw_remove(struct qed_dev *cdev); 0183 0184 /** 0185 * qed_ptt_acquire(): Allocate a PTT window. 0186 * 0187 * @p_hwfn: HW device data. 0188 * 0189 * Return: struct qed_ptt. 0190 * 0191 * Should be called at the entry point to the driver (at the beginning of an 0192 * exported function). 0193 */ 0194 struct qed_ptt *qed_ptt_acquire(struct qed_hwfn *p_hwfn); 0195 0196 /** 0197 * qed_ptt_release(): Release PTT Window. 0198 * 0199 * @p_hwfn: HW device data. 0200 * @p_ptt: P_ptt. 0201 * 0202 * Return: Void. 0203 * 0204 * Should be called at the end of a flow - at the end of the function that 0205 * acquired the PTT. 0206 */ 0207 void qed_ptt_release(struct qed_hwfn *p_hwfn, 0208 struct qed_ptt *p_ptt); 0209 void qed_reset_vport_stats(struct qed_dev *cdev); 0210 0211 enum qed_dmae_address_type_t { 0212 QED_DMAE_ADDRESS_HOST_VIRT, 0213 QED_DMAE_ADDRESS_HOST_PHYS, 0214 QED_DMAE_ADDRESS_GRC 0215 }; 0216 0217 /** 0218 * qed_dmae_host2grc(): Copy data from source addr to 0219 * dmae registers using the given ptt. 0220 * 0221 * @p_hwfn: HW device data. 0222 * @p_ptt: P_ptt. 0223 * @source_addr: Source address. 0224 * @grc_addr: GRC address (dmae_data_offset). 0225 * @size_in_dwords: Size. 0226 * @p_params: (default parameters will be used in case of NULL). 0227 * 0228 * Return: Int. 0229 */ 0230 int 0231 qed_dmae_host2grc(struct qed_hwfn *p_hwfn, 0232 struct qed_ptt *p_ptt, 0233 u64 source_addr, 0234 u32 grc_addr, 0235 u32 size_in_dwords, 0236 struct qed_dmae_params *p_params); 0237 0238 /** 0239 * qed_dmae_grc2host(): Read data from dmae data offset 0240 * to source address using the given ptt. 0241 * 0242 * @p_ptt: P_ptt. 0243 * @grc_addr: GRC address (dmae_data_offset). 0244 * @dest_addr: Destination Address. 0245 * @size_in_dwords: Size. 0246 * @p_params: (default parameters will be used in case of NULL). 0247 * 0248 * Return: Int. 0249 */ 0250 int qed_dmae_grc2host(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 0251 u32 grc_addr, dma_addr_t dest_addr, u32 size_in_dwords, 0252 struct qed_dmae_params *p_params); 0253 0254 /** 0255 * qed_dmae_host2host(): Copy data from to source address 0256 * to a destination adrress (for SRIOV) using the given 0257 * ptt. 0258 * 0259 * @p_hwfn: HW device data. 0260 * @p_ptt: P_ptt. 0261 * @source_addr: Source address. 0262 * @dest_addr: Destination address. 0263 * @size_in_dwords: size. 0264 * @p_params: (default parameters will be used in case of NULL). 0265 * 0266 * Return: Int. 0267 */ 0268 int qed_dmae_host2host(struct qed_hwfn *p_hwfn, 0269 struct qed_ptt *p_ptt, 0270 dma_addr_t source_addr, 0271 dma_addr_t dest_addr, 0272 u32 size_in_dwords, struct qed_dmae_params *p_params); 0273 0274 int qed_chain_alloc(struct qed_dev *cdev, struct qed_chain *chain, 0275 struct qed_chain_init_params *params); 0276 void qed_chain_free(struct qed_dev *cdev, struct qed_chain *chain); 0277 0278 /** 0279 * qed_fw_l2_queue(): Get absolute L2 queue ID. 0280 * 0281 * @p_hwfn: HW device data. 0282 * @src_id: Relative to p_hwfn. 0283 * @dst_id: Absolute per engine. 0284 * 0285 * Return: Int. 0286 */ 0287 int qed_fw_l2_queue(struct qed_hwfn *p_hwfn, 0288 u16 src_id, 0289 u16 *dst_id); 0290 0291 /** 0292 * qed_fw_vport(): Get absolute vport ID. 0293 * 0294 * @p_hwfn: HW device data. 0295 * @src_id: Relative to p_hwfn. 0296 * @dst_id: Absolute per engine. 0297 * 0298 * Return: Int. 0299 */ 0300 int qed_fw_vport(struct qed_hwfn *p_hwfn, 0301 u8 src_id, 0302 u8 *dst_id); 0303 0304 /** 0305 * qed_fw_rss_eng(): Get absolute RSS engine ID. 0306 * 0307 * @p_hwfn: HW device data. 0308 * @src_id: Relative to p_hwfn. 0309 * @dst_id: Absolute per engine. 0310 * 0311 * Return: Int. 0312 */ 0313 int qed_fw_rss_eng(struct qed_hwfn *p_hwfn, 0314 u8 src_id, 0315 u8 *dst_id); 0316 0317 /** 0318 * qed_llh_get_num_ppfid(): Return the allocated number of LLH filter 0319 * banks that are allocated to the PF. 0320 * 0321 * @cdev: Qed dev pointer. 0322 * 0323 * Return: u8 Number of LLH filter banks. 0324 */ 0325 u8 qed_llh_get_num_ppfid(struct qed_dev *cdev); 0326 0327 enum qed_eng { 0328 QED_ENG0, 0329 QED_ENG1, 0330 QED_BOTH_ENG, 0331 }; 0332 0333 /** 0334 * qed_llh_set_ppfid_affinity(): Set the engine affinity for the given 0335 * LLH filter bank. 0336 * 0337 * @cdev: Qed dev pointer. 0338 * @ppfid: Relative within the allocated ppfids ('0' is the default one). 0339 * @eng: Engine. 0340 * 0341 * Return: Int. 0342 */ 0343 int qed_llh_set_ppfid_affinity(struct qed_dev *cdev, 0344 u8 ppfid, enum qed_eng eng); 0345 0346 /** 0347 * qed_llh_set_roce_affinity(): Set the RoCE engine affinity. 0348 * 0349 * @cdev: Qed dev pointer. 0350 * @eng: Engine. 0351 * 0352 * Return: Int. 0353 */ 0354 int qed_llh_set_roce_affinity(struct qed_dev *cdev, enum qed_eng eng); 0355 0356 /** 0357 * qed_llh_add_mac_filter(): Add a LLH MAC filter into the given filter 0358 * bank. 0359 * 0360 * @cdev: Qed dev pointer. 0361 * @ppfid: Relative within the allocated ppfids ('0' is the default one). 0362 * @mac_addr: MAC to add. 0363 * 0364 * Return: Int. 0365 */ 0366 int qed_llh_add_mac_filter(struct qed_dev *cdev, 0367 u8 ppfid, const u8 mac_addr[ETH_ALEN]); 0368 0369 /** 0370 * qed_llh_remove_mac_filter(): Remove a LLH MAC filter from the given 0371 * filter bank. 0372 * 0373 * @cdev: Qed dev pointer. 0374 * @ppfid: Ppfid. 0375 * @mac_addr: MAC to remove 0376 * 0377 * Return: Void. 0378 */ 0379 void qed_llh_remove_mac_filter(struct qed_dev *cdev, 0380 u8 ppfid, u8 mac_addr[ETH_ALEN]); 0381 0382 enum qed_llh_prot_filter_type_t { 0383 QED_LLH_FILTER_ETHERTYPE, 0384 QED_LLH_FILTER_TCP_SRC_PORT, 0385 QED_LLH_FILTER_TCP_DEST_PORT, 0386 QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT, 0387 QED_LLH_FILTER_UDP_SRC_PORT, 0388 QED_LLH_FILTER_UDP_DEST_PORT, 0389 QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT 0390 }; 0391 0392 /** 0393 * qed_llh_add_protocol_filter(): Add a LLH protocol filter into the 0394 * given filter bank. 0395 * 0396 * @cdev: Qed dev pointer. 0397 * @ppfid: Relative within the allocated ppfids ('0' is the default one). 0398 * @type: Type of filters and comparing. 0399 * @source_port_or_eth_type: Source port or ethertype to add. 0400 * @dest_port: Destination port to add. 0401 * 0402 * Return: Int. 0403 */ 0404 int 0405 qed_llh_add_protocol_filter(struct qed_dev *cdev, 0406 u8 ppfid, 0407 enum qed_llh_prot_filter_type_t type, 0408 u16 source_port_or_eth_type, u16 dest_port); 0409 0410 /** 0411 * qed_llh_remove_protocol_filter(): Remove a LLH protocol filter from 0412 * the given filter bank. 0413 * 0414 * @cdev: Qed dev pointer. 0415 * @ppfid: Relative within the allocated ppfids ('0' is the default one). 0416 * @type: Type of filters and comparing. 0417 * @source_port_or_eth_type: Source port or ethertype to add. 0418 * @dest_port: Destination port to add. 0419 */ 0420 void 0421 qed_llh_remove_protocol_filter(struct qed_dev *cdev, 0422 u8 ppfid, 0423 enum qed_llh_prot_filter_type_t type, 0424 u16 source_port_or_eth_type, u16 dest_port); 0425 0426 /** 0427 * qed_final_cleanup(): Cleanup of previous driver remains prior to load. 0428 * 0429 * @p_hwfn: HW device data. 0430 * @p_ptt: P_ptt. 0431 * @id: For PF, engine-relative. For VF, PF-relative. 0432 * @is_vf: True iff cleanup is made for a VF. 0433 * 0434 * Return: Int. 0435 */ 0436 int qed_final_cleanup(struct qed_hwfn *p_hwfn, 0437 struct qed_ptt *p_ptt, u16 id, bool is_vf); 0438 0439 /** 0440 * qed_get_queue_coalesce(): Retrieve coalesce value for a given queue. 0441 * 0442 * @p_hwfn: HW device data. 0443 * @coal: Store coalesce value read from the hardware. 0444 * @handle: P_handle. 0445 * 0446 * Return: Int. 0447 **/ 0448 int qed_get_queue_coalesce(struct qed_hwfn *p_hwfn, u16 *coal, void *handle); 0449 0450 /** 0451 * qed_set_queue_coalesce(): Configure coalesce parameters for Rx and 0452 * Tx queue. The fact that we can configure coalescing to up to 511, but on 0453 * varying accuracy [the bigger the value the less accurate] up to a mistake 0454 * of 3usec for the highest values. 0455 * While the API allows setting coalescing per-qid, all queues sharing a SB 0456 * should be in same range [i.e., either 0-0x7f, 0x80-0xff or 0x100-0x1ff] 0457 * otherwise configuration would break. 0458 * 0459 * @rx_coal: Rx Coalesce value in micro seconds. 0460 * @tx_coal: TX Coalesce value in micro seconds. 0461 * @p_handle: P_handle. 0462 * 0463 * Return: Int. 0464 **/ 0465 int 0466 qed_set_queue_coalesce(u16 rx_coal, u16 tx_coal, void *p_handle); 0467 0468 /** 0469 * qed_pglueb_set_pfid_enable(): Enable or disable PCI BUS MASTER. 0470 * 0471 * @p_hwfn: HW device data. 0472 * @p_ptt: P_ptt. 0473 * @b_enable: True/False. 0474 * 0475 * Return: Int. 0476 */ 0477 int qed_pglueb_set_pfid_enable(struct qed_hwfn *p_hwfn, 0478 struct qed_ptt *p_ptt, bool b_enable); 0479 0480 /** 0481 * qed_db_recovery_add(): add doorbell information to the doorbell 0482 * recovery mechanism. 0483 * 0484 * @cdev: Qed dev pointer. 0485 * @db_addr: Doorbell address. 0486 * @db_data: Address of where db_data is stored. 0487 * @db_width: Doorbell is 32b pr 64b. 0488 * @db_space: Doorbell recovery addresses are user or kernel space. 0489 * 0490 * Return: Int. 0491 */ 0492 int qed_db_recovery_add(struct qed_dev *cdev, 0493 void __iomem *db_addr, 0494 void *db_data, 0495 enum qed_db_rec_width db_width, 0496 enum qed_db_rec_space db_space); 0497 0498 /** 0499 * qed_db_recovery_del() - remove doorbell information from the doorbell 0500 * recovery mechanism. db_data serves as key (db_addr is not unique). 0501 * 0502 * @cdev: Qed dev pointer. 0503 * @db_addr: doorbell address. 0504 * @db_data: address where db_data is stored. Serves as key for the 0505 * entry to delete. 0506 * 0507 * Return: Int. 0508 */ 0509 int qed_db_recovery_del(struct qed_dev *cdev, 0510 void __iomem *db_addr, void *db_data); 0511 0512 const char *qed_hw_get_resc_name(enum qed_resources res_id); 0513 #endif
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