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0001 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
0002 /* QLogic qed NIC Driver
0003  * Copyright (c) 2019-2021 Marvell International Ltd.
0004  */
0005 #ifndef _QED_DBG_HSI_H
0006 #define _QED_DBG_HSI_H
0007 
0008 #include <linux/types.h>
0009 #include <linux/io.h>
0010 #include <linux/bitops.h>
0011 #include <linux/delay.h>
0012 #include <linux/kernel.h>
0013 #include <linux/list.h>
0014 #include <linux/slab.h>
0015 
0016 /****************************************/
0017 /* Debug Tools HSI constants and macros */
0018 /****************************************/
0019 
0020 enum block_id {
0021     BLOCK_GRC,
0022     BLOCK_MISCS,
0023     BLOCK_MISC,
0024     BLOCK_DBU,
0025     BLOCK_PGLUE_B,
0026     BLOCK_CNIG,
0027     BLOCK_CPMU,
0028     BLOCK_NCSI,
0029     BLOCK_OPTE,
0030     BLOCK_BMB,
0031     BLOCK_PCIE,
0032     BLOCK_MCP,
0033     BLOCK_MCP2,
0034     BLOCK_PSWHST,
0035     BLOCK_PSWHST2,
0036     BLOCK_PSWRD,
0037     BLOCK_PSWRD2,
0038     BLOCK_PSWWR,
0039     BLOCK_PSWWR2,
0040     BLOCK_PSWRQ,
0041     BLOCK_PSWRQ2,
0042     BLOCK_PGLCS,
0043     BLOCK_DMAE,
0044     BLOCK_PTU,
0045     BLOCK_TCM,
0046     BLOCK_MCM,
0047     BLOCK_UCM,
0048     BLOCK_XCM,
0049     BLOCK_YCM,
0050     BLOCK_PCM,
0051     BLOCK_QM,
0052     BLOCK_TM,
0053     BLOCK_DORQ,
0054     BLOCK_BRB,
0055     BLOCK_SRC,
0056     BLOCK_PRS,
0057     BLOCK_TSDM,
0058     BLOCK_MSDM,
0059     BLOCK_USDM,
0060     BLOCK_XSDM,
0061     BLOCK_YSDM,
0062     BLOCK_PSDM,
0063     BLOCK_TSEM,
0064     BLOCK_MSEM,
0065     BLOCK_USEM,
0066     BLOCK_XSEM,
0067     BLOCK_YSEM,
0068     BLOCK_PSEM,
0069     BLOCK_RSS,
0070     BLOCK_TMLD,
0071     BLOCK_MULD,
0072     BLOCK_YULD,
0073     BLOCK_XYLD,
0074     BLOCK_PRM,
0075     BLOCK_PBF_PB1,
0076     BLOCK_PBF_PB2,
0077     BLOCK_RPB,
0078     BLOCK_BTB,
0079     BLOCK_PBF,
0080     BLOCK_RDIF,
0081     BLOCK_TDIF,
0082     BLOCK_CDU,
0083     BLOCK_CCFC,
0084     BLOCK_TCFC,
0085     BLOCK_IGU,
0086     BLOCK_CAU,
0087     BLOCK_UMAC,
0088     BLOCK_XMAC,
0089     BLOCK_MSTAT,
0090     BLOCK_DBG,
0091     BLOCK_NIG,
0092     BLOCK_WOL,
0093     BLOCK_BMBN,
0094     BLOCK_IPC,
0095     BLOCK_NWM,
0096     BLOCK_NWS,
0097     BLOCK_MS,
0098     BLOCK_PHY_PCIE,
0099     BLOCK_LED,
0100     BLOCK_AVS_WRAP,
0101     BLOCK_PXPREQBUS,
0102     BLOCK_BAR0_MAP,
0103     BLOCK_MCP_FIO,
0104     BLOCK_LAST_INIT,
0105     BLOCK_PRS_FC,
0106     BLOCK_PBF_FC,
0107     BLOCK_NIG_LB_FC,
0108     BLOCK_NIG_LB_FC_PLLH,
0109     BLOCK_NIG_TX_FC_PLLH,
0110     BLOCK_NIG_TX_FC,
0111     BLOCK_NIG_RX_FC_PLLH,
0112     BLOCK_NIG_RX_FC,
0113     MAX_BLOCK_ID
0114 };
0115 
0116 /* binary debug buffer types */
0117 enum bin_dbg_buffer_type {
0118     BIN_BUF_DBG_MODE_TREE,
0119     BIN_BUF_DBG_DUMP_REG,
0120     BIN_BUF_DBG_DUMP_MEM,
0121     BIN_BUF_DBG_IDLE_CHK_REGS,
0122     BIN_BUF_DBG_IDLE_CHK_IMMS,
0123     BIN_BUF_DBG_IDLE_CHK_RULES,
0124     BIN_BUF_DBG_IDLE_CHK_PARSING_DATA,
0125     BIN_BUF_DBG_ATTN_BLOCKS,
0126     BIN_BUF_DBG_ATTN_REGS,
0127     BIN_BUF_DBG_ATTN_INDEXES,
0128     BIN_BUF_DBG_ATTN_NAME_OFFSETS,
0129     BIN_BUF_DBG_BLOCKS,
0130     BIN_BUF_DBG_BLOCKS_CHIP_DATA,
0131     BIN_BUF_DBG_BUS_LINES,
0132     BIN_BUF_DBG_BLOCKS_USER_DATA,
0133     BIN_BUF_DBG_BLOCKS_CHIP_USER_DATA,
0134     BIN_BUF_DBG_BUS_LINE_NAME_OFFSETS,
0135     BIN_BUF_DBG_RESET_REGS,
0136     BIN_BUF_DBG_PARSING_STRINGS,
0137     MAX_BIN_DBG_BUFFER_TYPE
0138 };
0139 
0140 /* Attention bit mapping */
0141 struct dbg_attn_bit_mapping {
0142     u16 data;
0143 #define DBG_ATTN_BIT_MAPPING_VAL_MASK           0x7FFF
0144 #define DBG_ATTN_BIT_MAPPING_VAL_SHIFT          0
0145 #define DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_MASK 0x1
0146 #define DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_SHIFT    15
0147 };
0148 
0149 /* Attention block per-type data */
0150 struct dbg_attn_block_type_data {
0151     u16 names_offset;
0152     u16 reserved1;
0153     u8 num_regs;
0154     u8 reserved2;
0155     u16 regs_offset;
0156 
0157 };
0158 
0159 /* Block attentions */
0160 struct dbg_attn_block {
0161     struct dbg_attn_block_type_data per_type_data[2];
0162 };
0163 
0164 /* Attention register result */
0165 struct dbg_attn_reg_result {
0166     u32 data;
0167 #define DBG_ATTN_REG_RESULT_STS_ADDRESS_MASK    0xFFFFFF
0168 #define DBG_ATTN_REG_RESULT_STS_ADDRESS_SHIFT   0
0169 #define DBG_ATTN_REG_RESULT_NUM_REG_ATTN_MASK   0xFF
0170 #define DBG_ATTN_REG_RESULT_NUM_REG_ATTN_SHIFT  24
0171     u16 block_attn_offset;
0172     u16 reserved;
0173     u32 sts_val;
0174     u32 mask_val;
0175 };
0176 
0177 /* Attention block result */
0178 struct dbg_attn_block_result {
0179     u8 block_id;
0180     u8 data;
0181 #define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_MASK    0x3
0182 #define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_SHIFT   0
0183 #define DBG_ATTN_BLOCK_RESULT_NUM_REGS_MASK 0x3F
0184 #define DBG_ATTN_BLOCK_RESULT_NUM_REGS_SHIFT    2
0185     u16 names_offset;
0186     struct dbg_attn_reg_result reg_results[15];
0187 };
0188 
0189 /* Mode header */
0190 struct dbg_mode_hdr {
0191     u16 data;
0192 #define DBG_MODE_HDR_EVAL_MODE_MASK     0x1
0193 #define DBG_MODE_HDR_EVAL_MODE_SHIFT        0
0194 #define DBG_MODE_HDR_MODES_BUF_OFFSET_MASK  0x7FFF
0195 #define DBG_MODE_HDR_MODES_BUF_OFFSET_SHIFT 1
0196 };
0197 
0198 /* Attention register */
0199 struct dbg_attn_reg {
0200     struct dbg_mode_hdr mode;
0201     u16 block_attn_offset;
0202     u32 data;
0203 #define DBG_ATTN_REG_STS_ADDRESS_MASK   0xFFFFFF
0204 #define DBG_ATTN_REG_STS_ADDRESS_SHIFT  0
0205 #define DBG_ATTN_REG_NUM_REG_ATTN_MASK  0xFF
0206 #define DBG_ATTN_REG_NUM_REG_ATTN_SHIFT 24
0207     u32 sts_clr_address;
0208     u32 mask_address;
0209 };
0210 
0211 /* Attention types */
0212 enum dbg_attn_type {
0213     ATTN_TYPE_INTERRUPT,
0214     ATTN_TYPE_PARITY,
0215     MAX_DBG_ATTN_TYPE
0216 };
0217 
0218 /* Block debug data */
0219 struct dbg_block {
0220     u8 name[15];
0221     u8 associated_storm_letter;
0222 };
0223 
0224 /* Chip-specific block debug data */
0225 struct dbg_block_chip {
0226     u8 flags;
0227 #define DBG_BLOCK_CHIP_IS_REMOVED_MASK       0x1
0228 #define DBG_BLOCK_CHIP_IS_REMOVED_SHIFT      0
0229 #define DBG_BLOCK_CHIP_HAS_RESET_REG_MASK    0x1
0230 #define DBG_BLOCK_CHIP_HAS_RESET_REG_SHIFT   1
0231 #define DBG_BLOCK_CHIP_UNRESET_BEFORE_DUMP_MASK  0x1
0232 #define DBG_BLOCK_CHIP_UNRESET_BEFORE_DUMP_SHIFT 2
0233 #define DBG_BLOCK_CHIP_HAS_DBG_BUS_MASK      0x1
0234 #define DBG_BLOCK_CHIP_HAS_DBG_BUS_SHIFT     3
0235 #define DBG_BLOCK_CHIP_HAS_LATENCY_EVENTS_MASK   0x1
0236 #define DBG_BLOCK_CHIP_HAS_LATENCY_EVENTS_SHIFT  4
0237 #define DBG_BLOCK_CHIP_RESERVED0_MASK        0x7
0238 #define DBG_BLOCK_CHIP_RESERVED0_SHIFT       5
0239     u8 dbg_client_id;
0240     u8 reset_reg_id;
0241     u8 reset_reg_bit_offset;
0242     struct dbg_mode_hdr dbg_bus_mode;
0243     u16 reserved1;
0244     u8 reserved2;
0245     u8 num_of_dbg_bus_lines;
0246     u16 dbg_bus_lines_offset;
0247     u32 dbg_select_reg_addr;
0248     u32 dbg_dword_enable_reg_addr;
0249     u32 dbg_shift_reg_addr;
0250     u32 dbg_force_valid_reg_addr;
0251     u32 dbg_force_frame_reg_addr;
0252 };
0253 
0254 /* Chip-specific block user debug data */
0255 struct dbg_block_chip_user {
0256     u8 num_of_dbg_bus_lines;
0257     u8 has_latency_events;
0258     u16 names_offset;
0259 };
0260 
0261 /* Block user debug data */
0262 struct dbg_block_user {
0263     u8 name[16];
0264 };
0265 
0266 /* Block Debug line data */
0267 struct dbg_bus_line {
0268     u8 data;
0269 #define DBG_BUS_LINE_NUM_OF_GROUPS_MASK     0xF
0270 #define DBG_BUS_LINE_NUM_OF_GROUPS_SHIFT    0
0271 #define DBG_BUS_LINE_IS_256B_MASK       0x1
0272 #define DBG_BUS_LINE_IS_256B_SHIFT      4
0273 #define DBG_BUS_LINE_RESERVED_MASK      0x7
0274 #define DBG_BUS_LINE_RESERVED_SHIFT     5
0275     u8 group_sizes;
0276 };
0277 
0278 /* Condition header for registers dump */
0279 struct dbg_dump_cond_hdr {
0280     struct dbg_mode_hdr mode; /* Mode header */
0281     u8 block_id; /* block ID */
0282     u8 data_size; /* size in dwords of the data following this header */
0283 };
0284 
0285 /* Memory data for registers dump */
0286 struct dbg_dump_mem {
0287     u32 dword0;
0288 #define DBG_DUMP_MEM_ADDRESS_MASK   0xFFFFFF
0289 #define DBG_DUMP_MEM_ADDRESS_SHIFT  0
0290 #define DBG_DUMP_MEM_MEM_GROUP_ID_MASK  0xFF
0291 #define DBG_DUMP_MEM_MEM_GROUP_ID_SHIFT 24
0292     u32 dword1;
0293 #define DBG_DUMP_MEM_LENGTH_MASK    0xFFFFFF
0294 #define DBG_DUMP_MEM_LENGTH_SHIFT   0
0295 #define DBG_DUMP_MEM_WIDE_BUS_MASK  0x1
0296 #define DBG_DUMP_MEM_WIDE_BUS_SHIFT 24
0297 #define DBG_DUMP_MEM_RESERVED_MASK  0x7F
0298 #define DBG_DUMP_MEM_RESERVED_SHIFT 25
0299 };
0300 
0301 /* Register data for registers dump */
0302 struct dbg_dump_reg {
0303     u32 data;
0304 #define DBG_DUMP_REG_ADDRESS_MASK   0x7FFFFF
0305 #define DBG_DUMP_REG_ADDRESS_SHIFT  0
0306 #define DBG_DUMP_REG_WIDE_BUS_MASK  0x1
0307 #define DBG_DUMP_REG_WIDE_BUS_SHIFT 23
0308 #define DBG_DUMP_REG_LENGTH_MASK    0xFF
0309 #define DBG_DUMP_REG_LENGTH_SHIFT   24
0310 };
0311 
0312 /* Split header for registers dump */
0313 struct dbg_dump_split_hdr {
0314     u32 hdr;
0315 #define DBG_DUMP_SPLIT_HDR_DATA_SIZE_MASK   0xFFFFFF
0316 #define DBG_DUMP_SPLIT_HDR_DATA_SIZE_SHIFT  0
0317 #define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_MASK   0xFF
0318 #define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_SHIFT  24
0319 };
0320 
0321 /* Condition header for idle check */
0322 struct dbg_idle_chk_cond_hdr {
0323     struct dbg_mode_hdr mode; /* Mode header */
0324     u16 data_size; /* size in dwords of the data following this header */
0325 };
0326 
0327 /* Idle Check condition register */
0328 struct dbg_idle_chk_cond_reg {
0329     u32 data;
0330 #define DBG_IDLE_CHK_COND_REG_ADDRESS_MASK  0x7FFFFF
0331 #define DBG_IDLE_CHK_COND_REG_ADDRESS_SHIFT 0
0332 #define DBG_IDLE_CHK_COND_REG_WIDE_BUS_MASK 0x1
0333 #define DBG_IDLE_CHK_COND_REG_WIDE_BUS_SHIFT    23
0334 #define DBG_IDLE_CHK_COND_REG_BLOCK_ID_MASK 0xFF
0335 #define DBG_IDLE_CHK_COND_REG_BLOCK_ID_SHIFT    24
0336     u16 num_entries;
0337     u8 entry_size;
0338     u8 start_entry;
0339 };
0340 
0341 /* Idle Check info register */
0342 struct dbg_idle_chk_info_reg {
0343     u32 data;
0344 #define DBG_IDLE_CHK_INFO_REG_ADDRESS_MASK  0x7FFFFF
0345 #define DBG_IDLE_CHK_INFO_REG_ADDRESS_SHIFT 0
0346 #define DBG_IDLE_CHK_INFO_REG_WIDE_BUS_MASK 0x1
0347 #define DBG_IDLE_CHK_INFO_REG_WIDE_BUS_SHIFT    23
0348 #define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_MASK 0xFF
0349 #define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_SHIFT    24
0350     u16 size; /* register size in dwords */
0351     struct dbg_mode_hdr mode; /* Mode header */
0352 };
0353 
0354 /* Idle Check register */
0355 union dbg_idle_chk_reg {
0356     struct dbg_idle_chk_cond_reg cond_reg; /* condition register */
0357     struct dbg_idle_chk_info_reg info_reg; /* info register */
0358 };
0359 
0360 /* Idle Check result header */
0361 struct dbg_idle_chk_result_hdr {
0362     u16 rule_id; /* Failing rule index */
0363     u16 mem_entry_id; /* Failing memory entry index */
0364     u8 num_dumped_cond_regs; /* number of dumped condition registers */
0365     u8 num_dumped_info_regs; /* number of dumped condition registers */
0366     u8 severity; /* from dbg_idle_chk_severity_types enum */
0367     u8 reserved;
0368 };
0369 
0370 /* Idle Check result register header */
0371 struct dbg_idle_chk_result_reg_hdr {
0372     u8 data;
0373 #define DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM_MASK  0x1
0374 #define DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM_SHIFT 0
0375 #define DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_MASK  0x7F
0376 #define DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_SHIFT 1
0377     u8 start_entry; /* index of the first checked entry */
0378     u16 size; /* register size in dwords */
0379 };
0380 
0381 /* Idle Check rule */
0382 struct dbg_idle_chk_rule {
0383     u16 rule_id; /* Idle Check rule ID */
0384     u8 severity; /* value from dbg_idle_chk_severity_types enum */
0385     u8 cond_id; /* Condition ID */
0386     u8 num_cond_regs; /* number of condition registers */
0387     u8 num_info_regs; /* number of info registers */
0388     u8 num_imms; /* number of immediates in the condition */
0389     u8 reserved1;
0390     u16 reg_offset; /* offset of this rules registers in the idle check
0391              * register array (in dbg_idle_chk_reg units).
0392              */
0393     u16 imm_offset; /* offset of this rules immediate values in the
0394              * immediate values array (in dwords).
0395              */
0396 };
0397 
0398 /* Idle Check rule parsing data */
0399 struct dbg_idle_chk_rule_parsing_data {
0400     u32 data;
0401 #define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_MASK  0x1
0402 #define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_SHIFT 0
0403 #define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_MASK  0x7FFFFFFF
0404 #define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_SHIFT 1
0405 };
0406 
0407 /* Idle check severity types */
0408 enum dbg_idle_chk_severity_types {
0409     /* idle check failure should cause an error */
0410     IDLE_CHK_SEVERITY_ERROR,
0411     /* idle check failure should cause an error only if theres no traffic */
0412     IDLE_CHK_SEVERITY_ERROR_NO_TRAFFIC,
0413     /* idle check failure should cause a warning */
0414     IDLE_CHK_SEVERITY_WARNING,
0415     MAX_DBG_IDLE_CHK_SEVERITY_TYPES
0416 };
0417 
0418 /* Reset register */
0419 struct dbg_reset_reg {
0420     u32 data;
0421 #define DBG_RESET_REG_ADDR_MASK        0xFFFFFF
0422 #define DBG_RESET_REG_ADDR_SHIFT       0
0423 #define DBG_RESET_REG_IS_REMOVED_MASK  0x1
0424 #define DBG_RESET_REG_IS_REMOVED_SHIFT 24
0425 #define DBG_RESET_REG_RESERVED_MASK    0x7F
0426 #define DBG_RESET_REG_RESERVED_SHIFT   25
0427 };
0428 
0429 /* Debug Bus block data */
0430 struct dbg_bus_block_data {
0431     u8 enable_mask;
0432     u8 right_shift;
0433     u8 force_valid_mask;
0434     u8 force_frame_mask;
0435     u8 dword_mask;
0436     u8 line_num;
0437     u8 hw_id;
0438     u8 flags;
0439 #define DBG_BUS_BLOCK_DATA_IS_256B_LINE_MASK  0x1
0440 #define DBG_BUS_BLOCK_DATA_IS_256B_LINE_SHIFT 0
0441 #define DBG_BUS_BLOCK_DATA_RESERVED_MASK      0x7F
0442 #define DBG_BUS_BLOCK_DATA_RESERVED_SHIFT     1
0443 };
0444 
0445 enum dbg_bus_clients {
0446     DBG_BUS_CLIENT_RBCN,
0447     DBG_BUS_CLIENT_RBCP,
0448     DBG_BUS_CLIENT_RBCR,
0449     DBG_BUS_CLIENT_RBCT,
0450     DBG_BUS_CLIENT_RBCU,
0451     DBG_BUS_CLIENT_RBCF,
0452     DBG_BUS_CLIENT_RBCX,
0453     DBG_BUS_CLIENT_RBCS,
0454     DBG_BUS_CLIENT_RBCH,
0455     DBG_BUS_CLIENT_RBCZ,
0456     DBG_BUS_CLIENT_OTHER_ENGINE,
0457     DBG_BUS_CLIENT_TIMESTAMP,
0458     DBG_BUS_CLIENT_CPU,
0459     DBG_BUS_CLIENT_RBCY,
0460     DBG_BUS_CLIENT_RBCQ,
0461     DBG_BUS_CLIENT_RBCM,
0462     DBG_BUS_CLIENT_RBCB,
0463     DBG_BUS_CLIENT_RBCW,
0464     DBG_BUS_CLIENT_RBCV,
0465     MAX_DBG_BUS_CLIENTS
0466 };
0467 
0468 /* Debug Bus constraint operation types */
0469 enum dbg_bus_constraint_ops {
0470     DBG_BUS_CONSTRAINT_OP_EQ,
0471     DBG_BUS_CONSTRAINT_OP_NE,
0472     DBG_BUS_CONSTRAINT_OP_LT,
0473     DBG_BUS_CONSTRAINT_OP_LTC,
0474     DBG_BUS_CONSTRAINT_OP_LE,
0475     DBG_BUS_CONSTRAINT_OP_LEC,
0476     DBG_BUS_CONSTRAINT_OP_GT,
0477     DBG_BUS_CONSTRAINT_OP_GTC,
0478     DBG_BUS_CONSTRAINT_OP_GE,
0479     DBG_BUS_CONSTRAINT_OP_GEC,
0480     MAX_DBG_BUS_CONSTRAINT_OPS
0481 };
0482 
0483 /* Debug Bus trigger state data */
0484 struct dbg_bus_trigger_state_data {
0485     u8 msg_len;
0486     u8 constraint_dword_mask;
0487     u8 storm_id;
0488     u8 reserved;
0489 };
0490 
0491 /* Debug Bus memory address */
0492 struct dbg_bus_mem_addr {
0493     u32 lo;
0494     u32 hi;
0495 };
0496 
0497 /* Debug Bus PCI buffer data */
0498 struct dbg_bus_pci_buf_data {
0499     struct dbg_bus_mem_addr phys_addr; /* PCI buffer physical address */
0500     struct dbg_bus_mem_addr virt_addr; /* PCI buffer virtual address */
0501     u32 size; /* PCI buffer size in bytes */
0502 };
0503 
0504 /* Debug Bus Storm EID range filter params */
0505 struct dbg_bus_storm_eid_range_params {
0506     u8 min; /* Minimal event ID to filter on */
0507     u8 max; /* Maximal event ID to filter on */
0508 };
0509 
0510 /* Debug Bus Storm EID mask filter params */
0511 struct dbg_bus_storm_eid_mask_params {
0512     u8 val; /* Event ID value */
0513     u8 mask; /* Event ID mask. 1s in the mask = dont care bits. */
0514 };
0515 
0516 /* Debug Bus Storm EID filter params */
0517 union dbg_bus_storm_eid_params {
0518     struct dbg_bus_storm_eid_range_params range;
0519     struct dbg_bus_storm_eid_mask_params mask;
0520 };
0521 
0522 /* Debug Bus Storm data */
0523 struct dbg_bus_storm_data {
0524     u8 enabled;
0525     u8 mode;
0526     u8 hw_id;
0527     u8 eid_filter_en;
0528     u8 eid_range_not_mask;
0529     u8 cid_filter_en;
0530     union dbg_bus_storm_eid_params eid_filter_params;
0531     u32 cid;
0532 };
0533 
0534 /* Debug Bus data */
0535 struct dbg_bus_data {
0536     u32 app_version;
0537     u8 state;
0538     u8 mode_256b_en;
0539     u8 num_enabled_blocks;
0540     u8 num_enabled_storms;
0541     u8 target;
0542     u8 one_shot_en;
0543     u8 grc_input_en;
0544     u8 timestamp_input_en;
0545     u8 filter_en;
0546     u8 adding_filter;
0547     u8 filter_pre_trigger;
0548     u8 filter_post_trigger;
0549     u8 trigger_en;
0550     u8 filter_constraint_dword_mask;
0551     u8 next_trigger_state;
0552     u8 next_constraint_id;
0553     struct dbg_bus_trigger_state_data trigger_states[3];
0554     u8 filter_msg_len;
0555     u8 rcv_from_other_engine;
0556     u8 blocks_dword_mask;
0557     u8 blocks_dword_overlap;
0558     u32 hw_id_mask;
0559     struct dbg_bus_pci_buf_data pci_buf;
0560     struct dbg_bus_block_data blocks[132];
0561     struct dbg_bus_storm_data storms[6];
0562 };
0563 
0564 /* Debug bus states */
0565 enum dbg_bus_states {
0566     DBG_BUS_STATE_IDLE,
0567     DBG_BUS_STATE_READY,
0568     DBG_BUS_STATE_RECORDING,
0569     DBG_BUS_STATE_STOPPED,
0570     MAX_DBG_BUS_STATES
0571 };
0572 
0573 /* Debug Bus Storm modes */
0574 enum dbg_bus_storm_modes {
0575     DBG_BUS_STORM_MODE_PRINTF,
0576     DBG_BUS_STORM_MODE_PRAM_ADDR,
0577     DBG_BUS_STORM_MODE_DRA_RW,
0578     DBG_BUS_STORM_MODE_DRA_W,
0579     DBG_BUS_STORM_MODE_LD_ST_ADDR,
0580     DBG_BUS_STORM_MODE_DRA_FSM,
0581     DBG_BUS_STORM_MODE_FAST_DBGMUX,
0582     DBG_BUS_STORM_MODE_RH,
0583     DBG_BUS_STORM_MODE_RH_WITH_STORE,
0584     DBG_BUS_STORM_MODE_FOC,
0585     DBG_BUS_STORM_MODE_EXT_STORE,
0586     MAX_DBG_BUS_STORM_MODES
0587 };
0588 
0589 /* Debug bus target IDs */
0590 enum dbg_bus_targets {
0591     DBG_BUS_TARGET_ID_INT_BUF,
0592     DBG_BUS_TARGET_ID_NIG,
0593     DBG_BUS_TARGET_ID_PCI,
0594     MAX_DBG_BUS_TARGETS
0595 };
0596 
0597 /* GRC Dump data */
0598 struct dbg_grc_data {
0599     u8 params_initialized;
0600     u8 reserved1;
0601     u16 reserved2;
0602     u32 param_val[48];
0603 };
0604 
0605 /* Debug GRC params */
0606 enum dbg_grc_params {
0607     DBG_GRC_PARAM_DUMP_TSTORM,
0608     DBG_GRC_PARAM_DUMP_MSTORM,
0609     DBG_GRC_PARAM_DUMP_USTORM,
0610     DBG_GRC_PARAM_DUMP_XSTORM,
0611     DBG_GRC_PARAM_DUMP_YSTORM,
0612     DBG_GRC_PARAM_DUMP_PSTORM,
0613     DBG_GRC_PARAM_DUMP_REGS,
0614     DBG_GRC_PARAM_DUMP_RAM,
0615     DBG_GRC_PARAM_DUMP_PBUF,
0616     DBG_GRC_PARAM_DUMP_IOR,
0617     DBG_GRC_PARAM_DUMP_VFC,
0618     DBG_GRC_PARAM_DUMP_CM_CTX,
0619     DBG_GRC_PARAM_DUMP_PXP,
0620     DBG_GRC_PARAM_DUMP_RSS,
0621     DBG_GRC_PARAM_DUMP_CAU,
0622     DBG_GRC_PARAM_DUMP_QM,
0623     DBG_GRC_PARAM_DUMP_MCP,
0624     DBG_GRC_PARAM_DUMP_DORQ,
0625     DBG_GRC_PARAM_DUMP_CFC,
0626     DBG_GRC_PARAM_DUMP_IGU,
0627     DBG_GRC_PARAM_DUMP_BRB,
0628     DBG_GRC_PARAM_DUMP_BTB,
0629     DBG_GRC_PARAM_DUMP_BMB,
0630     DBG_GRC_PARAM_RESERVD1,
0631     DBG_GRC_PARAM_DUMP_MULD,
0632     DBG_GRC_PARAM_DUMP_PRS,
0633     DBG_GRC_PARAM_DUMP_DMAE,
0634     DBG_GRC_PARAM_DUMP_TM,
0635     DBG_GRC_PARAM_DUMP_SDM,
0636     DBG_GRC_PARAM_DUMP_DIF,
0637     DBG_GRC_PARAM_DUMP_STATIC,
0638     DBG_GRC_PARAM_UNSTALL,
0639     DBG_GRC_PARAM_RESERVED2,
0640     DBG_GRC_PARAM_MCP_TRACE_META_SIZE,
0641     DBG_GRC_PARAM_EXCLUDE_ALL,
0642     DBG_GRC_PARAM_CRASH,
0643     DBG_GRC_PARAM_PARITY_SAFE,
0644     DBG_GRC_PARAM_DUMP_CM,
0645     DBG_GRC_PARAM_DUMP_PHY,
0646     DBG_GRC_PARAM_NO_MCP,
0647     DBG_GRC_PARAM_NO_FW_VER,
0648     DBG_GRC_PARAM_RESERVED3,
0649     DBG_GRC_PARAM_DUMP_MCP_HW_DUMP,
0650     DBG_GRC_PARAM_DUMP_ILT_CDUC,
0651     DBG_GRC_PARAM_DUMP_ILT_CDUT,
0652     DBG_GRC_PARAM_DUMP_CAU_EXT,
0653     MAX_DBG_GRC_PARAMS
0654 };
0655 
0656 /* Debug status codes */
0657 enum dbg_status {
0658     DBG_STATUS_OK,
0659     DBG_STATUS_APP_VERSION_NOT_SET,
0660     DBG_STATUS_UNSUPPORTED_APP_VERSION,
0661     DBG_STATUS_DBG_BLOCK_NOT_RESET,
0662     DBG_STATUS_INVALID_ARGS,
0663     DBG_STATUS_OUTPUT_ALREADY_SET,
0664     DBG_STATUS_INVALID_PCI_BUF_SIZE,
0665     DBG_STATUS_PCI_BUF_ALLOC_FAILED,
0666     DBG_STATUS_PCI_BUF_NOT_ALLOCATED,
0667     DBG_STATUS_INVALID_FILTER_TRIGGER_DWORDS,
0668     DBG_STATUS_NO_MATCHING_FRAMING_MODE,
0669     DBG_STATUS_VFC_READ_ERROR,
0670     DBG_STATUS_STORM_ALREADY_ENABLED,
0671     DBG_STATUS_STORM_NOT_ENABLED,
0672     DBG_STATUS_BLOCK_ALREADY_ENABLED,
0673     DBG_STATUS_BLOCK_NOT_ENABLED,
0674     DBG_STATUS_NO_INPUT_ENABLED,
0675     DBG_STATUS_NO_FILTER_TRIGGER_256B,
0676     DBG_STATUS_FILTER_ALREADY_ENABLED,
0677     DBG_STATUS_TRIGGER_ALREADY_ENABLED,
0678     DBG_STATUS_TRIGGER_NOT_ENABLED,
0679     DBG_STATUS_CANT_ADD_CONSTRAINT,
0680     DBG_STATUS_TOO_MANY_TRIGGER_STATES,
0681     DBG_STATUS_TOO_MANY_CONSTRAINTS,
0682     DBG_STATUS_RECORDING_NOT_STARTED,
0683     DBG_STATUS_DATA_DIDNT_TRIGGER,
0684     DBG_STATUS_NO_DATA_RECORDED,
0685     DBG_STATUS_DUMP_BUF_TOO_SMALL,
0686     DBG_STATUS_DUMP_NOT_CHUNK_ALIGNED,
0687     DBG_STATUS_UNKNOWN_CHIP,
0688     DBG_STATUS_VIRT_MEM_ALLOC_FAILED,
0689     DBG_STATUS_BLOCK_IN_RESET,
0690     DBG_STATUS_INVALID_TRACE_SIGNATURE,
0691     DBG_STATUS_INVALID_NVRAM_BUNDLE,
0692     DBG_STATUS_NVRAM_GET_IMAGE_FAILED,
0693     DBG_STATUS_NON_ALIGNED_NVRAM_IMAGE,
0694     DBG_STATUS_NVRAM_READ_FAILED,
0695     DBG_STATUS_IDLE_CHK_PARSE_FAILED,
0696     DBG_STATUS_MCP_TRACE_BAD_DATA,
0697     DBG_STATUS_MCP_TRACE_NO_META,
0698     DBG_STATUS_MCP_COULD_NOT_HALT,
0699     DBG_STATUS_MCP_COULD_NOT_RESUME,
0700     DBG_STATUS_RESERVED0,
0701     DBG_STATUS_SEMI_FIFO_NOT_EMPTY,
0702     DBG_STATUS_IGU_FIFO_BAD_DATA,
0703     DBG_STATUS_MCP_COULD_NOT_MASK_PRTY,
0704     DBG_STATUS_FW_ASSERTS_PARSE_FAILED,
0705     DBG_STATUS_REG_FIFO_BAD_DATA,
0706     DBG_STATUS_PROTECTION_OVERRIDE_BAD_DATA,
0707     DBG_STATUS_DBG_ARRAY_NOT_SET,
0708     DBG_STATUS_RESERVED1,
0709     DBG_STATUS_NON_MATCHING_LINES,
0710     DBG_STATUS_INSUFFICIENT_HW_IDS,
0711     DBG_STATUS_DBG_BUS_IN_USE,
0712     DBG_STATUS_INVALID_STORM_DBG_MODE,
0713     DBG_STATUS_OTHER_ENGINE_BB_ONLY,
0714     DBG_STATUS_FILTER_SINGLE_HW_ID,
0715     DBG_STATUS_TRIGGER_SINGLE_HW_ID,
0716     DBG_STATUS_MISSING_TRIGGER_STATE_STORM,
0717     MAX_DBG_STATUS
0718 };
0719 
0720 /* Debug Storms IDs */
0721 enum dbg_storms {
0722     DBG_TSTORM_ID,
0723     DBG_MSTORM_ID,
0724     DBG_USTORM_ID,
0725     DBG_XSTORM_ID,
0726     DBG_YSTORM_ID,
0727     DBG_PSTORM_ID,
0728     MAX_DBG_STORMS
0729 };
0730 
0731 /* Idle Check data */
0732 struct idle_chk_data {
0733     u32 buf_size;
0734     u8 buf_size_set;
0735     u8 reserved1;
0736     u16 reserved2;
0737 };
0738 
0739 struct pretend_params {
0740     u8 split_type;
0741     u8 reserved;
0742     u16 split_id;
0743 };
0744 
0745 /* Debug Tools data (per HW function)
0746  */
0747 struct dbg_tools_data {
0748     struct dbg_grc_data grc;
0749     struct dbg_bus_data bus;
0750     struct idle_chk_data idle_chk;
0751     u8 mode_enable[40];
0752     u8 block_in_reset[132];
0753     u8 chip_id;
0754     u8 hw_type;
0755     u8 num_ports;
0756     u8 num_pfs_per_port;
0757     u8 num_vfs;
0758     u8 initialized;
0759     u8 use_dmae;
0760     u8 reserved;
0761     struct pretend_params pretend;
0762     u32 num_regs_read;
0763 };
0764 
0765 /* ILT Clients */
0766 enum ilt_clients {
0767     ILT_CLI_CDUC,
0768     ILT_CLI_CDUT,
0769     ILT_CLI_QM,
0770     ILT_CLI_TM,
0771     ILT_CLI_SRC,
0772     ILT_CLI_TSDM,
0773     ILT_CLI_RGFS,
0774     ILT_CLI_TGFS,
0775     MAX_ILT_CLIENTS
0776 };
0777 
0778 /***************************** Public Functions *******************************/
0779 
0780 /**
0781  * qed_dbg_set_bin_ptr(): Sets a pointer to the binary data with debug
0782  *                        arrays.
0783  *
0784  * @p_hwfn: HW device data.
0785  * @bin_ptr: A pointer to the binary data with debug arrays.
0786  *
0787  * Return: enum dbg status.
0788  */
0789 enum dbg_status qed_dbg_set_bin_ptr(struct qed_hwfn *p_hwfn,
0790                     const u8 * const bin_ptr);
0791 
0792 /**
0793  * qed_read_regs(): Reads registers into a buffer (using GRC).
0794  *
0795  * @p_hwfn: HW device data.
0796  * @p_ptt: Ptt window used for writing the registers.
0797  * @buf: Destination buffer.
0798  * @addr: Source GRC address in dwords.
0799  * @len: Number of registers to read.
0800  *
0801  * Return: Void.
0802  */
0803 void qed_read_regs(struct qed_hwfn *p_hwfn,
0804            struct qed_ptt *p_ptt, u32 *buf, u32 addr, u32 len);
0805 
0806 /**
0807  * qed_read_fw_info(): Reads FW info from the chip.
0808  *
0809  * @p_hwfn: HW device data.
0810  * @p_ptt: Ptt window used for writing the registers.
0811  * @fw_info: (Out) a pointer to write the FW info into.
0812  *
0813  * Return: True if the FW info was read successfully from one of the Storms,
0814  * or false if all Storms are in reset.
0815  *
0816  * The FW info contains FW-related information, such as the FW version,
0817  * FW image (main/L2B/kuku), FW timestamp, etc.
0818  * The FW info is read from the internal RAM of the first Storm that is not in
0819  * reset.
0820  */
0821 bool qed_read_fw_info(struct qed_hwfn *p_hwfn,
0822               struct qed_ptt *p_ptt, struct fw_info *fw_info);
0823 /**
0824  * qed_dbg_grc_config(): Sets the value of a GRC parameter.
0825  *
0826  * @p_hwfn: HW device data.
0827  * @grc_param: GRC parameter.
0828  * @val: Value to set.
0829  *
0830  * Return: Error if one of the following holds:
0831  *         - The version wasn't set.
0832  *         - Grc_param is invalid.
0833  *         - Val is outside the allowed boundaries.
0834  */
0835 enum dbg_status qed_dbg_grc_config(struct qed_hwfn *p_hwfn,
0836                    enum dbg_grc_params grc_param, u32 val);
0837 
0838 /**
0839  * qed_dbg_grc_set_params_default(): Reverts all GRC parameters to their
0840  *                                   default value.
0841  *
0842  * @p_hwfn: HW device data.
0843  *
0844  * Return: Void.
0845  */
0846 void qed_dbg_grc_set_params_default(struct qed_hwfn *p_hwfn);
0847 /**
0848  * qed_dbg_grc_get_dump_buf_size(): Returns the required buffer size for
0849  *                                  GRC Dump.
0850  *
0851  * @p_hwfn: HW device data.
0852  * @p_ptt: Ptt window used for writing the registers.
0853  * @buf_size: (OUT) required buffer size (in dwords) for the GRC Dump
0854  *             data.
0855  *
0856  * Return: Error if one of the following holds:
0857  *         - The version wasn't set
0858  *           Otherwise, returns ok.
0859  */
0860 enum dbg_status qed_dbg_grc_get_dump_buf_size(struct qed_hwfn *p_hwfn,
0861                           struct qed_ptt *p_ptt,
0862                           u32 *buf_size);
0863 
0864 /**
0865  * qed_dbg_grc_dump(): Dumps GRC data into the specified buffer.
0866  *
0867  * @p_hwfn: HW device data.
0868  * @p_ptt: Ptt window used for writing the registers.
0869  * @dump_buf: Pointer to write the collected GRC data into.
0870  * @buf_size_in_dwords:Size of the specified buffer in dwords.
0871  * @num_dumped_dwords: (OUT) number of dumped dwords.
0872  *
0873  * Return: Error if one of the following holds:
0874  *        - The version wasn't set.
0875  *        - The specified dump buffer is too small.
0876  *          Otherwise, returns ok.
0877  */
0878 enum dbg_status qed_dbg_grc_dump(struct qed_hwfn *p_hwfn,
0879                  struct qed_ptt *p_ptt,
0880                  u32 *dump_buf,
0881                  u32 buf_size_in_dwords,
0882                  u32 *num_dumped_dwords);
0883 
0884 /**
0885  * qed_dbg_idle_chk_get_dump_buf_size(): Returns the required buffer size
0886  *                                       for idle check results.
0887  *
0888  * @p_hwfn: HW device data.
0889  * @p_ptt: Ptt window used for writing the registers.
0890  * @buf_size: (OUT) required buffer size (in dwords) for the idle check
0891  *             data.
0892  *
0893  * return: Error if one of the following holds:
0894  *        - The version wasn't set.
0895  *          Otherwise, returns ok.
0896  */
0897 enum dbg_status qed_dbg_idle_chk_get_dump_buf_size(struct qed_hwfn *p_hwfn,
0898                            struct qed_ptt *p_ptt,
0899                            u32 *buf_size);
0900 
0901 /**
0902  * qed_dbg_idle_chk_dump: Performs idle check and writes the results
0903  *                        into the specified buffer.
0904  *
0905  * @p_hwfn: HW device data.
0906  * @p_ptt: Ptt window used for writing the registers.
0907  * @dump_buf: Pointer to write the idle check data into.
0908  * @buf_size_in_dwords: Size of the specified buffer in dwords.
0909  * @num_dumped_dwords: (OUT) number of dumped dwords.
0910  *
0911  * Return: Error if one of the following holds:
0912  *         - The version wasn't set.
0913  *         - The specified buffer is too small.
0914  *           Otherwise, returns ok.
0915  */
0916 enum dbg_status qed_dbg_idle_chk_dump(struct qed_hwfn *p_hwfn,
0917                       struct qed_ptt *p_ptt,
0918                       u32 *dump_buf,
0919                       u32 buf_size_in_dwords,
0920                       u32 *num_dumped_dwords);
0921 
0922 /**
0923  * qed_dbg_mcp_trace_get_dump_buf_size(): Returns the required buffer size
0924  *                                        for mcp trace results.
0925  *
0926  * @p_hwfn: HW device data.
0927  * @p_ptt: Ptt window used for writing the registers.
0928  * @buf_size: (OUT) Required buffer size (in dwords) for mcp trace data.
0929  *
0930  * Return: Error if one of the following holds:
0931  *         - The version wasn't set.
0932  *         - The trace data in MCP scratchpad contain an invalid signature.
0933  *         - The bundle ID in NVRAM is invalid.
0934  *         - The trace meta data cannot be found (in NVRAM or image file).
0935  *           Otherwise, returns ok.
0936  */
0937 enum dbg_status qed_dbg_mcp_trace_get_dump_buf_size(struct qed_hwfn *p_hwfn,
0938                             struct qed_ptt *p_ptt,
0939                             u32 *buf_size);
0940 
0941 /**
0942  * qed_dbg_mcp_trace_dump(): Performs mcp trace and writes the results
0943  *                           into the specified buffer.
0944  *
0945  * @p_hwfn: HW device data.
0946  * @p_ptt: Ptt window used for writing the registers.
0947  * @dump_buf: Pointer to write the mcp trace data into.
0948  * @buf_size_in_dwords: Size of the specified buffer in dwords.
0949  * @num_dumped_dwords: (OUT) number of dumped dwords.
0950  *
0951  * Return: Error if one of the following holds:
0952  *        - The version wasn't set.
0953  *        - The specified buffer is too small.
0954  *        - The trace data in MCP scratchpad contain an invalid signature.
0955  *        - The bundle ID in NVRAM is invalid.
0956  *        - The trace meta data cannot be found (in NVRAM or image file).
0957  *        - The trace meta data cannot be read (from NVRAM or image file).
0958  *          Otherwise, returns ok.
0959  */
0960 enum dbg_status qed_dbg_mcp_trace_dump(struct qed_hwfn *p_hwfn,
0961                        struct qed_ptt *p_ptt,
0962                        u32 *dump_buf,
0963                        u32 buf_size_in_dwords,
0964                        u32 *num_dumped_dwords);
0965 
0966 /**
0967  * qed_dbg_reg_fifo_get_dump_buf_size(): Returns the required buffer size
0968  *                                       for grc trace fifo results.
0969  *
0970  * @p_hwfn: HW device data.
0971  * @p_ptt: Ptt window used for writing the registers.
0972  * @buf_size: (OUT) Required buffer size (in dwords) for reg fifo data.
0973  *
0974  * Return: Error if one of the following holds:
0975  *         - The version wasn't set
0976  *           Otherwise, returns ok.
0977  */
0978 enum dbg_status qed_dbg_reg_fifo_get_dump_buf_size(struct qed_hwfn *p_hwfn,
0979                            struct qed_ptt *p_ptt,
0980                            u32 *buf_size);
0981 
0982 /**
0983  * qed_dbg_reg_fifo_dump(): Reads the reg fifo and writes the results into
0984  *                          the specified buffer.
0985  *
0986  * @p_hwfn: HW device data.
0987  * @p_ptt: Ptt window used for writing the registers.
0988  * @dump_buf: Pointer to write the reg fifo data into.
0989  * @buf_size_in_dwords: Size of the specified buffer in dwords.
0990  * @num_dumped_dwords: (OUT) number of dumped dwords.
0991  *
0992  * Return: Error if one of the following holds:
0993  *        - The version wasn't set.
0994  *        - The specified buffer is too small.
0995  *        - DMAE transaction failed.
0996  *           Otherwise, returns ok.
0997  */
0998 enum dbg_status qed_dbg_reg_fifo_dump(struct qed_hwfn *p_hwfn,
0999                       struct qed_ptt *p_ptt,
1000                       u32 *dump_buf,
1001                       u32 buf_size_in_dwords,
1002                       u32 *num_dumped_dwords);
1003 
1004 /**
1005  * qed_dbg_igu_fifo_get_dump_buf_size(): Returns the required buffer size
1006  *                                       for the IGU fifo results.
1007  *
1008  * @p_hwfn: HW device data.
1009  * @p_ptt: Ptt window used for writing the registers.
1010  * @buf_size: (OUT) Required buffer size (in dwords) for the IGU fifo
1011  *            data.
1012  *
1013  * Return: Error if one of the following holds:
1014  *         - The version wasn't set.
1015  *           Otherwise, returns ok.
1016  */
1017 enum dbg_status qed_dbg_igu_fifo_get_dump_buf_size(struct qed_hwfn *p_hwfn,
1018                            struct qed_ptt *p_ptt,
1019                            u32 *buf_size);
1020 
1021 /**
1022  * qed_dbg_igu_fifo_dump(): Reads the IGU fifo and writes the results into
1023  *                          the specified buffer.
1024  *
1025  * @p_hwfn: HW device data.
1026  * @p_ptt: Ptt window used for writing the registers.
1027  * @dump_buf: Pointer to write the IGU fifo data into.
1028  * @buf_size_in_dwords: Size of the specified buffer in dwords.
1029  * @num_dumped_dwords: (OUT) number of dumped dwords.
1030  *
1031  * Return: Error if one of the following holds:
1032  *         - The version wasn't set
1033  *         - The specified buffer is too small
1034  *         - DMAE transaction failed
1035  *           Otherwise, returns ok.
1036  */
1037 enum dbg_status qed_dbg_igu_fifo_dump(struct qed_hwfn *p_hwfn,
1038                       struct qed_ptt *p_ptt,
1039                       u32 *dump_buf,
1040                       u32 buf_size_in_dwords,
1041                       u32 *num_dumped_dwords);
1042 
1043 /**
1044  * qed_dbg_protection_override_get_dump_buf_size(): Returns the required
1045  *        buffer size for protection override window results.
1046  *
1047  * @p_hwfn: HW device data.
1048  * @p_ptt: Ptt window used for writing the registers.
1049  * @buf_size: (OUT) Required buffer size (in dwords) for protection
1050  *             override data.
1051  *
1052  * Return: Error if one of the following holds:
1053  *         - The version wasn't set
1054  *           Otherwise, returns ok.
1055  */
1056 enum dbg_status
1057 qed_dbg_protection_override_get_dump_buf_size(struct qed_hwfn *p_hwfn,
1058                           struct qed_ptt *p_ptt,
1059                           u32 *buf_size);
1060 /**
1061  * qed_dbg_protection_override_dump(): Reads protection override window
1062  *       entries and writes the results into the specified buffer.
1063  *
1064  * @p_hwfn: HW device data.
1065  * @p_ptt: Ptt window used for writing the registers.
1066  * @dump_buf: Pointer to write the protection override data into.
1067  * @buf_size_in_dwords: Size of the specified buffer in dwords.
1068  * @num_dumped_dwords: (OUT) number of dumped dwords.
1069  *
1070  * @return: Error if one of the following holds:
1071  *          - The version wasn't set.
1072  *          - The specified buffer is too small.
1073  *          - DMAE transaction failed.
1074  *             Otherwise, returns ok.
1075  */
1076 enum dbg_status qed_dbg_protection_override_dump(struct qed_hwfn *p_hwfn,
1077                          struct qed_ptt *p_ptt,
1078                          u32 *dump_buf,
1079                          u32 buf_size_in_dwords,
1080                          u32 *num_dumped_dwords);
1081 /**
1082  * qed_dbg_fw_asserts_get_dump_buf_size(): Returns the required buffer
1083  *                                         size for FW Asserts results.
1084  *
1085  * @p_hwfn: HW device data.
1086  * @p_ptt: Ptt window used for writing the registers.
1087  * @buf_size: (OUT) Required buffer size (in dwords) for FW Asserts data.
1088  *
1089  * Return: Error if one of the following holds:
1090  *         - The version wasn't set.
1091  *           Otherwise, returns ok.
1092  */
1093 enum dbg_status qed_dbg_fw_asserts_get_dump_buf_size(struct qed_hwfn *p_hwfn,
1094                              struct qed_ptt *p_ptt,
1095                              u32 *buf_size);
1096 /**
1097  * qed_dbg_fw_asserts_dump(): Reads the FW Asserts and writes the results
1098  *                            into the specified buffer.
1099  *
1100  * @p_hwfn: HW device data.
1101  * @p_ptt: Ptt window used for writing the registers.
1102  * @dump_buf: Pointer to write the FW Asserts data into.
1103  * @buf_size_in_dwords: Size of the specified buffer in dwords.
1104  * @num_dumped_dwords: (OUT) number of dumped dwords.
1105  *
1106  * Return: Error if one of the following holds:
1107  *         - The version wasn't set.
1108  *         - The specified buffer is too small.
1109  *           Otherwise, returns ok.
1110  */
1111 enum dbg_status qed_dbg_fw_asserts_dump(struct qed_hwfn *p_hwfn,
1112                     struct qed_ptt *p_ptt,
1113                     u32 *dump_buf,
1114                     u32 buf_size_in_dwords,
1115                     u32 *num_dumped_dwords);
1116 
1117 /**
1118  * qed_dbg_read_attn(): Reads the attention registers of the specified
1119  * block and type, and writes the results into the specified buffer.
1120  *
1121  * @p_hwfn: HW device data.
1122  * @p_ptt: Ptt window used for writing the registers.
1123  * @block: Block ID.
1124  * @attn_type: Attention type.
1125  * @clear_status: Indicates if the attention status should be cleared.
1126  * @results:  (OUT) Pointer to write the read results into.
1127  *
1128  * Return: Error if one of the following holds:
1129  *         - The version wasn't set
1130  *          Otherwise, returns ok.
1131  */
1132 enum dbg_status qed_dbg_read_attn(struct qed_hwfn *p_hwfn,
1133                   struct qed_ptt *p_ptt,
1134                   enum block_id block,
1135                   enum dbg_attn_type attn_type,
1136                   bool clear_status,
1137                   struct dbg_attn_block_result *results);
1138 
1139 /**
1140  * qed_dbg_print_attn(): Prints attention registers values in the
1141  *                       specified results struct.
1142  *
1143  * @p_hwfn: HW device data.
1144  * @results: Pointer to the attention read results
1145  *
1146  * Return: Error if one of the following holds:
1147  *        - The version wasn't set
1148  *          Otherwise, returns ok.
1149  */
1150 enum dbg_status qed_dbg_print_attn(struct qed_hwfn *p_hwfn,
1151                    struct dbg_attn_block_result *results);
1152 
1153 /******************************* Data Types **********************************/
1154 
1155 struct mcp_trace_format {
1156     u32 data;
1157 #define MCP_TRACE_FORMAT_MODULE_MASK    0x0000ffff
1158 #define MCP_TRACE_FORMAT_MODULE_OFFSET  0
1159 #define MCP_TRACE_FORMAT_LEVEL_MASK 0x00030000
1160 #define MCP_TRACE_FORMAT_LEVEL_OFFSET   16
1161 #define MCP_TRACE_FORMAT_P1_SIZE_MASK   0x000c0000
1162 #define MCP_TRACE_FORMAT_P1_SIZE_OFFSET 18
1163 #define MCP_TRACE_FORMAT_P2_SIZE_MASK   0x00300000
1164 #define MCP_TRACE_FORMAT_P2_SIZE_OFFSET 20
1165 #define MCP_TRACE_FORMAT_P3_SIZE_MASK   0x00c00000
1166 #define MCP_TRACE_FORMAT_P3_SIZE_OFFSET 22
1167 #define MCP_TRACE_FORMAT_LEN_MASK   0xff000000
1168 #define MCP_TRACE_FORMAT_LEN_OFFSET 24
1169 
1170     char *format_str;
1171 };
1172 
1173 /* MCP Trace Meta data structure */
1174 struct mcp_trace_meta {
1175     u32 modules_num;
1176     char **modules;
1177     u32 formats_num;
1178     struct mcp_trace_format *formats;
1179     bool is_allocated;
1180 };
1181 
1182 /* Debug Tools user data */
1183 struct dbg_tools_user_data {
1184     struct mcp_trace_meta mcp_trace_meta;
1185     const u32 *mcp_trace_user_meta_buf;
1186 };
1187 
1188 /******************************** Constants **********************************/
1189 
1190 #define MAX_NAME_LEN    16
1191 
1192 /***************************** Public Functions *******************************/
1193 
1194 /**
1195  * qed_dbg_user_set_bin_ptr(): Sets a pointer to the binary data with
1196  *                             debug arrays.
1197  *
1198  * @p_hwfn: HW device data.
1199  * @bin_ptr: a pointer to the binary data with debug arrays.
1200  *
1201  * Return: dbg_status.
1202  */
1203 enum dbg_status qed_dbg_user_set_bin_ptr(struct qed_hwfn *p_hwfn,
1204                      const u8 * const bin_ptr);
1205 
1206 /**
1207  * qed_dbg_alloc_user_data(): Allocates user debug data.
1208  *
1209  * @p_hwfn: HW device data.
1210  * @user_data_ptr: (OUT) a pointer to the allocated memory.
1211  *
1212  * Return: dbg_status.
1213  */
1214 enum dbg_status qed_dbg_alloc_user_data(struct qed_hwfn *p_hwfn,
1215                     void **user_data_ptr);
1216 
1217 /**
1218  * qed_dbg_get_status_str(): Returns a string for the specified status.
1219  *
1220  * @status: A debug status code.
1221  *
1222  * Return: A string for the specified status.
1223  */
1224 const char *qed_dbg_get_status_str(enum dbg_status status);
1225 
1226 /**
1227  * qed_get_idle_chk_results_buf_size(): Returns the required buffer size
1228  *                                      for idle check results (in bytes).
1229  *
1230  * @p_hwfn: HW device data.
1231  * @dump_buf: idle check dump buffer.
1232  * @num_dumped_dwords: number of dwords that were dumped.
1233  * @results_buf_size: (OUT) required buffer size (in bytes) for the parsed
1234  *                    results.
1235  *
1236  * Return: Error if the parsing fails, ok otherwise.
1237  */
1238 enum dbg_status qed_get_idle_chk_results_buf_size(struct qed_hwfn *p_hwfn,
1239                           u32 *dump_buf,
1240                           u32  num_dumped_dwords,
1241                           u32 *results_buf_size);
1242 /**
1243  * qed_print_idle_chk_results(): Prints idle check results
1244  *
1245  * @p_hwfn: HW device data.
1246  * @dump_buf: idle check dump buffer.
1247  * @num_dumped_dwords: number of dwords that were dumped.
1248  * @results_buf: buffer for printing the idle check results.
1249  * @num_errors: (OUT) number of errors found in idle check.
1250  * @num_warnings: (OUT) number of warnings found in idle check.
1251  *
1252  * Return: Error if the parsing fails, ok otherwise.
1253  */
1254 enum dbg_status qed_print_idle_chk_results(struct qed_hwfn *p_hwfn,
1255                        u32 *dump_buf,
1256                        u32 num_dumped_dwords,
1257                        char *results_buf,
1258                        u32 *num_errors,
1259                        u32 *num_warnings);
1260 
1261 /**
1262  * qed_dbg_mcp_trace_set_meta_data(): Sets the MCP Trace meta data.
1263  *
1264  * @p_hwfn: HW device data.
1265  * @meta_buf: Meta buffer.
1266  *
1267  * Return: Void.
1268  *
1269  * Needed in case the MCP Trace dump doesn't contain the meta data (e.g. due to
1270  * no NVRAM access).
1271  */
1272 void qed_dbg_mcp_trace_set_meta_data(struct qed_hwfn *p_hwfn,
1273                      const u32 *meta_buf);
1274 
1275 /**
1276  * qed_get_mcp_trace_results_buf_size(): Returns the required buffer size
1277  *                                       for MCP Trace results (in bytes).
1278  *
1279  * @p_hwfn: HW device data.
1280  * @dump_buf: MCP Trace dump buffer.
1281  * @num_dumped_dwords: number of dwords that were dumped.
1282  * @results_buf_size: (OUT) required buffer size (in bytes) for the parsed
1283  *                    results.
1284  *
1285  * Return: Error if the parsing fails, ok otherwise.
1286  */
1287 enum dbg_status qed_get_mcp_trace_results_buf_size(struct qed_hwfn *p_hwfn,
1288                            u32 *dump_buf,
1289                            u32 num_dumped_dwords,
1290                            u32 *results_buf_size);
1291 
1292 /**
1293  * qed_print_mcp_trace_results(): Prints MCP Trace results
1294  *
1295  * @p_hwfn: HW device data.
1296  * @dump_buf: MCP trace dump buffer, starting from the header.
1297  * @num_dumped_dwords: Member of dwords that were dumped.
1298  * @results_buf: Buffer for printing the mcp trace results.
1299  *
1300  * Return: Error if the parsing fails, ok otherwise.
1301  */
1302 enum dbg_status qed_print_mcp_trace_results(struct qed_hwfn *p_hwfn,
1303                         u32 *dump_buf,
1304                         u32 num_dumped_dwords,
1305                         char *results_buf);
1306 
1307 /**
1308  * qed_print_mcp_trace_results_cont(): Prints MCP Trace results, and
1309  * keeps the MCP trace meta data allocated, to support continuous MCP Trace
1310  * parsing. After the continuous parsing ends, mcp_trace_free_meta_data should
1311  * be called to free the meta data.
1312  *
1313  * @p_hwfn: HW device data.
1314  * @dump_buf: MVP trace dump buffer, starting from the header.
1315  * @results_buf: Buffer for printing the mcp trace results.
1316  *
1317  * Return: Error if the parsing fails, ok otherwise.
1318  */
1319 enum dbg_status qed_print_mcp_trace_results_cont(struct qed_hwfn *p_hwfn,
1320                          u32 *dump_buf,
1321                          char *results_buf);
1322 
1323 /**
1324  * qed_print_mcp_trace_line(): Prints MCP Trace results for a single line
1325  *
1326  * @p_hwfn: HW device data.
1327  * @dump_buf: MCP trace dump buffer, starting from the header.
1328  * @num_dumped_bytes: Number of bytes that were dumped.
1329  * @results_buf: Buffer for printing the mcp trace results.
1330  *
1331  * Return: Error if the parsing fails, ok otherwise.
1332  */
1333 enum dbg_status qed_print_mcp_trace_line(struct qed_hwfn *p_hwfn,
1334                      u8 *dump_buf,
1335                      u32 num_dumped_bytes,
1336                      char *results_buf);
1337 
1338 /**
1339  * qed_mcp_trace_free_meta_data(): Frees the MCP Trace meta data.
1340  * Should be called after continuous MCP Trace parsing.
1341  *
1342  * @p_hwfn: HW device data.
1343  *
1344  * Return: Void.
1345  */
1346 void qed_mcp_trace_free_meta_data(struct qed_hwfn *p_hwfn);
1347 
1348 /**
1349  * qed_get_reg_fifo_results_buf_size(): Returns the required buffer size
1350  *                                      for reg_fifo results (in bytes).
1351  *
1352  * @p_hwfn: HW device data.
1353  * @dump_buf: Reg fifo dump buffer.
1354  * @num_dumped_dwords: Number of dwords that were dumped.
1355  * @results_buf_size: (OUT) required buffer size (in bytes) for the parsed
1356  *                     results.
1357  *
1358  * Return: Error if the parsing fails, ok otherwise.
1359  */
1360 enum dbg_status qed_get_reg_fifo_results_buf_size(struct qed_hwfn *p_hwfn,
1361                           u32 *dump_buf,
1362                           u32 num_dumped_dwords,
1363                           u32 *results_buf_size);
1364 
1365 /**
1366  * qed_print_reg_fifo_results(): Prints reg fifo results.
1367  *
1368  * @p_hwfn: HW device data.
1369  * @dump_buf: Reg fifo dump buffer, starting from the header.
1370  * @num_dumped_dwords: Number of dwords that were dumped.
1371  * @results_buf: Buffer for printing the reg fifo results.
1372  *
1373  * Return: Error if the parsing fails, ok otherwise.
1374  */
1375 enum dbg_status qed_print_reg_fifo_results(struct qed_hwfn *p_hwfn,
1376                        u32 *dump_buf,
1377                        u32 num_dumped_dwords,
1378                        char *results_buf);
1379 
1380 /**
1381  * qed_get_igu_fifo_results_buf_size(): Returns the required buffer size
1382  *                                      for igu_fifo results (in bytes).
1383  *
1384  * @p_hwfn: HW device data.
1385  * @dump_buf: IGU fifo dump buffer.
1386  * @num_dumped_dwords: number of dwords that were dumped.
1387  * @results_buf_size: (OUT) required buffer size (in bytes) for the parsed
1388  *                    results.
1389  *
1390  * Return: Error if the parsing fails, ok otherwise.
1391  */
1392 enum dbg_status qed_get_igu_fifo_results_buf_size(struct qed_hwfn *p_hwfn,
1393                           u32 *dump_buf,
1394                           u32 num_dumped_dwords,
1395                           u32 *results_buf_size);
1396 
1397 /**
1398  * qed_print_igu_fifo_results(): Prints IGU fifo results
1399  *
1400  * @p_hwfn: HW device data.
1401  * @dump_buf: IGU fifo dump buffer, starting from the header.
1402  * @num_dumped_dwords: Number of dwords that were dumped.
1403  * @results_buf: Buffer for printing the IGU fifo results.
1404  *
1405  * Return: Error if the parsing fails, ok otherwise.
1406  */
1407 enum dbg_status qed_print_igu_fifo_results(struct qed_hwfn *p_hwfn,
1408                        u32 *dump_buf,
1409                        u32 num_dumped_dwords,
1410                        char *results_buf);
1411 
1412 /**
1413  * qed_get_protection_override_results_buf_size(): Returns the required
1414  *         buffer size for protection override results (in bytes).
1415  *
1416  * @p_hwfn: HW device data.
1417  * @dump_buf: Protection override dump buffer.
1418  * @num_dumped_dwords: Number of dwords that were dumped.
1419  * @results_buf_size: (OUT) required buffer size (in bytes) for the parsed
1420  *                    results.
1421  *
1422  * Return: Error if the parsing fails, ok otherwise.
1423  */
1424 enum dbg_status
1425 qed_get_protection_override_results_buf_size(struct qed_hwfn *p_hwfn,
1426                          u32 *dump_buf,
1427                          u32 num_dumped_dwords,
1428                          u32 *results_buf_size);
1429 
1430 /**
1431  * qed_print_protection_override_results(): Prints protection override
1432  *                                          results.
1433  *
1434  * @p_hwfn: HW device data.
1435  * @dump_buf: Protection override dump buffer, starting from the header.
1436  * @num_dumped_dwords: Number of dwords that were dumped.
1437  * @results_buf: Buffer for printing the reg fifo results.
1438  *
1439  * Return: Error if the parsing fails, ok otherwise.
1440  */
1441 enum dbg_status qed_print_protection_override_results(struct qed_hwfn *p_hwfn,
1442                               u32 *dump_buf,
1443                               u32 num_dumped_dwords,
1444                               char *results_buf);
1445 
1446 /**
1447  * qed_get_fw_asserts_results_buf_size(): Returns the required buffer size
1448  *                                        for FW Asserts results (in bytes).
1449  *
1450  * @p_hwfn: HW device data.
1451  * @dump_buf: FW Asserts dump buffer.
1452  * @num_dumped_dwords: number of dwords that were dumped.
1453  * @results_buf_size: (OUT) required buffer size (in bytes) for the parsed
1454  *                    results.
1455  *
1456  * Return: Error if the parsing fails, ok otherwise.
1457  */
1458 enum dbg_status qed_get_fw_asserts_results_buf_size(struct qed_hwfn *p_hwfn,
1459                             u32 *dump_buf,
1460                             u32 num_dumped_dwords,
1461                             u32 *results_buf_size);
1462 
1463 /**
1464  * qed_print_fw_asserts_results(): Prints FW Asserts results.
1465  *
1466  * @p_hwfn: HW device data.
1467  * @dump_buf: FW Asserts dump buffer, starting from the header.
1468  * @num_dumped_dwords: number of dwords that were dumped.
1469  * @results_buf: buffer for printing the FW Asserts results.
1470  *
1471  * Return: Error if the parsing fails, ok otherwise.
1472  */
1473 enum dbg_status qed_print_fw_asserts_results(struct qed_hwfn *p_hwfn,
1474                          u32 *dump_buf,
1475                          u32 num_dumped_dwords,
1476                          char *results_buf);
1477 
1478 /**
1479  * qed_dbg_parse_attn(): Parses and prints attention registers values in
1480  *                      the specified results struct.
1481  *
1482  * @p_hwfn: HW device data.
1483  * @results: Pointer to the attention read results
1484  *
1485  * Return: Error if one of the following holds:
1486  *         - The version wasn't set.
1487  *           Otherwise, returns ok.
1488  */
1489 enum dbg_status qed_dbg_parse_attn(struct qed_hwfn *p_hwfn,
1490                    struct dbg_attn_block_result *results);
1491 #endif
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