ethernet/pasemi/pasemi_mac.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 2006 PA Semi, Inc
0004  *
0005  * Driver for the PA6T-1682M onchip 1G/10G Ethernet MACs, soft state and
0006  * hardware register layouts.
0007  */
0008
0009 #ifndef PASEMI_MAC_H
0010 #define PASEMI_MAC_H
0011
0012 #include <linux/ethtool.h>
0013 #include <linux/netdevice.h>
0014 #include <linux/spinlock.h>
0015 #include <linux/phy.h>
0016
0017 /* Must be a power of two */
0018 #define RX_RING_SIZE 2048
0019 #define TX_RING_SIZE 4096
0020 #define CS_RING_SIZE (TX_RING_SIZE*2)
0021
0022
0023 #define MAX_CS  2
0024
0025 struct pasemi_mac_txring {
0026     struct pasemi_dmachan chan; /* Must be first */
0027     spinlock_t   lock;
0028     unsigned int     size;
0029     unsigned int     next_to_fill;
0030     unsigned int     next_to_clean;
0031     struct pasemi_mac_buffer *ring_info;
0032     struct pasemi_mac *mac; /* Needed in intr handler */
0033     struct timer_list clean_timer;
0034 };
0035
0036 struct pasemi_mac_rxring {
0037     struct pasemi_dmachan chan; /* Must be first */
0038     spinlock_t   lock;
0039     u64     *buffers;   /* RX interface buffer ring */
0040     dma_addr_t   buf_dma;
0041     unsigned int     size;
0042     unsigned int     next_to_fill;
0043     unsigned int     next_to_clean;
0044     struct pasemi_mac_buffer *ring_info;
0045     struct pasemi_mac *mac; /* Needed in intr handler */
0046 };
0047
0048 struct pasemi_mac_csring {
0049     struct pasemi_dmachan chan;
0050     unsigned int    size;
0051     unsigned int    next_to_fill;
0052     int     events[2];
0053     int     last_event;
0054     int     fun;
0055 };
0056
0057 struct pasemi_mac {
0058     struct net_device *netdev;
0059     struct pci_dev *pdev;
0060     struct pci_dev *dma_pdev;
0061     struct pci_dev *iob_pdev;
0062     struct napi_struct napi;
0063
0064     int     bufsz; /* RX ring buffer size */
0065     int     last_cs;
0066     int     num_cs;
0067     u32     dma_if;
0068     u8      type;
0069 #define MAC_TYPE_GMAC   1
0070 #define MAC_TYPE_XAUI   2
0071
0072     u8      mac_addr[ETH_ALEN];
0073
0074     struct timer_list   rxtimer;
0075
0076     struct pasemi_mac_txring *tx;
0077     struct pasemi_mac_rxring *rx;
0078     struct pasemi_mac_csring *cs[MAX_CS];
0079     char        tx_irq_name[10];        /* "eth%d tx" */
0080     char        rx_irq_name[10];        /* "eth%d rx" */
0081     int link;
0082     int speed;
0083     int duplex;
0084
0085     unsigned int    msg_enable;
0086 };
0087
0088 /* Software status descriptor (ring_info) */
0089 struct pasemi_mac_buffer {
0090     struct sk_buff *skb;
0091     dma_addr_t  dma;
0092 };
0093
0094 #define TX_DESC(tx, num)    ((tx)->chan.ring_virt[(num) & (TX_RING_SIZE-1)])
0095 #define TX_DESC_INFO(tx, num)   ((tx)->ring_info[(num) & (TX_RING_SIZE-1)])
0096 #define RX_DESC(rx, num)    ((rx)->chan.ring_virt[(num) & (RX_RING_SIZE-1)])
0097 #define RX_DESC_INFO(rx, num)   ((rx)->ring_info[(num) & (RX_RING_SIZE-1)])
0098 #define RX_BUFF(rx, num)    ((rx)->buffers[(num) & (RX_RING_SIZE-1)])
0099 #define CS_DESC(cs, num)    ((cs)->chan.ring_virt[(num) & (CS_RING_SIZE-1)])
0100
0101 #define RING_USED(ring) (((ring)->next_to_fill - (ring)->next_to_clean) \
0102                 & ((ring)->size - 1))
0103 #define RING_AVAIL(ring)    ((ring->size) - RING_USED(ring))
0104
0105 /* PCI register offsets and formats */
0106
0107
0108 /* MAC CFG register offsets */
0109 enum {
0110     PAS_MAC_CFG_PCFG = 0x80,
0111     PAS_MAC_CFG_MACCFG = 0x84,
0112     PAS_MAC_CFG_ADR0 = 0x8c,
0113     PAS_MAC_CFG_ADR1 = 0x90,
0114     PAS_MAC_CFG_TXP = 0x98,
0115     PAS_MAC_CFG_RMON = 0x100,
0116     PAS_MAC_IPC_CHNL = 0x208,
0117 };
0118
0119 /* MAC CFG register fields */
0120 #define PAS_MAC_CFG_PCFG_PE     0x80000000
0121 #define PAS_MAC_CFG_PCFG_CE     0x40000000
0122 #define PAS_MAC_CFG_PCFG_BU     0x20000000
0123 #define PAS_MAC_CFG_PCFG_TT     0x10000000
0124 #define PAS_MAC_CFG_PCFG_TSR_M      0x0c000000
0125 #define PAS_MAC_CFG_PCFG_TSR_10M    0x00000000
0126 #define PAS_MAC_CFG_PCFG_TSR_100M   0x04000000
0127 #define PAS_MAC_CFG_PCFG_TSR_1G     0x08000000
0128 #define PAS_MAC_CFG_PCFG_TSR_10G    0x0c000000
0129 #define PAS_MAC_CFG_PCFG_T24        0x02000000
0130 #define PAS_MAC_CFG_PCFG_PR     0x01000000
0131 #define PAS_MAC_CFG_PCFG_CRO_M      0x00ff0000
0132 #define PAS_MAC_CFG_PCFG_CRO_S  16
0133 #define PAS_MAC_CFG_PCFG_IPO_M      0x0000ff00
0134 #define PAS_MAC_CFG_PCFG_IPO_S  8
0135 #define PAS_MAC_CFG_PCFG_S1     0x00000080
0136 #define PAS_MAC_CFG_PCFG_IO_M       0x00000060
0137 #define PAS_MAC_CFG_PCFG_IO_MAC     0x00000000
0138 #define PAS_MAC_CFG_PCFG_IO_OFF     0x00000020
0139 #define PAS_MAC_CFG_PCFG_IO_IND_ETH 0x00000040
0140 #define PAS_MAC_CFG_PCFG_IO_IND_IP  0x00000060
0141 #define PAS_MAC_CFG_PCFG_LP     0x00000010
0142 #define PAS_MAC_CFG_PCFG_TS     0x00000008
0143 #define PAS_MAC_CFG_PCFG_HD     0x00000004
0144 #define PAS_MAC_CFG_PCFG_SPD_M      0x00000003
0145 #define PAS_MAC_CFG_PCFG_SPD_10M    0x00000000
0146 #define PAS_MAC_CFG_PCFG_SPD_100M   0x00000001
0147 #define PAS_MAC_CFG_PCFG_SPD_1G     0x00000002
0148 #define PAS_MAC_CFG_PCFG_SPD_10G    0x00000003
0149
0150 #define PAS_MAC_CFG_MACCFG_TXT_M    0x70000000
0151 #define PAS_MAC_CFG_MACCFG_TXT_S    28
0152 #define PAS_MAC_CFG_MACCFG_PRES_M   0x0f000000
0153 #define PAS_MAC_CFG_MACCFG_PRES_S   24
0154 #define PAS_MAC_CFG_MACCFG_MAXF_M   0x00ffff00
0155 #define PAS_MAC_CFG_MACCFG_MAXF_S   8
0156 #define PAS_MAC_CFG_MACCFG_MAXF(x)  (((x) << PAS_MAC_CFG_MACCFG_MAXF_S) & \
0157                      PAS_MAC_CFG_MACCFG_MAXF_M)
0158 #define PAS_MAC_CFG_MACCFG_MINF_M   0x000000ff
0159 #define PAS_MAC_CFG_MACCFG_MINF_S   0
0160
0161 #define PAS_MAC_CFG_TXP_FCF     0x01000000
0162 #define PAS_MAC_CFG_TXP_FCE     0x00800000
0163 #define PAS_MAC_CFG_TXP_FC      0x00400000
0164 #define PAS_MAC_CFG_TXP_FPC_M       0x00300000
0165 #define PAS_MAC_CFG_TXP_FPC_S       20
0166 #define PAS_MAC_CFG_TXP_FPC(x)      (((x) << PAS_MAC_CFG_TXP_FPC_S) & \
0167                      PAS_MAC_CFG_TXP_FPC_M)
0168 #define PAS_MAC_CFG_TXP_RT      0x00080000
0169 #define PAS_MAC_CFG_TXP_BL      0x00040000
0170 #define PAS_MAC_CFG_TXP_SL_M        0x00030000
0171 #define PAS_MAC_CFG_TXP_SL_S        16
0172 #define PAS_MAC_CFG_TXP_SL(x)       (((x) << PAS_MAC_CFG_TXP_SL_S) & \
0173                      PAS_MAC_CFG_TXP_SL_M)
0174 #define PAS_MAC_CFG_TXP_COB_M       0x0000f000
0175 #define PAS_MAC_CFG_TXP_COB_S       12
0176 #define PAS_MAC_CFG_TXP_COB(x)      (((x) << PAS_MAC_CFG_TXP_COB_S) & \
0177                      PAS_MAC_CFG_TXP_COB_M)
0178 #define PAS_MAC_CFG_TXP_TIFT_M      0x00000f00
0179 #define PAS_MAC_CFG_TXP_TIFT_S      8
0180 #define PAS_MAC_CFG_TXP_TIFT(x)     (((x) << PAS_MAC_CFG_TXP_TIFT_S) & \
0181                      PAS_MAC_CFG_TXP_TIFT_M)
0182 #define PAS_MAC_CFG_TXP_TIFG_M      0x000000ff
0183 #define PAS_MAC_CFG_TXP_TIFG_S      0
0184 #define PAS_MAC_CFG_TXP_TIFG(x)     (((x) << PAS_MAC_CFG_TXP_TIFG_S) & \
0185                      PAS_MAC_CFG_TXP_TIFG_M)
0186
0187 #define PAS_MAC_RMON(r)         (0x100+(r)*4)
0188
0189 #define PAS_MAC_IPC_CHNL_DCHNO_M    0x003f0000
0190 #define PAS_MAC_IPC_CHNL_DCHNO_S    16
0191 #define PAS_MAC_IPC_CHNL_DCHNO(x)   (((x) << PAS_MAC_IPC_CHNL_DCHNO_S) & \
0192                      PAS_MAC_IPC_CHNL_DCHNO_M)
0193 #define PAS_MAC_IPC_CHNL_BCH_M      0x0000003f
0194 #define PAS_MAC_IPC_CHNL_BCH_S      0
0195 #define PAS_MAC_IPC_CHNL_BCH(x)     (((x) << PAS_MAC_IPC_CHNL_BCH_S) & \
0196                      PAS_MAC_IPC_CHNL_BCH_M)
0197
0198
0199 #endif /* PASEMI_MAC_H */