oki-semi/pch_gbe/pch_gbe.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 1999 - 2010 Intel Corporation.
0004  * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
0005  *
0006  * This code was derived from the Intel e1000e Linux driver.
0007  */
0008
0009 #ifndef _PCH_GBE_H_
0010 #define _PCH_GBE_H_
0011
0012 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
0013
0014 #include <linux/mii.h>
0015 #include <linux/delay.h>
0016 #include <linux/pci.h>
0017 #include <linux/netdevice.h>
0018 #include <linux/etherdevice.h>
0019 #include <linux/ethtool.h>
0020 #include <linux/vmalloc.h>
0021 #include <net/ip.h>
0022 #include <net/tcp.h>
0023 #include <net/udp.h>
0024
0025 /**
0026  * pch_gbe_regs_mac_adr - Structure holding values of mac address registers
0027  * @high    Denotes the 1st to 4th byte from the initial of MAC address
0028  * @low     Denotes the 5th to 6th byte from the initial of MAC address
0029  */
0030 struct pch_gbe_regs_mac_adr {
0031     u32 high;
0032     u32 low;
0033 };
0034 /**
0035  * pch_udc_regs - Structure holding values of MAC registers
0036  */
0037 struct pch_gbe_regs {
0038     u32 INT_ST;
0039     u32 INT_EN;
0040     u32 MODE;
0041     u32 RESET;
0042     u32 TCPIP_ACC;
0043     u32 EX_LIST;
0044     u32 INT_ST_HOLD;
0045     u32 PHY_INT_CTRL;
0046     u32 MAC_RX_EN;
0047     u32 RX_FCTRL;
0048     u32 PAUSE_REQ;
0049     u32 RX_MODE;
0050     u32 TX_MODE;
0051     u32 RX_FIFO_ST;
0052     u32 TX_FIFO_ST;
0053     u32 TX_FID;
0054     u32 TX_RESULT;
0055     u32 PAUSE_PKT1;
0056     u32 PAUSE_PKT2;
0057     u32 PAUSE_PKT3;
0058     u32 PAUSE_PKT4;
0059     u32 PAUSE_PKT5;
0060     u32 reserve[2];
0061     struct pch_gbe_regs_mac_adr mac_adr[16];
0062     u32 ADDR_MASK;
0063     u32 MIIM;
0064     u32 MAC_ADDR_LOAD;
0065     u32 RGMII_ST;
0066     u32 RGMII_CTRL;
0067     u32 reserve3[3];
0068     u32 DMA_CTRL;
0069     u32 reserve4[3];
0070     u32 RX_DSC_BASE;
0071     u32 RX_DSC_SIZE;
0072     u32 RX_DSC_HW_P;
0073     u32 RX_DSC_HW_P_HLD;
0074     u32 RX_DSC_SW_P;
0075     u32 reserve5[3];
0076     u32 TX_DSC_BASE;
0077     u32 TX_DSC_SIZE;
0078     u32 TX_DSC_HW_P;
0079     u32 TX_DSC_HW_P_HLD;
0080     u32 TX_DSC_SW_P;
0081     u32 reserve6[3];
0082     u32 RX_DMA_ST;
0083     u32 TX_DMA_ST;
0084     u32 reserve7[2];
0085     u32 WOL_ST;
0086     u32 WOL_CTRL;
0087     u32 WOL_ADDR_MASK;
0088 };
0089
0090 /* Interrupt Status */
0091 /* Interrupt Status Hold */
0092 /* Interrupt Enable */
0093 #define PCH_GBE_INT_RX_DMA_CMPLT  0x00000001 /* Receive DMA Transfer Complete */
0094 #define PCH_GBE_INT_RX_VALID      0x00000002 /* MAC Normal Receive Complete */
0095 #define PCH_GBE_INT_RX_FRAME_ERR  0x00000004 /* Receive frame error */
0096 #define PCH_GBE_INT_RX_FIFO_ERR   0x00000008 /* Receive FIFO Overflow */
0097 #define PCH_GBE_INT_RX_DMA_ERR    0x00000010 /* Receive DMA Transfer Error */
0098 #define PCH_GBE_INT_RX_DSC_EMP    0x00000020 /* Receive Descriptor Empty */
0099 #define PCH_GBE_INT_TX_CMPLT      0x00000100 /* MAC Transmission Complete */
0100 #define PCH_GBE_INT_TX_DMA_CMPLT  0x00000200 /* DMA Transfer Complete */
0101 #define PCH_GBE_INT_TX_FIFO_ERR   0x00000400 /* Transmission FIFO underflow. */
0102 #define PCH_GBE_INT_TX_DMA_ERR    0x00000800 /* Transmission DMA Error */
0103 #define PCH_GBE_INT_PAUSE_CMPLT   0x00001000 /* Pause Transmission complete */
0104 #define PCH_GBE_INT_MIIM_CMPLT    0x00010000 /* MIIM I/F Read completion */
0105 #define PCH_GBE_INT_PHY_INT       0x00100000 /* Interruption from PHY */
0106 #define PCH_GBE_INT_WOL_DET       0x01000000 /* Wake On LAN Event detection. */
0107 #define PCH_GBE_INT_TCPIP_ERR     0x10000000 /* TCP/IP Accelerator Error */
0108
0109 /* Mode */
0110 #define PCH_GBE_MODE_MII_ETHER      0x00000000  /* GIGA Ethernet Mode [MII] */
0111 #define PCH_GBE_MODE_GMII_ETHER     0x80000000  /* GIGA Ethernet Mode [GMII] */
0112 #define PCH_GBE_MODE_HALF_DUPLEX    0x00000000  /* Duplex Mode [half duplex] */
0113 #define PCH_GBE_MODE_FULL_DUPLEX    0x40000000  /* Duplex Mode [full duplex] */
0114 #define PCH_GBE_MODE_FR_BST         0x04000000  /* Frame bursting is done */
0115
0116 /* Reset */
0117 #define PCH_GBE_ALL_RST         0x80000000  /* All reset */
0118 #define PCH_GBE_TX_RST          0x00008000  /* TX MAC, TX FIFO, TX DMA reset */
0119 #define PCH_GBE_RX_RST          0x00004000  /* RX MAC, RX FIFO, RX DMA reset */
0120
0121 /* TCP/IP Accelerator Control */
0122 #define PCH_GBE_EX_LIST_EN      0x00000008  /* External List Enable */
0123 #define PCH_GBE_RX_TCPIPACC_OFF 0x00000004  /* RX TCP/IP ACC Disabled */
0124 #define PCH_GBE_TX_TCPIPACC_EN  0x00000002  /* TX TCP/IP ACC Enable */
0125 #define PCH_GBE_RX_TCPIPACC_EN  0x00000001  /* RX TCP/IP ACC Enable */
0126
0127 /* MAC RX Enable */
0128 #define PCH_GBE_MRE_MAC_RX_EN   0x00000001      /* MAC Receive Enable */
0129
0130 /* RX Flow Control */
0131 #define PCH_GBE_FL_CTRL_EN      0x80000000  /* Pause packet is enabled */
0132
0133 /* Pause Packet Request */
0134 #define PCH_GBE_PS_PKT_RQ       0x80000000  /* Pause packet Request */
0135
0136 /* RX Mode */
0137 #define PCH_GBE_ADD_FIL_EN      0x80000000  /* Address Filtering Enable */
0138 /* Multicast Filtering Enable */
0139 #define PCH_GBE_MLT_FIL_EN      0x40000000
0140 /* Receive Almost Empty Threshold */
0141 #define PCH_GBE_RH_ALM_EMP_4    0x00000000      /* 4 words */
0142 #define PCH_GBE_RH_ALM_EMP_8    0x00004000      /* 8 words */
0143 #define PCH_GBE_RH_ALM_EMP_16   0x00008000      /* 16 words */
0144 #define PCH_GBE_RH_ALM_EMP_32   0x0000C000      /* 32 words */
0145 /* Receive Almost Full Threshold */
0146 #define PCH_GBE_RH_ALM_FULL_4   0x00000000      /* 4 words */
0147 #define PCH_GBE_RH_ALM_FULL_8   0x00001000      /* 8 words */
0148 #define PCH_GBE_RH_ALM_FULL_16  0x00002000      /* 16 words */
0149 #define PCH_GBE_RH_ALM_FULL_32  0x00003000      /* 32 words */
0150 /* RX FIFO Read Trigger Threshold */
0151 #define PCH_GBE_RH_RD_TRG_4     0x00000000      /* 4 words */
0152 #define PCH_GBE_RH_RD_TRG_8     0x00000200      /* 8 words */
0153 #define PCH_GBE_RH_RD_TRG_16    0x00000400      /* 16 words */
0154 #define PCH_GBE_RH_RD_TRG_32    0x00000600      /* 32 words */
0155 #define PCH_GBE_RH_RD_TRG_64    0x00000800      /* 64 words */
0156 #define PCH_GBE_RH_RD_TRG_128   0x00000A00      /* 128 words */
0157 #define PCH_GBE_RH_RD_TRG_256   0x00000C00      /* 256 words */
0158 #define PCH_GBE_RH_RD_TRG_512   0x00000E00      /* 512 words */
0159
0160 /* Receive Descriptor bit definitions */
0161 #define PCH_GBE_RXD_ACC_STAT_BCAST          0x00000400
0162 #define PCH_GBE_RXD_ACC_STAT_MCAST          0x00000200
0163 #define PCH_GBE_RXD_ACC_STAT_UCAST          0x00000100
0164 #define PCH_GBE_RXD_ACC_STAT_TCPIPOK        0x000000C0
0165 #define PCH_GBE_RXD_ACC_STAT_IPOK           0x00000080
0166 #define PCH_GBE_RXD_ACC_STAT_TCPOK          0x00000040
0167 #define PCH_GBE_RXD_ACC_STAT_IP6ERR         0x00000020
0168 #define PCH_GBE_RXD_ACC_STAT_OFLIST         0x00000010
0169 #define PCH_GBE_RXD_ACC_STAT_TYPEIP         0x00000008
0170 #define PCH_GBE_RXD_ACC_STAT_MACL           0x00000004
0171 #define PCH_GBE_RXD_ACC_STAT_PPPOE          0x00000002
0172 #define PCH_GBE_RXD_ACC_STAT_VTAGT          0x00000001
0173 #define PCH_GBE_RXD_GMAC_STAT_PAUSE         0x0200
0174 #define PCH_GBE_RXD_GMAC_STAT_MARBR         0x0100
0175 #define PCH_GBE_RXD_GMAC_STAT_MARMLT        0x0080
0176 #define PCH_GBE_RXD_GMAC_STAT_MARIND        0x0040
0177 #define PCH_GBE_RXD_GMAC_STAT_MARNOTMT      0x0020
0178 #define PCH_GBE_RXD_GMAC_STAT_TLONG         0x0010
0179 #define PCH_GBE_RXD_GMAC_STAT_TSHRT         0x0008
0180 #define PCH_GBE_RXD_GMAC_STAT_NOTOCTAL      0x0004
0181 #define PCH_GBE_RXD_GMAC_STAT_NBLERR        0x0002
0182 #define PCH_GBE_RXD_GMAC_STAT_CRCERR        0x0001
0183
0184 /* Transmit Descriptor bit definitions */
0185 #define PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF      0x0008
0186 #define PCH_GBE_TXD_CTRL_ITAG               0x0004
0187 #define PCH_GBE_TXD_CTRL_ICRC               0x0002
0188 #define PCH_GBE_TXD_CTRL_APAD               0x0001
0189 #define PCH_GBE_TXD_WORDS_SHIFT             2
0190 #define PCH_GBE_TXD_GMAC_STAT_CMPLT         0x2000
0191 #define PCH_GBE_TXD_GMAC_STAT_ABT           0x1000
0192 #define PCH_GBE_TXD_GMAC_STAT_EXCOL         0x0800
0193 #define PCH_GBE_TXD_GMAC_STAT_SNGCOL        0x0400
0194 #define PCH_GBE_TXD_GMAC_STAT_MLTCOL        0x0200
0195 #define PCH_GBE_TXD_GMAC_STAT_CRSER         0x0100
0196 #define PCH_GBE_TXD_GMAC_STAT_TLNG          0x0080
0197 #define PCH_GBE_TXD_GMAC_STAT_TSHRT         0x0040
0198 #define PCH_GBE_TXD_GMAC_STAT_LTCOL         0x0020
0199 #define PCH_GBE_TXD_GMAC_STAT_TFUNDFLW      0x0010
0200 #define PCH_GBE_TXD_GMAC_STAT_RTYCNT_MASK   0x000F
0201
0202 /* TX Mode */
0203 #define PCH_GBE_TM_NO_RTRY     0x80000000 /* No Retransmission */
0204 #define PCH_GBE_TM_LONG_PKT    0x40000000 /* Long Packt TX Enable */
0205 #define PCH_GBE_TM_ST_AND_FD   0x20000000 /* Stare and Forward */
0206 #define PCH_GBE_TM_SHORT_PKT   0x10000000 /* Short Packet TX Enable */
0207 #define PCH_GBE_TM_LTCOL_RETX  0x08000000 /* Retransmission at Late Collision */
0208 /* Frame Start Threshold */
0209 #define PCH_GBE_TM_TH_TX_STRT_4    0x00000000    /* 4 words */
0210 #define PCH_GBE_TM_TH_TX_STRT_8    0x00004000    /* 8 words */
0211 #define PCH_GBE_TM_TH_TX_STRT_16   0x00008000    /* 16 words */
0212 #define PCH_GBE_TM_TH_TX_STRT_32   0x0000C000    /* 32 words */
0213 /* Transmit Almost Empty Threshold */
0214 #define PCH_GBE_TM_TH_ALM_EMP_4    0x00000000    /* 4 words */
0215 #define PCH_GBE_TM_TH_ALM_EMP_8    0x00000800    /* 8 words */
0216 #define PCH_GBE_TM_TH_ALM_EMP_16   0x00001000    /* 16 words */
0217 #define PCH_GBE_TM_TH_ALM_EMP_32   0x00001800    /* 32 words */
0218 #define PCH_GBE_TM_TH_ALM_EMP_64   0x00002000    /* 64 words */
0219 #define PCH_GBE_TM_TH_ALM_EMP_128  0x00002800    /* 128 words */
0220 #define PCH_GBE_TM_TH_ALM_EMP_256  0x00003000    /* 256 words */
0221 #define PCH_GBE_TM_TH_ALM_EMP_512  0x00003800    /* 512 words */
0222 /* Transmit Almost Full Threshold */
0223 #define PCH_GBE_TM_TH_ALM_FULL_4   0x00000000    /* 4 words */
0224 #define PCH_GBE_TM_TH_ALM_FULL_8   0x00000200    /* 8 words */
0225 #define PCH_GBE_TM_TH_ALM_FULL_16  0x00000400    /* 16 words */
0226 #define PCH_GBE_TM_TH_ALM_FULL_32  0x00000600    /* 32 words */
0227
0228 /* RX FIFO Status */
0229 #define PCH_GBE_RF_ALM_FULL     0x80000000  /* RX FIFO is almost full. */
0230 #define PCH_GBE_RF_ALM_EMP      0x40000000  /* RX FIFO is almost empty. */
0231 #define PCH_GBE_RF_RD_TRG       0x20000000  /* Become more than RH_RD_TRG. */
0232 #define PCH_GBE_RF_STRWD        0x1FFE0000  /* The word count of RX FIFO. */
0233 #define PCH_GBE_RF_RCVING       0x00010000  /* Stored in RX FIFO. */
0234
0235 /* MAC Address Mask */
0236 #define PCH_GBE_BUSY                0x80000000
0237
0238 /* MIIM  */
0239 #define PCH_GBE_MIIM_OPER_WRITE     0x04000000
0240 #define PCH_GBE_MIIM_OPER_READ      0x00000000
0241 #define PCH_GBE_MIIM_OPER_READY     0x04000000
0242 #define PCH_GBE_MIIM_PHY_ADDR_SHIFT 21
0243 #define PCH_GBE_MIIM_REG_ADDR_SHIFT 16
0244
0245 /* RGMII Status */
0246 #define PCH_GBE_LINK_UP             0x80000008
0247 #define PCH_GBE_RXC_SPEED_MSK       0x00000006
0248 #define PCH_GBE_RXC_SPEED_2_5M      0x00000000    /* 2.5MHz */
0249 #define PCH_GBE_RXC_SPEED_25M       0x00000002    /* 25MHz  */
0250 #define PCH_GBE_RXC_SPEED_125M      0x00000004    /* 100MHz */
0251 #define PCH_GBE_DUPLEX_FULL         0x00000001
0252
0253 /* RGMII Control */
0254 #define PCH_GBE_CRS_SEL             0x00000010
0255 #define PCH_GBE_RGMII_RATE_125M     0x00000000
0256 #define PCH_GBE_RGMII_RATE_25M      0x00000008
0257 #define PCH_GBE_RGMII_RATE_2_5M     0x0000000C
0258 #define PCH_GBE_RGMII_MODE_GMII     0x00000000
0259 #define PCH_GBE_RGMII_MODE_RGMII    0x00000002
0260 #define PCH_GBE_CHIP_TYPE_EXTERNAL  0x00000000
0261 #define PCH_GBE_CHIP_TYPE_INTERNAL  0x00000001
0262
0263 /* DMA Control */
0264 #define PCH_GBE_RX_DMA_EN       0x00000002   /* Enables Receive DMA */
0265 #define PCH_GBE_TX_DMA_EN       0x00000001   /* Enables Transmission DMA */
0266
0267 /* RX DMA STATUS */
0268 #define PCH_GBE_IDLE_CHECK       0xFFFFFFFE
0269
0270 /* Wake On LAN Status */
0271 #define PCH_GBE_WLS_BR          0x00000008 /* Broadcas Address */
0272 #define PCH_GBE_WLS_MLT         0x00000004 /* Multicast Address */
0273
0274 /* The Frame registered in Address Recognizer */
0275 #define PCH_GBE_WLS_IND         0x00000002
0276 #define PCH_GBE_WLS_MP          0x00000001 /* Magic packet Address */
0277
0278 /* Wake On LAN Control */
0279 #define PCH_GBE_WLC_WOL_MODE    0x00010000
0280 #define PCH_GBE_WLC_IGN_TLONG   0x00000100
0281 #define PCH_GBE_WLC_IGN_TSHRT   0x00000080
0282 #define PCH_GBE_WLC_IGN_OCTER   0x00000040
0283 #define PCH_GBE_WLC_IGN_NBLER   0x00000020
0284 #define PCH_GBE_WLC_IGN_CRCER   0x00000010
0285 #define PCH_GBE_WLC_BR          0x00000008
0286 #define PCH_GBE_WLC_MLT         0x00000004
0287 #define PCH_GBE_WLC_IND         0x00000002
0288 #define PCH_GBE_WLC_MP          0x00000001
0289
0290 /* Wake On LAN Address Mask */
0291 #define PCH_GBE_WLA_BUSY        0x80000000
0292
0293
0294
0295 /* TX/RX descriptor defines */
0296 #define PCH_GBE_MAX_TXD                     4096
0297 #define PCH_GBE_DEFAULT_TXD                  256
0298 #define PCH_GBE_MIN_TXD                        8
0299 #define PCH_GBE_MAX_RXD                     4096
0300 #define PCH_GBE_DEFAULT_RXD                  256
0301 #define PCH_GBE_MIN_RXD                        8
0302
0303 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */
0304 #define PCH_GBE_TX_DESC_MULTIPLE               8
0305 #define PCH_GBE_RX_DESC_MULTIPLE               8
0306
0307 /* Read/Write operation is done through MII Management IF */
0308 #define PCH_GBE_HAL_MIIM_READ          ((u32)0x00000000)
0309 #define PCH_GBE_HAL_MIIM_WRITE         ((u32)0x04000000)
0310
0311 /* flow control values */
0312 #define PCH_GBE_FC_NONE         0
0313 #define PCH_GBE_FC_RX_PAUSE     1
0314 #define PCH_GBE_FC_TX_PAUSE     2
0315 #define PCH_GBE_FC_FULL         3
0316 #define PCH_GBE_FC_DEFAULT      PCH_GBE_FC_FULL
0317
0318 /**
0319  * struct pch_gbe_mac_info - MAC information
0320  * @addr[6]:        Store the MAC address
0321  * @fc:         Mode of flow control
0322  * @fc_autoneg:     Auto negotiation enable for flow control setting
0323  * @tx_fc_enable:   Enable flag of Transmit flow control
0324  * @max_frame_size: Max transmit frame size
0325  * @min_frame_size: Min transmit frame size
0326  * @autoneg:        Auto negotiation enable
0327  * @link_speed:     Link speed
0328  * @link_duplex:    Link duplex
0329  */
0330 struct pch_gbe_mac_info {
0331     u8 addr[6];
0332     u8 fc;
0333     u8 fc_autoneg;
0334     u8 tx_fc_enable;
0335     u32 max_frame_size;
0336     u32 min_frame_size;
0337     u8 autoneg;
0338     u16 link_speed;
0339     u16 link_duplex;
0340 };
0341
0342 /**
0343  * struct pch_gbe_phy_info - PHY information
0344  * @addr:       PHY address
0345  * @id:         PHY's identifier
0346  * @revision:       PHY's revision
0347  * @reset_delay_us: HW reset delay time[us]
0348  * @autoneg_advertised: Autoneg advertised
0349  */
0350 struct pch_gbe_phy_info {
0351     u32 addr;
0352     u32 id;
0353     u32 revision;
0354     u32 reset_delay_us;
0355     u16 autoneg_advertised;
0356 };
0357
0358 /*!
0359  * @ingroup Gigabit Ether driver Layer
0360  * @struct  pch_gbe_hw
0361  * @brief   Hardware information
0362  */
0363 struct pch_gbe_hw {
0364     void *back;
0365
0366     struct pch_gbe_regs  __iomem *reg;
0367     spinlock_t miim_lock;
0368
0369     struct pch_gbe_mac_info mac;
0370     struct pch_gbe_phy_info phy;
0371 };
0372
0373 /**
0374  * struct pch_gbe_rx_desc - Receive Descriptor
0375  * @buffer_addr:    RX Frame Buffer Address
0376  * @tcp_ip_status:  TCP/IP Accelerator Status
0377  * @rx_words_eob:   RX word count and Byte position
0378  * @gbec_status:    GMAC Status
0379  * @dma_status:     DMA Status
0380  * @reserved1:      Reserved
0381  * @reserved2:      Reserved
0382  */
0383 struct pch_gbe_rx_desc {
0384     u32 buffer_addr;
0385     u32 tcp_ip_status;
0386     u16 rx_words_eob;
0387     u16 gbec_status;
0388     u8 dma_status;
0389     u8 reserved1;
0390     u16 reserved2;
0391 };
0392
0393 /**
0394  * struct pch_gbe_tx_desc - Transmit Descriptor
0395  * @buffer_addr:    TX Frame Buffer Address
0396  * @length:     Data buffer length
0397  * @reserved1:      Reserved
0398  * @tx_words_eob:   TX word count and Byte position
0399  * @tx_frame_ctrl:  TX Frame Control
0400  * @dma_status:     DMA Status
0401  * @reserved2:      Reserved
0402  * @gbec_status:    GMAC Status
0403  */
0404 struct pch_gbe_tx_desc {
0405     u32 buffer_addr;
0406     u16 length;
0407     u16 reserved1;
0408     u16 tx_words_eob;
0409     u16 tx_frame_ctrl;
0410     u8 dma_status;
0411     u8 reserved2;
0412     u16 gbec_status;
0413 };
0414
0415
0416 /**
0417  * struct pch_gbe_buffer - Buffer information
0418  * @skb:    pointer to a socket buffer
0419  * @dma:    DMA address
0420  * @time_stamp: time stamp
0421  * @length: data size
0422  */
0423 struct pch_gbe_buffer {
0424     struct sk_buff *skb;
0425     dma_addr_t dma;
0426     unsigned char *rx_buffer;
0427     unsigned long time_stamp;
0428     u16 length;
0429     bool mapped;
0430 };
0431
0432 /**
0433  * struct pch_gbe_tx_ring - tx ring information
0434  * @desc:   pointer to the descriptor ring memory
0435  * @dma:    physical address of the descriptor ring
0436  * @size:   length of descriptor ring in bytes
0437  * @count:  number of descriptors in the ring
0438  * @next_to_use:    next descriptor to associate a buffer with
0439  * @next_to_clean:  next descriptor to check for DD status bit
0440  * @buffer_info:    array of buffer information structs
0441  */
0442 struct pch_gbe_tx_ring {
0443     struct pch_gbe_tx_desc *desc;
0444     dma_addr_t dma;
0445     unsigned int size;
0446     unsigned int count;
0447     unsigned int next_to_use;
0448     unsigned int next_to_clean;
0449     struct pch_gbe_buffer *buffer_info;
0450 };
0451
0452 /**
0453  * struct pch_gbe_rx_ring - rx ring information
0454  * @desc:   pointer to the descriptor ring memory
0455  * @dma:    physical address of the descriptor ring
0456  * @size:   length of descriptor ring in bytes
0457  * @count:  number of descriptors in the ring
0458  * @next_to_use:    next descriptor to associate a buffer with
0459  * @next_to_clean:  next descriptor to check for DD status bit
0460  * @buffer_info:    array of buffer information structs
0461  */
0462 struct pch_gbe_rx_ring {
0463     struct pch_gbe_rx_desc *desc;
0464     dma_addr_t dma;
0465     unsigned char *rx_buff_pool;
0466     dma_addr_t rx_buff_pool_logic;
0467     unsigned int rx_buff_pool_size;
0468     unsigned int size;
0469     unsigned int count;
0470     unsigned int next_to_use;
0471     unsigned int next_to_clean;
0472     struct pch_gbe_buffer *buffer_info;
0473 };
0474
0475 /**
0476  * struct pch_gbe_hw_stats - Statistics counters collected by the MAC
0477  * @rx_packets:         total packets received
0478  * @tx_packets:         total packets transmitted
0479  * @rx_bytes:           total bytes received
0480  * @tx_bytes:           total bytes transmitted
0481  * @rx_errors:          bad packets received
0482  * @tx_errors:          packet transmit problems
0483  * @rx_dropped:         no space in Linux buffers
0484  * @tx_dropped:         no space available in Linux
0485  * @multicast:          multicast packets received
0486  * @collisions:         collisions
0487  * @rx_crc_errors:      received packet with crc error
0488  * @rx_frame_errors:        received frame alignment error
0489  * @rx_alloc_buff_failed:   allocate failure of a receive buffer
0490  * @tx_length_errors:       transmit length error
0491  * @tx_aborted_errors:      transmit aborted error
0492  * @tx_carrier_errors:      transmit carrier error
0493  * @tx_timeout_count:       Number of transmit timeout
0494  * @tx_restart_count:       Number of transmit restert
0495  * @intr_rx_dsc_empty_count:    Interrupt count of receive descriptor empty
0496  * @intr_rx_frame_err_count:    Interrupt count of receive frame error
0497  * @intr_rx_fifo_err_count: Interrupt count of receive FIFO error
0498  * @intr_rx_dma_err_count:  Interrupt count of receive DMA error
0499  * @intr_tx_fifo_err_count: Interrupt count of transmit FIFO error
0500  * @intr_tx_dma_err_count:  Interrupt count of transmit DMA error
0501  * @intr_tcpip_err_count:   Interrupt count of TCP/IP Accelerator
0502  */
0503 struct pch_gbe_hw_stats {
0504     u32 rx_packets;
0505     u32 tx_packets;
0506     u32 rx_bytes;
0507     u32 tx_bytes;
0508     u32 rx_errors;
0509     u32 tx_errors;
0510     u32 rx_dropped;
0511     u32 tx_dropped;
0512     u32 multicast;
0513     u32 collisions;
0514     u32 rx_crc_errors;
0515     u32 rx_frame_errors;
0516     u32 rx_alloc_buff_failed;
0517     u32 tx_length_errors;
0518     u32 tx_aborted_errors;
0519     u32 tx_carrier_errors;
0520     u32 tx_timeout_count;
0521     u32 tx_restart_count;
0522     u32 intr_rx_dsc_empty_count;
0523     u32 intr_rx_frame_err_count;
0524     u32 intr_rx_fifo_err_count;
0525     u32 intr_rx_dma_err_count;
0526     u32 intr_tx_fifo_err_count;
0527     u32 intr_tx_dma_err_count;
0528     u32 intr_tcpip_err_count;
0529 };
0530
0531 /**
0532  * struct pch_gbe_privdata - PCI Device ID driver data
0533  * @phy_tx_clk_delay:       Bool, configure the PHY TX delay in software
0534  * @phy_disable_hibernate:  Bool, disable PHY hibernation
0535  * @platform_init:      Platform initialization callback, called from
0536  *              probe, prior to PHY initialization.
0537  */
0538 struct pch_gbe_privdata {
0539     bool phy_tx_clk_delay;
0540     bool phy_disable_hibernate;
0541     int (*platform_init)(struct pci_dev *pdev);
0542 };
0543
0544 /**
0545  * struct pch_gbe_adapter - board specific private data structure
0546  * @stats_lock: Spinlock structure for status
0547  * @ethtool_lock:   Spinlock structure for ethtool
0548  * @irq_sem:        Semaphore for interrupt
0549  * @netdev:     Pointer of network device structure
0550  * @pdev:       Pointer of pci device structure
0551  * @polling_netdev: Pointer of polling network device structure
0552  * @napi:       NAPI structure
0553  * @hw:         Pointer of hardware structure
0554  * @stats:      Hardware status
0555  * @reset_task:     Reset task
0556  * @mii:        MII information structure
0557  * @watchdog_timer: Watchdog timer list
0558  * @wake_up_evt:    Wake up event
0559  * @config_space:   Configuration space
0560  * @msg_enable:     Driver message level
0561  * @led_status:     LED status
0562  * @tx_ring:        Pointer of Tx descriptor ring structure
0563  * @rx_ring:        Pointer of Rx descriptor ring structure
0564  * @rx_buffer_len:  Receive buffer length
0565  * @tx_queue_len:   Transmit queue length
0566  * @pch_gbe_privdata:   PCI Device ID driver_data
0567  */
0568
0569 struct pch_gbe_adapter {
0570     spinlock_t stats_lock;
0571     spinlock_t ethtool_lock;
0572     atomic_t irq_sem;
0573     struct net_device *netdev;
0574     struct pci_dev *pdev;
0575     int irq;
0576     struct net_device *polling_netdev;
0577     struct napi_struct napi;
0578     struct pch_gbe_hw hw;
0579     struct pch_gbe_hw_stats stats;
0580     struct work_struct reset_task;
0581     struct mii_if_info mii;
0582     struct timer_list watchdog_timer;
0583     u32 wake_up_evt;
0584     u32 *config_space;
0585     unsigned long led_status;
0586     struct pch_gbe_tx_ring *tx_ring;
0587     struct pch_gbe_rx_ring *rx_ring;
0588     unsigned long rx_buffer_len;
0589     unsigned long tx_queue_len;
0590     bool rx_stop_flag;
0591     int hwts_tx_en;
0592     int hwts_rx_en;
0593     struct pci_dev *ptp_pdev;
0594     struct pch_gbe_privdata *pdata;
0595 };
0596
0597 #define pch_gbe_hw_to_adapter(hw)   container_of(hw, struct pch_gbe_adapter, hw)
0598
0599 /* pch_gbe_main.c */
0600 int pch_gbe_up(struct pch_gbe_adapter *adapter);
0601 void pch_gbe_down(struct pch_gbe_adapter *adapter);
0602 void pch_gbe_reinit_locked(struct pch_gbe_adapter *adapter);
0603 void pch_gbe_reset(struct pch_gbe_adapter *adapter);
0604 int pch_gbe_setup_tx_resources(struct pch_gbe_adapter *adapter,
0605                    struct pch_gbe_tx_ring *txdr);
0606 int pch_gbe_setup_rx_resources(struct pch_gbe_adapter *adapter,
0607                    struct pch_gbe_rx_ring *rxdr);
0608 void pch_gbe_free_tx_resources(struct pch_gbe_adapter *adapter,
0609                    struct pch_gbe_tx_ring *tx_ring);
0610 void pch_gbe_free_rx_resources(struct pch_gbe_adapter *adapter,
0611                    struct pch_gbe_rx_ring *rx_ring);
0612 void pch_gbe_update_stats(struct pch_gbe_adapter *adapter);
0613
0614 /* pch_gbe_param.c */
0615 void pch_gbe_check_options(struct pch_gbe_adapter *adapter);
0616
0617 /* pch_gbe_ethtool.c */
0618 void pch_gbe_set_ethtool_ops(struct net_device *netdev);
0619
0620 /* pch_gbe_mac.c */
0621 s32 pch_gbe_mac_force_mac_fc(struct pch_gbe_hw *hw);
0622 u16 pch_gbe_mac_ctrl_miim(struct pch_gbe_hw *hw, u32 addr, u32 dir, u32 reg,
0623               u16 data);
0624 #endif /* _PCH_GBE_H_ */