nfp/nfpcore/nfp_dev.c

0001 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 /* Copyright (C) 2019 Netronome Systems, Inc. */
0003
0004 #include <linux/dma-mapping.h>
0005 #include <linux/kernel.h>
0006 #include <linux/sizes.h>
0007
0008 #include "nfp_dev.h"
0009
0010 const struct nfp_dev_info nfp_dev_info[NFP_DEV_CNT] = {
0011     [NFP_DEV_NFP3800] = {
0012         .dma_mask       = DMA_BIT_MASK(48),
0013         .qc_idx_mask        = GENMASK(8, 0),
0014         .qc_addr_offset     = 0x400000,
0015         .min_qc_size        = 512,
0016         .max_qc_size        = SZ_64K,
0017
0018         .chip_names     = "NFP3800",
0019         .pcie_cfg_expbar_offset = 0x0a00,
0020         .pcie_expl_offset   = 0xd000,
0021         .qc_area_sz     = 0x100000,
0022     },
0023     [NFP_DEV_NFP3800_VF] = {
0024         .dma_mask       = DMA_BIT_MASK(48),
0025         .qc_idx_mask        = GENMASK(8, 0),
0026         .qc_addr_offset     = 0,
0027         .min_qc_size        = 512,
0028         .max_qc_size        = SZ_64K,
0029     },
0030     [NFP_DEV_NFP6000] = {
0031         .dma_mask       = DMA_BIT_MASK(40),
0032         .qc_idx_mask        = GENMASK(7, 0),
0033         .qc_addr_offset     = 0x80000,
0034         .min_qc_size        = 256,
0035         .max_qc_size        = SZ_256K,
0036
0037         .chip_names     = "NFP4000/NFP5000/NFP6000",
0038         .pcie_cfg_expbar_offset = 0x0400,
0039         .pcie_expl_offset   = 0x1000,
0040         .qc_area_sz     = 0x80000,
0041     },
0042     [NFP_DEV_NFP6000_VF] = {
0043         .dma_mask       = DMA_BIT_MASK(40),
0044         .qc_idx_mask        = GENMASK(7, 0),
0045         .qc_addr_offset     = 0,
0046         .min_qc_size        = 256,
0047         .max_qc_size        = SZ_256K,
0048     },
0049 };