nfp/nfpcore/nfp_arm.h

0001 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
0002 /* Copyright (C) 2015-2017 Netronome Systems, Inc. */
0003
0004 /*
0005  * nfp_arm.h
0006  * Definitions for ARM-based registers and memory spaces
0007  */
0008
0009 #ifndef NFP_ARM_H
0010 #define NFP_ARM_H
0011
0012 #define NFP_ARM_QUEUE(_q)              (0x100000 + (0x800 * ((_q) & 0xff)))
0013 #define NFP_ARM_IM                     0x200000
0014 #define NFP_ARM_EM                     0x300000
0015 #define NFP_ARM_GCSR                   0x400000
0016 #define NFP_ARM_MPCORE                 0x800000
0017 #define NFP_ARM_PL310                  0xa00000
0018 /* Register Type: BulkBARConfig */
0019 #define NFP_ARM_GCSR_BULK_BAR(_bar)    (0x0 + (0x4 * ((_bar) & 0x7)))
0020 #define   NFP_ARM_GCSR_BULK_BAR_TYPE                    (0x1 << 31)
0021 #define     NFP_ARM_GCSR_BULK_BAR_TYPE_BULK             (0x0)
0022 #define     NFP_ARM_GCSR_BULK_BAR_TYPE_EXPA             (0x80000000)
0023 #define   NFP_ARM_GCSR_BULK_BAR_TGT(_x)                 (((_x) & 0xf) << 27)
0024 #define   NFP_ARM_GCSR_BULK_BAR_TGT_of(_x)              (((_x) >> 27) & 0xf)
0025 #define   NFP_ARM_GCSR_BULK_BAR_TOK(_x)                 (((_x) & 0x3) << 25)
0026 #define   NFP_ARM_GCSR_BULK_BAR_TOK_of(_x)              (((_x) >> 25) & 0x3)
0027 #define   NFP_ARM_GCSR_BULK_BAR_LEN                     (0x1 << 24)
0028 #define     NFP_ARM_GCSR_BULK_BAR_LEN_32BIT             (0x0)
0029 #define     NFP_ARM_GCSR_BULK_BAR_LEN_64BIT             (0x1000000)
0030 #define   NFP_ARM_GCSR_BULK_BAR_ADDR(_x)                ((_x) & 0x7ff)
0031 #define   NFP_ARM_GCSR_BULK_BAR_ADDR_of(_x)             ((_x) & 0x7ff)
0032 /* Register Type: ExpansionBARConfig */
0033 #define NFP_ARM_GCSR_EXPA_BAR(_bar)    (0x20 + (0x4 * ((_bar) & 0xf)))
0034 #define   NFP_ARM_GCSR_EXPA_BAR_TYPE                    (0x1 << 31)
0035 #define     NFP_ARM_GCSR_EXPA_BAR_TYPE_EXPA             (0x0)
0036 #define     NFP_ARM_GCSR_EXPA_BAR_TYPE_EXPL             (0x80000000)
0037 #define   NFP_ARM_GCSR_EXPA_BAR_TGT(_x)                 (((_x) & 0xf) << 27)
0038 #define   NFP_ARM_GCSR_EXPA_BAR_TGT_of(_x)              (((_x) >> 27) & 0xf)
0039 #define   NFP_ARM_GCSR_EXPA_BAR_TOK(_x)                 (((_x) & 0x3) << 25)
0040 #define   NFP_ARM_GCSR_EXPA_BAR_TOK_of(_x)              (((_x) >> 25) & 0x3)
0041 #define   NFP_ARM_GCSR_EXPA_BAR_LEN                     (0x1 << 24)
0042 #define     NFP_ARM_GCSR_EXPA_BAR_LEN_32BIT             (0x0)
0043 #define     NFP_ARM_GCSR_EXPA_BAR_LEN_64BIT             (0x1000000)
0044 #define   NFP_ARM_GCSR_EXPA_BAR_ACT(_x)                 (((_x) & 0x1f) << 19)
0045 #define   NFP_ARM_GCSR_EXPA_BAR_ACT_of(_x)              (((_x) >> 19) & 0x1f)
0046 #define     NFP_ARM_GCSR_EXPA_BAR_ACT_DERIVED           (0)
0047 #define   NFP_ARM_GCSR_EXPA_BAR_ADDR(_x)                ((_x) & 0x7fff)
0048 #define   NFP_ARM_GCSR_EXPA_BAR_ADDR_of(_x)             ((_x) & 0x7fff)
0049 /* Register Type: ExplicitBARConfig0_Reg */
0050 #define NFP_ARM_GCSR_EXPL0_BAR(_bar)   (0x60 + (0x4 * ((_bar) & 0x7)))
0051 #define   NFP_ARM_GCSR_EXPL0_BAR_ADDR(_x)               ((_x) & 0x3ffff)
0052 #define   NFP_ARM_GCSR_EXPL0_BAR_ADDR_of(_x)            ((_x) & 0x3ffff)
0053 /* Register Type: ExplicitBARConfig1_Reg */
0054 #define NFP_ARM_GCSR_EXPL1_BAR(_bar)   (0x80 + (0x4 * ((_bar) & 0x7)))
0055 #define   NFP_ARM_GCSR_EXPL1_BAR_POSTED                 (0x1 << 31)
0056 #define   NFP_ARM_GCSR_EXPL1_BAR_SIGNAL_REF(_x)         (((_x) & 0x7f) << 24)
0057 #define   NFP_ARM_GCSR_EXPL1_BAR_SIGNAL_REF_of(_x)      (((_x) >> 24) & 0x7f)
0058 #define   NFP_ARM_GCSR_EXPL1_BAR_DATA_MASTER(_x)        (((_x) & 0xff) << 16)
0059 #define   NFP_ARM_GCSR_EXPL1_BAR_DATA_MASTER_of(_x)     (((_x) >> 16) & 0xff)
0060 #define   NFP_ARM_GCSR_EXPL1_BAR_DATA_REF(_x)           ((_x) & 0x3fff)
0061 #define   NFP_ARM_GCSR_EXPL1_BAR_DATA_REF_of(_x)        ((_x) & 0x3fff)
0062 /* Register Type: ExplicitBARConfig2_Reg */
0063 #define NFP_ARM_GCSR_EXPL2_BAR(_bar)   (0xa0 + (0x4 * ((_bar) & 0x7)))
0064 #define   NFP_ARM_GCSR_EXPL2_BAR_TGT(_x)                (((_x) & 0xf) << 28)
0065 #define   NFP_ARM_GCSR_EXPL2_BAR_TGT_of(_x)             (((_x) >> 28) & 0xf)
0066 #define   NFP_ARM_GCSR_EXPL2_BAR_ACT(_x)                (((_x) & 0x1f) << 23)
0067 #define   NFP_ARM_GCSR_EXPL2_BAR_ACT_of(_x)             (((_x) >> 23) & 0x1f)
0068 #define   NFP_ARM_GCSR_EXPL2_BAR_LEN(_x)                (((_x) & 0x1f) << 18)
0069 #define   NFP_ARM_GCSR_EXPL2_BAR_LEN_of(_x)             (((_x) >> 18) & 0x1f)
0070 #define   NFP_ARM_GCSR_EXPL2_BAR_BYTE_MASK(_x)          (((_x) & 0xff) << 10)
0071 #define   NFP_ARM_GCSR_EXPL2_BAR_BYTE_MASK_of(_x)       (((_x) >> 10) & 0xff)
0072 #define   NFP_ARM_GCSR_EXPL2_BAR_TOK(_x)                (((_x) & 0x3) << 8)
0073 #define   NFP_ARM_GCSR_EXPL2_BAR_TOK_of(_x)             (((_x) >> 8) & 0x3)
0074 #define   NFP_ARM_GCSR_EXPL2_BAR_SIGNAL_MASTER(_x)      ((_x) & 0xff)
0075 #define   NFP_ARM_GCSR_EXPL2_BAR_SIGNAL_MASTER_of(_x)   ((_x) & 0xff)
0076 /* Register Type: PostedCommandSignal */
0077 #define NFP_ARM_GCSR_EXPL_POST(_bar)   (0xc0 + (0x4 * ((_bar) & 0x7)))
0078 #define   NFP_ARM_GCSR_EXPL_POST_SIG_B(_x)              (((_x) & 0x7f) << 25)
0079 #define   NFP_ARM_GCSR_EXPL_POST_SIG_B_of(_x)           (((_x) >> 25) & 0x7f)
0080 #define   NFP_ARM_GCSR_EXPL_POST_SIG_B_BUS              (0x1 << 24)
0081 #define     NFP_ARM_GCSR_EXPL_POST_SIG_B_BUS_PULL       (0x0)
0082 #define     NFP_ARM_GCSR_EXPL_POST_SIG_B_BUS_PUSH       (0x1000000)
0083 #define   NFP_ARM_GCSR_EXPL_POST_SIG_A(_x)              (((_x) & 0x7f) << 17)
0084 #define   NFP_ARM_GCSR_EXPL_POST_SIG_A_of(_x)           (((_x) >> 17) & 0x7f)
0085 #define   NFP_ARM_GCSR_EXPL_POST_SIG_A_BUS              (0x1 << 16)
0086 #define     NFP_ARM_GCSR_EXPL_POST_SIG_A_BUS_PULL       (0x0)
0087 #define     NFP_ARM_GCSR_EXPL_POST_SIG_A_BUS_PUSH       (0x10000)
0088 #define   NFP_ARM_GCSR_EXPL_POST_SIG_B_RCVD             (0x1 << 7)
0089 #define   NFP_ARM_GCSR_EXPL_POST_SIG_B_VALID            (0x1 << 6)
0090 #define   NFP_ARM_GCSR_EXPL_POST_SIG_A_RCVD             (0x1 << 5)
0091 #define   NFP_ARM_GCSR_EXPL_POST_SIG_A_VALID            (0x1 << 4)
0092 #define   NFP_ARM_GCSR_EXPL_POST_CMD_COMPLETE           (0x1)
0093 /* Register Type: MPCoreBaseAddress */
0094 #define NFP_ARM_GCSR_MPCORE_BASE       0x00e0
0095 #define   NFP_ARM_GCSR_MPCORE_BASE_ADDR(_x)             (((_x) & 0x7ffff) << 13)
0096 #define   NFP_ARM_GCSR_MPCORE_BASE_ADDR_of(_x)          (((_x) >> 13) & 0x7ffff)
0097 /* Register Type: PL310BaseAddress */
0098 #define NFP_ARM_GCSR_PL310_BASE        0x00e4
0099 #define   NFP_ARM_GCSR_PL310_BASE_ADDR(_x)              (((_x) & 0xfffff) << 12)
0100 #define   NFP_ARM_GCSR_PL310_BASE_ADDR_of(_x)           (((_x) >> 12) & 0xfffff)
0101 /* Register Type: MPCoreConfig */
0102 #define NFP_ARM_GCSR_MP0_CFG           0x00e8
0103 #define   NFP_ARM_GCSR_MP0_CFG_SPI_BOOT                 (0x1 << 14)
0104 #define   NFP_ARM_GCSR_MP0_CFG_ENDIAN(_x)               (((_x) & 0x3) << 12)
0105 #define   NFP_ARM_GCSR_MP0_CFG_ENDIAN_of(_x)            (((_x) >> 12) & 0x3)
0106 #define     NFP_ARM_GCSR_MP0_CFG_ENDIAN_LITTLE          (0)
0107 #define     NFP_ARM_GCSR_MP0_CFG_ENDIAN_BIG             (1)
0108 #define   NFP_ARM_GCSR_MP0_CFG_RESET_VECTOR             (0x1 << 8)
0109 #define     NFP_ARM_GCSR_MP0_CFG_RESET_VECTOR_LO        (0x0)
0110 #define     NFP_ARM_GCSR_MP0_CFG_RESET_VECTOR_HI        (0x100)
0111 #define   NFP_ARM_GCSR_MP0_CFG_OUTCLK_EN(_x)            (((_x) & 0xf) << 4)
0112 #define   NFP_ARM_GCSR_MP0_CFG_OUTCLK_EN_of(_x)         (((_x) >> 4) & 0xf)
0113 #define   NFP_ARM_GCSR_MP0_CFG_ARMID(_x)                ((_x) & 0xf)
0114 #define   NFP_ARM_GCSR_MP0_CFG_ARMID_of(_x)             ((_x) & 0xf)
0115 /* Register Type: MPCoreIDCacheDataError */
0116 #define NFP_ARM_GCSR_MP0_CACHE_ERR     0x00ec
0117 #define   NFP_ARM_GCSR_MP0_CACHE_ERR_MP0_D7             (0x1 << 15)
0118 #define   NFP_ARM_GCSR_MP0_CACHE_ERR_MP0_D6             (0x1 << 14)
0119 #define   NFP_ARM_GCSR_MP0_CACHE_ERR_MP0_D5             (0x1 << 13)
0120 #define   NFP_ARM_GCSR_MP0_CACHE_ERR_MP0_D4             (0x1 << 12)
0121 #define   NFP_ARM_GCSR_MP0_CACHE_ERR_MP0_D3             (0x1 << 11)
0122 #define   NFP_ARM_GCSR_MP0_CACHE_ERR_MP0_D2             (0x1 << 10)
0123 #define   NFP_ARM_GCSR_MP0_CACHE_ERR_MP0_D1             (0x1 << 9)
0124 #define   NFP_ARM_GCSR_MP0_CACHE_ERR_MP0_D0             (0x1 << 8)
0125 #define   NFP_ARM_GCSR_MP0_CACHE_ERR_MP0_I7             (0x1 << 7)
0126 #define   NFP_ARM_GCSR_MP0_CACHE_ERR_MP0_I6             (0x1 << 6)
0127 #define   NFP_ARM_GCSR_MP0_CACHE_ERR_MP0_I5             (0x1 << 5)
0128 #define   NFP_ARM_GCSR_MP0_CACHE_ERR_MP0_I4             (0x1 << 4)
0129 #define   NFP_ARM_GCSR_MP0_CACHE_ERR_MP0_I3             (0x1 << 3)
0130 #define   NFP_ARM_GCSR_MP0_CACHE_ERR_MP0_I2             (0x1 << 2)
0131 #define   NFP_ARM_GCSR_MP0_CACHE_ERR_MP0_I1             (0x1 << 1)
0132 #define   NFP_ARM_GCSR_MP0_CACHE_ERR_MP0_I0             (0x1)
0133 /* Register Type: ARMDFT */
0134 #define NFP_ARM_GCSR_DFT               0x0100
0135 #define   NFP_ARM_GCSR_DFT_DBG_REQ                      (0x1 << 20)
0136 #define   NFP_ARM_GCSR_DFT_DBG_EN                       (0x1 << 19)
0137 #define   NFP_ARM_GCSR_DFT_WFE_EVT_TRG                  (0x1 << 18)
0138 #define   NFP_ARM_GCSR_DFT_ETM_WFI_RDY                  (0x1 << 17)
0139 #define   NFP_ARM_GCSR_DFT_ETM_PWR_ON                   (0x1 << 16)
0140 #define   NFP_ARM_GCSR_DFT_BIST_FAIL_of(_x)             (((_x) >> 8) & 0xf)
0141 #define   NFP_ARM_GCSR_DFT_BIST_DONE_of(_x)             (((_x) >> 4) & 0xf)
0142 #define   NFP_ARM_GCSR_DFT_BIST_RUN(_x)                 ((_x) & 0x7)
0143 #define   NFP_ARM_GCSR_DFT_BIST_RUN_of(_x)              ((_x) & 0x7)
0144
0145 /* Gasket CSRs */
0146 /* NOTE: These cannot be remapped, and are always at this location.
0147  */
0148 #define NFP_ARM_GCSR_START  (0xd6000000 + NFP_ARM_GCSR)
0149 #define NFP_ARM_GCSR_SIZE   SZ_64K
0150
0151 /* BAR CSRs
0152  */
0153 #define NFP_ARM_GCSR_BULK_BITS  11
0154 #define NFP_ARM_GCSR_EXPA_BITS  15
0155 #define NFP_ARM_GCSR_EXPL_BITS  18
0156
0157 #define NFP_ARM_GCSR_BULK_SHIFT (40 - 11)
0158 #define NFP_ARM_GCSR_EXPA_SHIFT (40 - 15)
0159 #define NFP_ARM_GCSR_EXPL_SHIFT (40 - 18)
0160
0161 #define NFP_ARM_GCSR_BULK_SIZE  (1 << NFP_ARM_GCSR_BULK_SHIFT)
0162 #define NFP_ARM_GCSR_EXPA_SIZE  (1 << NFP_ARM_GCSR_EXPA_SHIFT)
0163 #define NFP_ARM_GCSR_EXPL_SIZE  (1 << NFP_ARM_GCSR_EXPL_SHIFT)
0164
0165 #define NFP_ARM_GCSR_EXPL2_CSR(target, action, length, \
0166                    byte_mask, token, signal_master) \
0167     (NFP_ARM_GCSR_EXPL2_BAR_TGT(target) | \
0168      NFP_ARM_GCSR_EXPL2_BAR_ACT(action) | \
0169      NFP_ARM_GCSR_EXPL2_BAR_LEN(length) | \
0170      NFP_ARM_GCSR_EXPL2_BAR_BYTE_MASK(byte_mask) | \
0171      NFP_ARM_GCSR_EXPL2_BAR_TOK(token) | \
0172      NFP_ARM_GCSR_EXPL2_BAR_SIGNAL_MASTER(signal_master))
0173 #define NFP_ARM_GCSR_EXPL1_CSR(posted, signal_ref, data_master, data_ref) \
0174     (((posted) ? NFP_ARM_GCSR_EXPL1_BAR_POSTED : 0) | \
0175      NFP_ARM_GCSR_EXPL1_BAR_SIGNAL_REF(signal_ref) | \
0176      NFP_ARM_GCSR_EXPL1_BAR_DATA_MASTER(data_master) | \
0177      NFP_ARM_GCSR_EXPL1_BAR_DATA_REF(data_ref))
0178 #define NFP_ARM_GCSR_EXPL0_CSR(address) \
0179     NFP_ARM_GCSR_EXPL0_BAR_ADDR((address) >> NFP_ARM_GCSR_EXPL_SHIFT)
0180 #define NFP_ARM_GCSR_EXPL_POST_EXPECT_A(sig_ref, is_push, is_required) \
0181     (NFP_ARM_GCSR_EXPL_POST_SIG_A(sig_ref) | \
0182      ((is_push) ? NFP_ARM_GCSR_EXPL_POST_SIG_A_BUS_PUSH : \
0183               NFP_ARM_GCSR_EXPL_POST_SIG_A_BUS_PULL) | \
0184      ((is_required) ? NFP_ARM_GCSR_EXPL_POST_SIG_A_VALID : 0))
0185 #define NFP_ARM_GCSR_EXPL_POST_EXPECT_B(sig_ref, is_push, is_required) \
0186     (NFP_ARM_GCSR_EXPL_POST_SIG_B(sig_ref) | \
0187      ((is_push) ? NFP_ARM_GCSR_EXPL_POST_SIG_B_BUS_PUSH : \
0188               NFP_ARM_GCSR_EXPL_POST_SIG_B_BUS_PULL) | \
0189      ((is_required) ? NFP_ARM_GCSR_EXPL_POST_SIG_B_VALID : 0))
0190
0191 #define NFP_ARM_GCSR_EXPA_CSR(mode, target, token, is_64, action, address) \
0192     (((mode) ? NFP_ARM_GCSR_EXPA_BAR_TYPE_EXPL : \
0193            NFP_ARM_GCSR_EXPA_BAR_TYPE_EXPA) | \
0194      NFP_ARM_GCSR_EXPA_BAR_TGT(target) | \
0195      NFP_ARM_GCSR_EXPA_BAR_TOK(token) | \
0196      ((is_64) ? NFP_ARM_GCSR_EXPA_BAR_LEN_64BIT : \
0197             NFP_ARM_GCSR_EXPA_BAR_LEN_32BIT) | \
0198      NFP_ARM_GCSR_EXPA_BAR_ACT(action) | \
0199      NFP_ARM_GCSR_EXPA_BAR_ADDR((address) >> NFP_ARM_GCSR_EXPA_SHIFT))
0200
0201 #define NFP_ARM_GCSR_BULK_CSR(mode, target, token, is_64, address) \
0202     (((mode) ? NFP_ARM_GCSR_BULK_BAR_TYPE_EXPA : \
0203            NFP_ARM_GCSR_BULK_BAR_TYPE_BULK) | \
0204      NFP_ARM_GCSR_BULK_BAR_TGT(target) | \
0205      NFP_ARM_GCSR_BULK_BAR_TOK(token) | \
0206      ((is_64) ? NFP_ARM_GCSR_BULK_BAR_LEN_64BIT : \
0207             NFP_ARM_GCSR_BULK_BAR_LEN_32BIT) | \
0208      NFP_ARM_GCSR_BULK_BAR_ADDR((address) >> NFP_ARM_GCSR_BULK_SHIFT))
0209
0210     /* MP Core CSRs */
0211 #define NFP_ARM_MPCORE_SIZE SZ_128K
0212
0213     /* PL320 CSRs */
0214 #define NFP_ARM_PCSR_SIZE   SZ_64K
0215
0216 #endif /* NFP_ARM_H */