netronome/nfp/nfp_net_ctrl.h

0001 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
0002 /* Copyright (C) 2015-2018 Netronome Systems, Inc. */
0003
0004 /* nfp_net_ctrl.h
0005  * Netronome network device driver: Control BAR layout
0006  * Authors: Jakub Kicinski <jakub.kicinski@netronome.com>
0007  *          Jason McMullan <jason.mcmullan@netronome.com>
0008  *          Rolf Neugebauer <rolf.neugebauer@netronome.com>
0009  *          Brad Petrus <brad.petrus@netronome.com>
0010  */
0011
0012 #ifndef _NFP_NET_CTRL_H_
0013 #define _NFP_NET_CTRL_H_
0014
0015 #include <linux/types.h>
0016
0017 /* Configuration BAR size.
0018  *
0019  * The configuration BAR is 8K in size, but due to
0020  * THB-350, 32k needs to be reserved.
0021  */
0022 #define NFP_NET_CFG_BAR_SZ      (32 * 1024)
0023
0024 /* Offset in Freelist buffer where packet starts on RX */
0025 #define NFP_NET_RX_OFFSET       32
0026
0027 /* LSO parameters
0028  * %NFP_NET_LSO_MAX_HDR_SZ: Maximum header size supported for LSO frames
0029  * %NFP_NET_LSO_MAX_SEGS:   Maximum number of segments LSO frame can produce
0030  */
0031 #define NFP_NET_LSO_MAX_HDR_SZ      255
0032 #define NFP_NET_LSO_MAX_SEGS        64
0033
0034 /* working with metadata vlan api (NFD version >= 2.0) */
0035 #define NFP_NET_META_VLAN_STRIP         BIT(31)
0036 #define NFP_NET_META_VLAN_TPID_MASK     GENMASK(19, 16)
0037 #define NFP_NET_META_VLAN_TCI_MASK      GENMASK(15, 0)
0038
0039 /* Prepend field types */
0040 #define NFP_NET_META_FIELD_SIZE     4
0041 #define NFP_NET_META_HASH       1 /* next field carries hash type */
0042 #define NFP_NET_META_MARK       2
0043 #define NFP_NET_META_VLAN       4 /* ctag or stag type */
0044 #define NFP_NET_META_PORTID     5
0045 #define NFP_NET_META_CSUM       6 /* checksum complete type */
0046 #define NFP_NET_META_CONN_HANDLE    7
0047 #define NFP_NET_META_RESYNC_INFO    8 /* RX resync info request */
0048
0049 #define NFP_META_PORT_ID_CTRL       ~0U
0050
0051 /* Prepend field sizes */
0052 #define NFP_NET_META_VLAN_SIZE          4
0053 #define NFP_NET_META_PORTID_SIZE        4
0054 #define NFP_NET_META_CONN_HANDLE_SIZE       8
0055 /* Hash type pre-pended when a RSS hash was computed */
0056 #define NFP_NET_RSS_NONE        0
0057 #define NFP_NET_RSS_IPV4        1
0058 #define NFP_NET_RSS_IPV6        2
0059 #define NFP_NET_RSS_IPV6_EX     3
0060 #define NFP_NET_RSS_IPV4_TCP        4
0061 #define NFP_NET_RSS_IPV6_TCP        5
0062 #define NFP_NET_RSS_IPV6_EX_TCP     6
0063 #define NFP_NET_RSS_IPV4_UDP        7
0064 #define NFP_NET_RSS_IPV6_UDP        8
0065 #define NFP_NET_RSS_IPV6_EX_UDP     9
0066
0067 /* Ring counts
0068  * %NFP_NET_TXR_MAX:         Maximum number of TX rings
0069  * %NFP_NET_RXR_MAX:         Maximum number of RX rings
0070  */
0071 #define NFP_NET_TXR_MAX         64
0072 #define NFP_NET_RXR_MAX         64
0073
0074 /* Read/Write config words (0x0000 - 0x002c)
0075  * %NFP_NET_CFG_CTRL:        Global control
0076  * %NFP_NET_CFG_UPDATE:      Indicate which fields are updated
0077  * %NFP_NET_CFG_TXRS_ENABLE: Bitmask of enabled TX rings
0078  * %NFP_NET_CFG_RXRS_ENABLE: Bitmask of enabled RX rings
0079  * %NFP_NET_CFG_MTU:         Set MTU size
0080  * %NFP_NET_CFG_FLBUFSZ:     Set freelist buffer size (must be larger than MTU)
0081  * %NFP_NET_CFG_EXN:         MSI-X table entry for exceptions
0082  * %NFP_NET_CFG_LSC:         MSI-X table entry for link state changes
0083  * %NFP_NET_CFG_MACADDR:     MAC address
0084  *
0085  * TODO:
0086  * - define Error details in UPDATE
0087  */
0088 #define NFP_NET_CFG_CTRL        0x0000
0089 #define   NFP_NET_CFG_CTRL_ENABLE     (0x1 <<  0) /* Global enable */
0090 #define   NFP_NET_CFG_CTRL_PROMISC    (0x1 <<  1) /* Enable Promisc mode */
0091 #define   NFP_NET_CFG_CTRL_L2BC       (0x1 <<  2) /* Allow L2 Broadcast */
0092 #define   NFP_NET_CFG_CTRL_L2MC       (0x1 <<  3) /* Allow L2 Multicast */
0093 #define   NFP_NET_CFG_CTRL_RXCSUM     (0x1 <<  4) /* Enable RX Checksum */
0094 #define   NFP_NET_CFG_CTRL_TXCSUM     (0x1 <<  5) /* Enable TX Checksum */
0095 #define   NFP_NET_CFG_CTRL_RXVLAN     (0x1 <<  6) /* Enable VLAN strip */
0096 #define   NFP_NET_CFG_CTRL_TXVLAN     (0x1 <<  7) /* Enable VLAN insert */
0097 #define   NFP_NET_CFG_CTRL_SCATTER    (0x1 <<  8) /* Scatter DMA */
0098 #define   NFP_NET_CFG_CTRL_GATHER     (0x1 <<  9) /* Gather DMA */
0099 #define   NFP_NET_CFG_CTRL_LSO        (0x1 << 10) /* LSO/TSO (version 1) */
0100 #define   NFP_NET_CFG_CTRL_CTAG_FILTER    (0x1 << 11) /* VLAN CTAG filtering */
0101 #define   NFP_NET_CFG_CTRL_CMSG_DATA      (0x1 << 12) /* RX cmsgs on data Qs */
0102 #define   NFP_NET_CFG_CTRL_RXQINQ     (0x1 << 13) /* Enable S-tag strip */
0103 #define   NFP_NET_CFG_CTRL_RXVLAN_V2      (0x1 << 15) /* Enable C-tag strip */
0104 #define   NFP_NET_CFG_CTRL_RINGCFG    (0x1 << 16) /* Ring runtime changes */
0105 #define   NFP_NET_CFG_CTRL_RSS        (0x1 << 17) /* RSS (version 1) */
0106 #define   NFP_NET_CFG_CTRL_IRQMOD     (0x1 << 18) /* Interrupt moderation */
0107 #define   NFP_NET_CFG_CTRL_MSIXAUTO   (0x1 << 20) /* MSI-X auto-masking */
0108 #define   NFP_NET_CFG_CTRL_TXRWB      (0x1 << 21) /* Write-back of TX ring*/
0109 #define   NFP_NET_CFG_CTRL_VEPA       (0x1 << 22) /* Enable VEPA mode */
0110 #define   NFP_NET_CFG_CTRL_TXVLAN_V2      (0x1 << 23) /* Enable VLAN C-tag insert*/
0111 #define   NFP_NET_CFG_CTRL_VXLAN      (0x1 << 24) /* VXLAN tunnel support */
0112 #define   NFP_NET_CFG_CTRL_NVGRE      (0x1 << 25) /* NVGRE tunnel support */
0113 #define   NFP_NET_CFG_CTRL_BPF        (0x1 << 27) /* BPF offload capable */
0114 #define   NFP_NET_CFG_CTRL_LSO2       (0x1 << 28) /* LSO/TSO (version 2) */
0115 #define   NFP_NET_CFG_CTRL_RSS2       (0x1 << 29) /* RSS (version 2) */
0116 #define   NFP_NET_CFG_CTRL_CSUM_COMPLETE  (0x1 << 30) /* Checksum complete */
0117 #define   NFP_NET_CFG_CTRL_LIVE_ADDR      (0x1 << 31) /* live MAC addr change */
0118
0119 #define NFP_NET_CFG_CTRL_LSO_ANY    (NFP_NET_CFG_CTRL_LSO | \
0120                      NFP_NET_CFG_CTRL_LSO2)
0121 #define NFP_NET_CFG_CTRL_RSS_ANY    (NFP_NET_CFG_CTRL_RSS | \
0122                      NFP_NET_CFG_CTRL_RSS2)
0123 #define NFP_NET_CFG_CTRL_RXCSUM_ANY (NFP_NET_CFG_CTRL_RXCSUM | \
0124                      NFP_NET_CFG_CTRL_CSUM_COMPLETE)
0125 #define NFP_NET_CFG_CTRL_CHAIN_META (NFP_NET_CFG_CTRL_RSS2 | \
0126                      NFP_NET_CFG_CTRL_CSUM_COMPLETE)
0127 #define NFP_NET_CFG_CTRL_RXVLAN_ANY (NFP_NET_CFG_CTRL_RXVLAN | \
0128                      NFP_NET_CFG_CTRL_RXVLAN_V2)
0129 #define NFP_NET_CFG_CTRL_TXVLAN_ANY (NFP_NET_CFG_CTRL_TXVLAN | \
0130                      NFP_NET_CFG_CTRL_TXVLAN_V2)
0131
0132 #define NFP_NET_CFG_UPDATE      0x0004
0133 #define   NFP_NET_CFG_UPDATE_GEN      (0x1 <<  0) /* General update */
0134 #define   NFP_NET_CFG_UPDATE_RING     (0x1 <<  1) /* Ring config change */
0135 #define   NFP_NET_CFG_UPDATE_RSS      (0x1 <<  2) /* RSS config change */
0136 #define   NFP_NET_CFG_UPDATE_TXRPRIO      (0x1 <<  3) /* TX Ring prio change */
0137 #define   NFP_NET_CFG_UPDATE_RXRPRIO      (0x1 <<  4) /* RX Ring prio change */
0138 #define   NFP_NET_CFG_UPDATE_MSIX     (0x1 <<  5) /* MSI-X change */
0139 #define   NFP_NET_CFG_UPDATE_RESET    (0x1 <<  7) /* Update due to FLR */
0140 #define   NFP_NET_CFG_UPDATE_IRQMOD   (0x1 <<  8) /* IRQ mod change */
0141 #define   NFP_NET_CFG_UPDATE_VXLAN    (0x1 <<  9) /* VXLAN port change */
0142 #define   NFP_NET_CFG_UPDATE_BPF      (0x1 << 10) /* BPF program load */
0143 #define   NFP_NET_CFG_UPDATE_MACADDR      (0x1 << 11) /* MAC address change */
0144 #define   NFP_NET_CFG_UPDATE_MBOX     (0x1 << 12) /* Mailbox update */
0145 #define   NFP_NET_CFG_UPDATE_VF       (0x1 << 13) /* VF settings change */
0146 #define   NFP_NET_CFG_UPDATE_CRYPTO   (0x1 << 14) /* Crypto on/off */
0147 #define   NFP_NET_CFG_UPDATE_ERR      (0x1 << 31) /* A error occurred */
0148 #define NFP_NET_CFG_TXRS_ENABLE     0x0008
0149 #define NFP_NET_CFG_RXRS_ENABLE     0x0010
0150 #define NFP_NET_CFG_MTU         0x0018
0151 #define NFP_NET_CFG_FLBUFSZ     0x001c
0152 #define NFP_NET_CFG_EXN         0x001f
0153 #define NFP_NET_CFG_LSC         0x0020
0154 #define NFP_NET_CFG_MACADDR     0x0024
0155
0156 /* Read-only words (0x0030 - 0x0050):
0157  * %NFP_NET_CFG_VERSION:     Firmware version number
0158  * %NFP_NET_CFG_STS:         Status
0159  * %NFP_NET_CFG_CAP:         Capabilities (same bits as %NFP_NET_CFG_CTRL)
0160  * %NFP_NET_CFG_MAX_TXRINGS: Maximum number of TX rings
0161  * %NFP_NET_CFG_MAX_RXRINGS: Maximum number of RX rings
0162  * %NFP_NET_CFG_MAX_MTU:     Maximum support MTU
0163  * %NFP_NET_CFG_START_TXQ:   Start Queue Control Queue to use for TX (PF only)
0164  * %NFP_NET_CFG_START_RXQ:   Start Queue Control Queue to use for RX (PF only)
0165  *
0166  * TODO:
0167  * - define more STS bits
0168  */
0169 #define NFP_NET_CFG_VERSION     0x0030
0170 #define   NFP_NET_CFG_VERSION_RESERVED_MASK (0xfe << 24)
0171 #define   NFP_NET_CFG_VERSION_DP_NFD3       0
0172 #define   NFP_NET_CFG_VERSION_DP_NFDK       1
0173 #define   NFP_NET_CFG_VERSION_DP_MASK       1
0174 #define   NFP_NET_CFG_VERSION_CLASS_MASK  (0xff << 16)
0175 #define   NFP_NET_CFG_VERSION_CLASS(x)    (((x) & 0xff) << 16)
0176 #define   NFP_NET_CFG_VERSION_CLASS_GENERIC 0
0177 #define   NFP_NET_CFG_VERSION_MAJOR_MASK  (0xff <<  8)
0178 #define   NFP_NET_CFG_VERSION_MAJOR(x)    (((x) & 0xff) <<  8)
0179 #define   NFP_NET_CFG_VERSION_MINOR_MASK  (0xff <<  0)
0180 #define   NFP_NET_CFG_VERSION_MINOR(x)    (((x) & 0xff) <<  0)
0181 #define NFP_NET_CFG_STS         0x0034
0182 #define   NFP_NET_CFG_STS_LINK        (0x1 << 0) /* Link up or down */
0183 /* Link rate */
0184 #define   NFP_NET_CFG_STS_LINK_RATE_SHIFT 1
0185 #define   NFP_NET_CFG_STS_LINK_RATE_MASK  0xF
0186 #define   NFP_NET_CFG_STS_LINK_RATE   \
0187     (NFP_NET_CFG_STS_LINK_RATE_MASK << NFP_NET_CFG_STS_LINK_RATE_SHIFT)
0188 #define   NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED   0
0189 #define   NFP_NET_CFG_STS_LINK_RATE_UNKNOWN   1
0190 #define   NFP_NET_CFG_STS_LINK_RATE_1G        2
0191 #define   NFP_NET_CFG_STS_LINK_RATE_10G       3
0192 #define   NFP_NET_CFG_STS_LINK_RATE_25G       4
0193 #define   NFP_NET_CFG_STS_LINK_RATE_40G       5
0194 #define   NFP_NET_CFG_STS_LINK_RATE_50G       6
0195 #define   NFP_NET_CFG_STS_LINK_RATE_100G      7
0196 #define NFP_NET_CFG_CAP         0x0038
0197 #define NFP_NET_CFG_MAX_TXRINGS     0x003c
0198 #define NFP_NET_CFG_MAX_RXRINGS     0x0040
0199 #define NFP_NET_CFG_MAX_MTU     0x0044
0200 /* Next two words are being used by VFs for solving THB350 issue */
0201 #define NFP_NET_CFG_START_TXQ       0x0048
0202 #define NFP_NET_CFG_START_RXQ       0x004c
0203
0204 /* Prepend configuration
0205  */
0206 #define NFP_NET_CFG_RX_OFFSET       0x0050
0207 #define NFP_NET_CFG_RX_OFFSET_DYNAMIC       0   /* Prepend mode */
0208
0209 /* RSS capabilities
0210  * %NFP_NET_CFG_RSS_CAP_HFUNC:  supported hash functions (same bits as
0211  *              %NFP_NET_CFG_RSS_HFUNC)
0212  */
0213 #define NFP_NET_CFG_RSS_CAP     0x0054
0214 #define   NFP_NET_CFG_RSS_CAP_HFUNC   0xff000000
0215
0216 /* TLV area start
0217  * %NFP_NET_CFG_TLV_BASE:   start anchor of the TLV area
0218  */
0219 #define NFP_NET_CFG_TLV_BASE        0x0058
0220
0221 /* VXLAN/UDP encap configuration
0222  * %NFP_NET_CFG_VXLAN_PORT: Base address of table of tunnels' UDP dst ports
0223  * %NFP_NET_CFG_VXLAN_SZ:   Size of the UDP port table in bytes
0224  */
0225 #define NFP_NET_CFG_VXLAN_PORT      0x0060
0226 #define NFP_NET_CFG_VXLAN_SZ          0x0008
0227
0228 /* BPF section
0229  * %NFP_NET_CFG_BPF_ABI:    BPF ABI version
0230  * %NFP_NET_CFG_BPF_CAP:    BPF capabilities
0231  * %NFP_NET_CFG_BPF_MAX_LEN:    Maximum size of JITed BPF code in bytes
0232  * %NFP_NET_CFG_BPF_START:  Offset at which BPF will be loaded
0233  * %NFP_NET_CFG_BPF_DONE:   Offset to jump to on exit
0234  * %NFP_NET_CFG_BPF_STACK_SZ:   Total size of stack area in 64B chunks
0235  * %NFP_NET_CFG_BPF_INL_MTU:    Packet data split offset in 64B chunks
0236  * %NFP_NET_CFG_BPF_SIZE:   Size of the JITed BPF code in instructions
0237  * %NFP_NET_CFG_BPF_ADDR:   DMA address of the buffer with JITed BPF code
0238  */
0239 #define NFP_NET_CFG_BPF_ABI     0x0080
0240 #define NFP_NET_CFG_BPF_CAP     0x0081
0241 #define   NFP_NET_BPF_CAP_RELO      (1 << 0) /* seamless reload */
0242 #define NFP_NET_CFG_BPF_MAX_LEN     0x0082
0243 #define NFP_NET_CFG_BPF_START       0x0084
0244 #define NFP_NET_CFG_BPF_DONE        0x0086
0245 #define NFP_NET_CFG_BPF_STACK_SZ    0x0088
0246 #define NFP_NET_CFG_BPF_INL_MTU     0x0089
0247 #define NFP_NET_CFG_BPF_SIZE        0x008e
0248 #define NFP_NET_CFG_BPF_ADDR        0x0090
0249 #define   NFP_NET_CFG_BPF_CFG_8CTX  (1 << 0) /* 8ctx mode */
0250 #define   NFP_NET_CFG_BPF_CFG_MASK  7ULL
0251 #define   NFP_NET_CFG_BPF_ADDR_MASK (~NFP_NET_CFG_BPF_CFG_MASK)
0252
0253 /* 40B reserved for future use (0x0098 - 0x00c0)
0254  */
0255 #define NFP_NET_CFG_RESERVED        0x0098
0256 #define NFP_NET_CFG_RESERVED_SZ     0x0028
0257
0258 /* RSS configuration (0x0100 - 0x01ac):
0259  * Used only when NFP_NET_CFG_CTRL_RSS is enabled
0260  * %NFP_NET_CFG_RSS_CFG:     RSS configuration word
0261  * %NFP_NET_CFG_RSS_KEY:     RSS "secret" key
0262  * %NFP_NET_CFG_RSS_ITBL:    RSS indirection table
0263  */
0264 #define NFP_NET_CFG_RSS_BASE        0x0100
0265 #define NFP_NET_CFG_RSS_CTRL        NFP_NET_CFG_RSS_BASE
0266 #define   NFP_NET_CFG_RSS_MASK        (0x7f)
0267 #define   NFP_NET_CFG_RSS_MASK_of(_x)     ((_x) & 0x7f)
0268 #define   NFP_NET_CFG_RSS_IPV4        (1 <<  8) /* RSS for IPv4 */
0269 #define   NFP_NET_CFG_RSS_IPV6        (1 <<  9) /* RSS for IPv6 */
0270 #define   NFP_NET_CFG_RSS_IPV4_TCP    (1 << 10) /* RSS for IPv4/TCP */
0271 #define   NFP_NET_CFG_RSS_IPV4_UDP    (1 << 11) /* RSS for IPv4/UDP */
0272 #define   NFP_NET_CFG_RSS_IPV6_TCP    (1 << 12) /* RSS for IPv6/TCP */
0273 #define   NFP_NET_CFG_RSS_IPV6_UDP    (1 << 13) /* RSS for IPv6/UDP */
0274 #define   NFP_NET_CFG_RSS_HFUNC       0xff000000
0275 #define   NFP_NET_CFG_RSS_TOEPLITZ    (1 << 24) /* Use Toeplitz hash */
0276 #define   NFP_NET_CFG_RSS_XOR         (1 << 25) /* Use XOR as hash */
0277 #define   NFP_NET_CFG_RSS_CRC32       (1 << 26) /* Use CRC32 as hash */
0278 #define   NFP_NET_CFG_RSS_HFUNCS      3
0279 #define NFP_NET_CFG_RSS_KEY     (NFP_NET_CFG_RSS_BASE + 0x4)
0280 #define NFP_NET_CFG_RSS_KEY_SZ      0x28
0281 #define NFP_NET_CFG_RSS_ITBL        (NFP_NET_CFG_RSS_BASE + 0x4 + \
0282                      NFP_NET_CFG_RSS_KEY_SZ)
0283 #define NFP_NET_CFG_RSS_ITBL_SZ     0x80
0284
0285 /* TX ring configuration (0x200 - 0x800)
0286  * %NFP_NET_CFG_TXR_BASE:    Base offset for TX ring configuration
0287  * %NFP_NET_CFG_TXR_ADDR:    Per TX ring DMA address (8B entries)
0288  * %NFP_NET_CFG_TXR_WB_ADDR: Per TX ring write back DMA address (8B entries)
0289  * %NFP_NET_CFG_TXR_SZ:      Per TX ring ring size (1B entries)
0290  * %NFP_NET_CFG_TXR_VEC:     Per TX ring MSI-X table entry (1B entries)
0291  * %NFP_NET_CFG_TXR_PRIO:    Per TX ring priority (1B entries)
0292  * %NFP_NET_CFG_TXR_IRQ_MOD: Per TX ring interrupt moderation packet
0293  */
0294 #define NFP_NET_CFG_TXR_BASE        0x0200
0295 #define NFP_NET_CFG_TXR_ADDR(_x)    (NFP_NET_CFG_TXR_BASE + ((_x) * 0x8))
0296 #define NFP_NET_CFG_TXR_WB_ADDR(_x) (NFP_NET_CFG_TXR_BASE + 0x200 + \
0297                      ((_x) * 0x8))
0298 #define NFP_NET_CFG_TXR_SZ(_x)      (NFP_NET_CFG_TXR_BASE + 0x400 + (_x))
0299 #define NFP_NET_CFG_TXR_VEC(_x)     (NFP_NET_CFG_TXR_BASE + 0x440 + (_x))
0300 #define NFP_NET_CFG_TXR_PRIO(_x)    (NFP_NET_CFG_TXR_BASE + 0x480 + (_x))
0301 #define NFP_NET_CFG_TXR_IRQ_MOD(_x) (NFP_NET_CFG_TXR_BASE + 0x500 + \
0302                      ((_x) * 0x4))
0303
0304 /* RX ring configuration (0x0800 - 0x0c00)
0305  * %NFP_NET_CFG_RXR_BASE:    Base offset for RX ring configuration
0306  * %NFP_NET_CFG_RXR_ADDR:    Per RX ring DMA address (8B entries)
0307  * %NFP_NET_CFG_RXR_SZ:      Per RX ring ring size (1B entries)
0308  * %NFP_NET_CFG_RXR_VEC:     Per RX ring MSI-X table entry (1B entries)
0309  * %NFP_NET_CFG_RXR_PRIO:    Per RX ring priority (1B entries)
0310  * %NFP_NET_CFG_RXR_IRQ_MOD: Per RX ring interrupt moderation (4B entries)
0311  */
0312 #define NFP_NET_CFG_RXR_BASE        0x0800
0313 #define NFP_NET_CFG_RXR_ADDR(_x)    (NFP_NET_CFG_RXR_BASE + ((_x) * 0x8))
0314 #define NFP_NET_CFG_RXR_SZ(_x)      (NFP_NET_CFG_RXR_BASE + 0x200 + (_x))
0315 #define NFP_NET_CFG_RXR_VEC(_x)     (NFP_NET_CFG_RXR_BASE + 0x240 + (_x))
0316 #define NFP_NET_CFG_RXR_PRIO(_x)    (NFP_NET_CFG_RXR_BASE + 0x280 + (_x))
0317 #define NFP_NET_CFG_RXR_IRQ_MOD(_x) (NFP_NET_CFG_RXR_BASE + 0x300 + \
0318                      ((_x) * 0x4))
0319
0320 /* Interrupt Control/Cause registers (0x0c00 - 0x0d00)
0321  * These registers are only used when MSI-X auto-masking is not
0322  * enabled (%NFP_NET_CFG_CTRL_MSIXAUTO not set).  The array is index
0323  * by MSI-X entry and are 1B in size.  If an entry is zero, the
0324  * corresponding entry is enabled.  If the FW generates an interrupt,
0325  * it writes a cause into the corresponding field.  This also masks
0326  * the MSI-X entry and the host driver must clear the register to
0327  * re-enable the interrupt.
0328  */
0329 #define NFP_NET_CFG_ICR_BASE        0x0c00
0330 #define NFP_NET_CFG_ICR(_x)     (NFP_NET_CFG_ICR_BASE + (_x))
0331 #define   NFP_NET_CFG_ICR_UNMASKED  0x0
0332 #define   NFP_NET_CFG_ICR_RXTX      0x1
0333 #define   NFP_NET_CFG_ICR_LSC       0x2
0334
0335 /* General device stats (0x0d00 - 0x0d90)
0336  * all counters are 64bit.
0337  */
0338 #define NFP_NET_CFG_STATS_BASE      0x0d00
0339 #define NFP_NET_CFG_STATS_RX_DISCARDS   (NFP_NET_CFG_STATS_BASE + 0x00)
0340 #define NFP_NET_CFG_STATS_RX_ERRORS (NFP_NET_CFG_STATS_BASE + 0x08)
0341 #define NFP_NET_CFG_STATS_RX_OCTETS (NFP_NET_CFG_STATS_BASE + 0x10)
0342 #define NFP_NET_CFG_STATS_RX_UC_OCTETS  (NFP_NET_CFG_STATS_BASE + 0x18)
0343 #define NFP_NET_CFG_STATS_RX_MC_OCTETS  (NFP_NET_CFG_STATS_BASE + 0x20)
0344 #define NFP_NET_CFG_STATS_RX_BC_OCTETS  (NFP_NET_CFG_STATS_BASE + 0x28)
0345 #define NFP_NET_CFG_STATS_RX_FRAMES (NFP_NET_CFG_STATS_BASE + 0x30)
0346 #define NFP_NET_CFG_STATS_RX_MC_FRAMES  (NFP_NET_CFG_STATS_BASE + 0x38)
0347 #define NFP_NET_CFG_STATS_RX_BC_FRAMES  (NFP_NET_CFG_STATS_BASE + 0x40)
0348
0349 #define NFP_NET_CFG_STATS_TX_DISCARDS   (NFP_NET_CFG_STATS_BASE + 0x48)
0350 #define NFP_NET_CFG_STATS_TX_ERRORS (NFP_NET_CFG_STATS_BASE + 0x50)
0351 #define NFP_NET_CFG_STATS_TX_OCTETS (NFP_NET_CFG_STATS_BASE + 0x58)
0352 #define NFP_NET_CFG_STATS_TX_UC_OCTETS  (NFP_NET_CFG_STATS_BASE + 0x60)
0353 #define NFP_NET_CFG_STATS_TX_MC_OCTETS  (NFP_NET_CFG_STATS_BASE + 0x68)
0354 #define NFP_NET_CFG_STATS_TX_BC_OCTETS  (NFP_NET_CFG_STATS_BASE + 0x70)
0355 #define NFP_NET_CFG_STATS_TX_FRAMES (NFP_NET_CFG_STATS_BASE + 0x78)
0356 #define NFP_NET_CFG_STATS_TX_MC_FRAMES  (NFP_NET_CFG_STATS_BASE + 0x80)
0357 #define NFP_NET_CFG_STATS_TX_BC_FRAMES  (NFP_NET_CFG_STATS_BASE + 0x88)
0358
0359 #define NFP_NET_CFG_STATS_APP0_FRAMES   (NFP_NET_CFG_STATS_BASE + 0x90)
0360 #define NFP_NET_CFG_STATS_APP0_BYTES    (NFP_NET_CFG_STATS_BASE + 0x98)
0361 #define NFP_NET_CFG_STATS_APP1_FRAMES   (NFP_NET_CFG_STATS_BASE + 0xa0)
0362 #define NFP_NET_CFG_STATS_APP1_BYTES    (NFP_NET_CFG_STATS_BASE + 0xa8)
0363 #define NFP_NET_CFG_STATS_APP2_FRAMES   (NFP_NET_CFG_STATS_BASE + 0xb0)
0364 #define NFP_NET_CFG_STATS_APP2_BYTES    (NFP_NET_CFG_STATS_BASE + 0xb8)
0365 #define NFP_NET_CFG_STATS_APP3_FRAMES   (NFP_NET_CFG_STATS_BASE + 0xc0)
0366 #define NFP_NET_CFG_STATS_APP3_BYTES    (NFP_NET_CFG_STATS_BASE + 0xc8)
0367
0368 /* Per ring stats (0x1000 - 0x1800)
0369  * options, 64bit per entry
0370  * %NFP_NET_CFG_TXR_STATS:   TX ring statistics (Packet and Byte count)
0371  * %NFP_NET_CFG_RXR_STATS:   RX ring statistics (Packet and Byte count)
0372  */
0373 #define NFP_NET_CFG_TXR_STATS_BASE  0x1000
0374 #define NFP_NET_CFG_TXR_STATS(_x)   (NFP_NET_CFG_TXR_STATS_BASE + \
0375                      ((_x) * 0x10))
0376 #define NFP_NET_CFG_RXR_STATS_BASE  0x1400
0377 #define NFP_NET_CFG_RXR_STATS(_x)   (NFP_NET_CFG_RXR_STATS_BASE + \
0378                      ((_x) * 0x10))
0379
0380 /* General use mailbox area (0x1800 - 0x19ff)
0381  * 4B used for update command and 4B return code
0382  * followed by a max of 504B of variable length value
0383  */
0384 #define NFP_NET_CFG_MBOX_BASE       0x1800
0385 #define NFP_NET_CFG_MBOX_VAL_MAX_SZ 0x1F8
0386
0387 #define NFP_NET_CFG_MBOX_SIMPLE_CMD 0x0
0388 #define NFP_NET_CFG_MBOX_SIMPLE_RET 0x4
0389 #define NFP_NET_CFG_MBOX_SIMPLE_VAL 0x8
0390
0391 #define NFP_NET_CFG_MBOX_CMD_CTAG_FILTER_ADD 1
0392 #define NFP_NET_CFG_MBOX_CMD_CTAG_FILTER_KILL 2
0393
0394 #define NFP_NET_CFG_MBOX_CMD_PCI_DSCP_PRIOMAP_SET   5
0395 #define NFP_NET_CFG_MBOX_CMD_TLV_CMSG           6
0396
0397 /* VLAN filtering using general use mailbox
0398  * %NFP_NET_CFG_VLAN_FILTER:        Base address of VLAN filter mailbox
0399  * %NFP_NET_CFG_VLAN_FILTER_VID:    VLAN ID to filter
0400  * %NFP_NET_CFG_VLAN_FILTER_PROTO:  VLAN proto to filter
0401  * %NFP_NET_CFG_VXLAN_SZ:       Size of the VLAN filter mailbox in bytes
0402  */
0403 #define NFP_NET_CFG_VLAN_FILTER     NFP_NET_CFG_MBOX_SIMPLE_VAL
0404 #define  NFP_NET_CFG_VLAN_FILTER_VID    NFP_NET_CFG_VLAN_FILTER
0405 #define  NFP_NET_CFG_VLAN_FILTER_PROTO   (NFP_NET_CFG_VLAN_FILTER + 2)
0406 #define NFP_NET_CFG_VLAN_FILTER_SZ   0x0004
0407
0408 /* TLV capabilities
0409  * %NFP_NET_CFG_TLV_TYPE:   Offset of type within the TLV
0410  * %NFP_NET_CFG_TLV_TYPE_REQUIRED: Driver must be able to parse the TLV
0411  * %NFP_NET_CFG_TLV_LENGTH: Offset of length within the TLV
0412  * %NFP_NET_CFG_TLV_LENGTH_INC: TLV length increments
0413  * %NFP_NET_CFG_TLV_VALUE:  Offset of value with the TLV
0414  *
0415  * List of simple TLV structures, first one starts at %NFP_NET_CFG_TLV_BASE.
0416  * Last structure must be of type %NFP_NET_CFG_TLV_TYPE_END.  Presence of TLVs
0417  * is indicated by %NFP_NET_CFG_TLV_BASE being non-zero.  TLV structures may
0418  * fill the entire remainder of the BAR or be shorter.  FW must make sure TLVs
0419  * don't conflict with other features which allocate space beyond
0420  * %NFP_NET_CFG_TLV_BASE.  %NFP_NET_CFG_TLV_TYPE_RESERVED should be used to wrap
0421  * space used by such features.
0422  * Note that the 4 byte TLV header is not counted in %NFP_NET_CFG_TLV_LENGTH.
0423  */
0424 #define NFP_NET_CFG_TLV_TYPE        0x00
0425 #define   NFP_NET_CFG_TLV_TYPE_REQUIRED   0x8000
0426 #define NFP_NET_CFG_TLV_LENGTH      0x02
0427 #define   NFP_NET_CFG_TLV_LENGTH_INC      4
0428 #define NFP_NET_CFG_TLV_VALUE       0x04
0429
0430 #define NFP_NET_CFG_TLV_HEADER_REQUIRED 0x80000000
0431 #define NFP_NET_CFG_TLV_HEADER_TYPE 0x7fff0000
0432 #define NFP_NET_CFG_TLV_HEADER_LENGTH   0x0000ffff
0433
0434 /* Capability TLV types
0435  *
0436  * %NFP_NET_CFG_TLV_TYPE_UNKNOWN:
0437  * Special TLV type to catch bugs, should never be encountered.  Drivers should
0438  * treat encountering this type as error and refuse to probe.
0439  *
0440  * %NFP_NET_CFG_TLV_TYPE_RESERVED:
0441  * Reserved space, may contain legacy fixed-offset fields, or be used for
0442  * padding.  The use of this type should be otherwise avoided.
0443  *
0444  * %NFP_NET_CFG_TLV_TYPE_END:
0445  * Empty, end of TLV list.  Must be the last TLV.  Drivers will stop processing
0446  * further TLVs when encountered.
0447  *
0448  * %NFP_NET_CFG_TLV_TYPE_ME_FREQ:
0449  * Single word, ME frequency in MHz as used in calculation for
0450  * %NFP_NET_CFG_RXR_IRQ_MOD and %NFP_NET_CFG_TXR_IRQ_MOD.
0451  *
0452  * %NFP_NET_CFG_TLV_TYPE_MBOX:
0453  * Variable, mailbox area.  Overwrites the default location which is
0454  * %NFP_NET_CFG_MBOX_BASE and length %NFP_NET_CFG_MBOX_VAL_MAX_SZ.
0455  *
0456  * %NFP_NET_CFG_TLV_TYPE_EXPERIMENTAL0:
0457  * %NFP_NET_CFG_TLV_TYPE_EXPERIMENTAL1:
0458  * Variable, experimental IDs.  IDs designated for internal development and
0459  * experiments before a stable TLV ID has been allocated to a feature.  Should
0460  * never be present in production firmware.
0461  *
0462  * %NFP_NET_CFG_TLV_TYPE_REPR_CAP:
0463  * Single word, equivalent of %NFP_NET_CFG_CAP for representors, features which
0464  * can be used on representors.
0465  *
0466  * %NFP_NET_CFG_TLV_TYPE_MBOX_CMSG_TYPES:
0467  * Variable, bitmap of control message types supported by the mailbox handler.
0468  * Bit 0 corresponds to message type 0, bit 1 to 1, etc.  Control messages are
0469  * encapsulated into simple TLVs, with an end TLV and written to the Mailbox.
0470  *
0471  * %NFP_NET_CFG_TLV_TYPE_CRYPTO_OPS:
0472  * 8 words, bitmaps of supported and enabled crypto operations.
0473  * First 16B (4 words) contains a bitmap of supported crypto operations,
0474  * and next 16B contain the enabled operations.
0475  * This capability is made obsolete by ones with better sync methods.
0476  *
0477  * %NFP_NET_CFG_TLV_TYPE_VNIC_STATS:
0478  * Variable, per-vNIC statistics, data should be 8B aligned (FW should insert
0479  * zero-length RESERVED TLV to pad).
0480  * TLV data has two sections.  First is an array of statistics' IDs (2B each).
0481  * Second 8B statistics themselves.  Statistics are 8B aligned, meaning there
0482  * may be a padding between sections.
0483  * Number of statistics can be determined as floor(tlv.length / (2 + 8)).
0484  * This TLV overwrites %NFP_NET_CFG_STATS_* values (statistics in this TLV
0485  * duplicate the old ones, so driver should be careful not to unnecessarily
0486  * render both).
0487  *
0488  * %NFP_NET_CFG_TLV_TYPE_CRYPTO_OPS_RX_SCAN:
0489  * Same as %NFP_NET_CFG_TLV_TYPE_CRYPTO_OPS, but crypto TLS does stream scan
0490  * RX sync, rather than kernel-assisted sync.
0491  */
0492 #define NFP_NET_CFG_TLV_TYPE_UNKNOWN        0
0493 #define NFP_NET_CFG_TLV_TYPE_RESERVED       1
0494 #define NFP_NET_CFG_TLV_TYPE_END        2
0495 #define NFP_NET_CFG_TLV_TYPE_ME_FREQ        3
0496 #define NFP_NET_CFG_TLV_TYPE_MBOX       4
0497 #define NFP_NET_CFG_TLV_TYPE_EXPERIMENTAL0  5
0498 #define NFP_NET_CFG_TLV_TYPE_EXPERIMENTAL1  6
0499 #define NFP_NET_CFG_TLV_TYPE_REPR_CAP       7
0500 #define NFP_NET_CFG_TLV_TYPE_MBOX_CMSG_TYPES    10
0501 #define NFP_NET_CFG_TLV_TYPE_CRYPTO_OPS     11 /* see crypto/fw.h */
0502 #define NFP_NET_CFG_TLV_TYPE_VNIC_STATS     12
0503 #define NFP_NET_CFG_TLV_TYPE_CRYPTO_OPS_RX_SCAN 13
0504
0505 struct device;
0506
0507 /* struct nfp_net_tlv_caps - parsed control BAR TLV capabilities
0508  * @me_freq_mhz:    ME clock_freq (MHz)
0509  * @mbox_off:       vNIC mailbox area offset
0510  * @mbox_len:       vNIC mailbox area length
0511  * @repr_cap:       capabilities for representors
0512  * @mbox_cmsg_types:    cmsgs which can be passed through the mailbox
0513  * @crypto_ops:     supported crypto operations
0514  * @crypto_enable_off:  offset of crypto ops enable region
0515  * @vnic_stats_off: offset of vNIC stats area
0516  * @vnic_stats_cnt: number of vNIC stats
0517  * @tls_resync_ss:  TLS resync will be performed via stream scan
0518  */
0519 struct nfp_net_tlv_caps {
0520     u32 me_freq_mhz;
0521     unsigned int mbox_off;
0522     unsigned int mbox_len;
0523     u32 repr_cap;
0524     u32 mbox_cmsg_types;
0525     u32 crypto_ops;
0526     unsigned int crypto_enable_off;
0527     unsigned int vnic_stats_off;
0528     unsigned int vnic_stats_cnt;
0529     unsigned int tls_resync_ss:1;
0530 };
0531
0532 int nfp_net_tlv_caps_parse(struct device *dev, u8 __iomem *ctrl_mem,
0533                struct nfp_net_tlv_caps *caps);
0534 #endif /* _NFP_NET_CTRL_H_ */