netronome/nfp/nfp_asm.c

0001 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 /* Copyright (C) 2016-2018 Netronome Systems, Inc. */
0003
0004 #include <linux/bitops.h>
0005 #include <linux/errno.h>
0006 #include <linux/kernel.h>
0007 #include <linux/string.h>
0008 #include <linux/types.h>
0009
0010 #include "nfp_asm.h"
0011
0012 const struct cmd_tgt_act cmd_tgt_act[__CMD_TGT_MAP_SIZE] = {
0013     [CMD_TGT_WRITE8_SWAP] =     { 0x02, 0x42 },
0014     [CMD_TGT_WRITE32_SWAP] =    { 0x02, 0x5f },
0015     [CMD_TGT_READ8] =       { 0x01, 0x43 },
0016     [CMD_TGT_READ32] =      { 0x00, 0x5c },
0017     [CMD_TGT_READ32_LE] =       { 0x01, 0x5c },
0018     [CMD_TGT_READ32_SWAP] =     { 0x02, 0x5c },
0019     [CMD_TGT_READ_LE] =     { 0x01, 0x40 },
0020     [CMD_TGT_READ_SWAP_LE] =    { 0x03, 0x40 },
0021     [CMD_TGT_ADD] =         { 0x00, 0x47 },
0022     [CMD_TGT_ADD_IMM] =     { 0x02, 0x47 },
0023 };
0024
0025 static bool unreg_is_imm(u16 reg)
0026 {
0027     return (reg & UR_REG_IMM) == UR_REG_IMM;
0028 }
0029
0030 u16 br_get_offset(u64 instr)
0031 {
0032     u16 addr_lo, addr_hi;
0033
0034     addr_lo = FIELD_GET(OP_BR_ADDR_LO, instr);
0035     addr_hi = FIELD_GET(OP_BR_ADDR_HI, instr);
0036
0037     return (addr_hi * ((OP_BR_ADDR_LO >> __bf_shf(OP_BR_ADDR_LO)) + 1)) |
0038         addr_lo;
0039 }
0040
0041 void br_set_offset(u64 *instr, u16 offset)
0042 {
0043     u16 addr_lo, addr_hi;
0044
0045     addr_lo = offset & (OP_BR_ADDR_LO >> __bf_shf(OP_BR_ADDR_LO));
0046     addr_hi = offset != addr_lo;
0047     *instr &= ~(OP_BR_ADDR_HI | OP_BR_ADDR_LO);
0048     *instr |= FIELD_PREP(OP_BR_ADDR_HI, addr_hi);
0049     *instr |= FIELD_PREP(OP_BR_ADDR_LO, addr_lo);
0050 }
0051
0052 void br_add_offset(u64 *instr, u16 offset)
0053 {
0054     u16 addr;
0055
0056     addr = br_get_offset(*instr);
0057     br_set_offset(instr, addr + offset);
0058 }
0059
0060 static bool immed_can_modify(u64 instr)
0061 {
0062     if (FIELD_GET(OP_IMMED_INV, instr) ||
0063         FIELD_GET(OP_IMMED_SHIFT, instr) ||
0064         FIELD_GET(OP_IMMED_WIDTH, instr) != IMMED_WIDTH_ALL) {
0065         pr_err("Can't decode/encode immed!\n");
0066         return false;
0067     }
0068     return true;
0069 }
0070
0071 u16 immed_get_value(u64 instr)
0072 {
0073     u16 reg;
0074
0075     if (!immed_can_modify(instr))
0076         return 0;
0077
0078     reg = FIELD_GET(OP_IMMED_A_SRC, instr);
0079     if (!unreg_is_imm(reg))
0080         reg = FIELD_GET(OP_IMMED_B_SRC, instr);
0081
0082     return (reg & 0xff) | FIELD_GET(OP_IMMED_IMM, instr) << 8;
0083 }
0084
0085 void immed_set_value(u64 *instr, u16 immed)
0086 {
0087     if (!immed_can_modify(*instr))
0088         return;
0089
0090     if (unreg_is_imm(FIELD_GET(OP_IMMED_A_SRC, *instr))) {
0091         *instr &= ~FIELD_PREP(OP_IMMED_A_SRC, 0xff);
0092         *instr |= FIELD_PREP(OP_IMMED_A_SRC, immed & 0xff);
0093     } else {
0094         *instr &= ~FIELD_PREP(OP_IMMED_B_SRC, 0xff);
0095         *instr |= FIELD_PREP(OP_IMMED_B_SRC, immed & 0xff);
0096     }
0097
0098     *instr &= ~OP_IMMED_IMM;
0099     *instr |= FIELD_PREP(OP_IMMED_IMM, immed >> 8);
0100 }
0101
0102 void immed_add_value(u64 *instr, u16 offset)
0103 {
0104     u16 val;
0105
0106     if (!immed_can_modify(*instr))
0107         return;
0108
0109     val = immed_get_value(*instr);
0110     immed_set_value(instr, val + offset);
0111 }
0112
0113 static u16 nfp_swreg_to_unreg(swreg reg, bool is_dst)
0114 {
0115     bool lm_id, lm_dec = false;
0116     u16 val = swreg_value(reg);
0117
0118     switch (swreg_type(reg)) {
0119     case NN_REG_GPR_A:
0120     case NN_REG_GPR_B:
0121     case NN_REG_GPR_BOTH:
0122         return val;
0123     case NN_REG_NNR:
0124         return UR_REG_NN | val;
0125     case NN_REG_XFER:
0126         return UR_REG_XFR | val;
0127     case NN_REG_LMEM:
0128         lm_id = swreg_lm_idx(reg);
0129
0130         switch (swreg_lm_mode(reg)) {
0131         case NN_LM_MOD_NONE:
0132             if (val & ~UR_REG_LM_IDX_MAX) {
0133                 pr_err("LM offset too large\n");
0134                 return 0;
0135             }
0136             return UR_REG_LM | FIELD_PREP(UR_REG_LM_IDX, lm_id) |
0137                 val;
0138         case NN_LM_MOD_DEC:
0139             lm_dec = true;
0140             fallthrough;
0141         case NN_LM_MOD_INC:
0142             if (val) {
0143                 pr_err("LM offset in inc/dev mode\n");
0144                 return 0;
0145             }
0146             return UR_REG_LM | UR_REG_LM_POST_MOD |
0147                 FIELD_PREP(UR_REG_LM_IDX, lm_id) |
0148                 FIELD_PREP(UR_REG_LM_POST_MOD_DEC, lm_dec);
0149         default:
0150             pr_err("bad LM mode for unrestricted operands %d\n",
0151                    swreg_lm_mode(reg));
0152             return 0;
0153         }
0154     case NN_REG_IMM:
0155         if (val & ~0xff) {
0156             pr_err("immediate too large\n");
0157             return 0;
0158         }
0159         return UR_REG_IMM_encode(val);
0160     case NN_REG_NONE:
0161         return is_dst ? UR_REG_NO_DST : REG_NONE;
0162     }
0163
0164     pr_err("unrecognized reg encoding %08x\n", reg);
0165     return 0;
0166 }
0167
0168 int swreg_to_unrestricted(swreg dst, swreg lreg, swreg rreg,
0169               struct nfp_insn_ur_regs *reg)
0170 {
0171     memset(reg, 0, sizeof(*reg));
0172
0173     /* Decode destination */
0174     if (swreg_type(dst) == NN_REG_IMM)
0175         return -EFAULT;
0176
0177     if (swreg_type(dst) == NN_REG_GPR_B)
0178         reg->dst_ab = ALU_DST_B;
0179     if (swreg_type(dst) == NN_REG_GPR_BOTH)
0180         reg->wr_both = true;
0181     reg->dst = nfp_swreg_to_unreg(dst, true);
0182
0183     /* Decode source operands */
0184     if (swreg_type(lreg) == swreg_type(rreg) &&
0185         swreg_type(lreg) != NN_REG_NONE)
0186         return -EFAULT;
0187
0188     if (swreg_type(lreg) == NN_REG_GPR_B ||
0189         swreg_type(rreg) == NN_REG_GPR_A) {
0190         reg->areg = nfp_swreg_to_unreg(rreg, false);
0191         reg->breg = nfp_swreg_to_unreg(lreg, false);
0192         reg->swap = true;
0193     } else {
0194         reg->areg = nfp_swreg_to_unreg(lreg, false);
0195         reg->breg = nfp_swreg_to_unreg(rreg, false);
0196     }
0197
0198     reg->dst_lmextn = swreg_lmextn(dst);
0199     reg->src_lmextn = swreg_lmextn(lreg) || swreg_lmextn(rreg);
0200
0201     return 0;
0202 }
0203
0204 static u16 nfp_swreg_to_rereg(swreg reg, bool is_dst, bool has_imm8, bool *i8)
0205 {
0206     u16 val = swreg_value(reg);
0207     bool lm_id;
0208
0209     switch (swreg_type(reg)) {
0210     case NN_REG_GPR_A:
0211     case NN_REG_GPR_B:
0212     case NN_REG_GPR_BOTH:
0213         return val;
0214     case NN_REG_XFER:
0215         return RE_REG_XFR | val;
0216     case NN_REG_LMEM:
0217         lm_id = swreg_lm_idx(reg);
0218
0219         if (swreg_lm_mode(reg) != NN_LM_MOD_NONE) {
0220             pr_err("bad LM mode for restricted operands %d\n",
0221                    swreg_lm_mode(reg));
0222             return 0;
0223         }
0224
0225         if (val & ~RE_REG_LM_IDX_MAX) {
0226             pr_err("LM offset too large\n");
0227             return 0;
0228         }
0229
0230         return RE_REG_LM | FIELD_PREP(RE_REG_LM_IDX, lm_id) | val;
0231     case NN_REG_IMM:
0232         if (val & ~(0x7f | has_imm8 << 7)) {
0233             pr_err("immediate too large\n");
0234             return 0;
0235         }
0236         *i8 = val & 0x80;
0237         return RE_REG_IMM_encode(val & 0x7f);
0238     case NN_REG_NONE:
0239         return is_dst ? RE_REG_NO_DST : REG_NONE;
0240     case NN_REG_NNR:
0241         pr_err("NNRs used with restricted encoding\n");
0242         return 0;
0243     }
0244
0245     pr_err("unrecognized reg encoding\n");
0246     return 0;
0247 }
0248
0249 int swreg_to_restricted(swreg dst, swreg lreg, swreg rreg,
0250             struct nfp_insn_re_regs *reg, bool has_imm8)
0251 {
0252     memset(reg, 0, sizeof(*reg));
0253
0254     /* Decode destination */
0255     if (swreg_type(dst) == NN_REG_IMM)
0256         return -EFAULT;
0257
0258     if (swreg_type(dst) == NN_REG_GPR_B)
0259         reg->dst_ab = ALU_DST_B;
0260     if (swreg_type(dst) == NN_REG_GPR_BOTH)
0261         reg->wr_both = true;
0262     reg->dst = nfp_swreg_to_rereg(dst, true, false, NULL);
0263
0264     /* Decode source operands */
0265     if (swreg_type(lreg) == swreg_type(rreg) &&
0266         swreg_type(lreg) != NN_REG_NONE)
0267         return -EFAULT;
0268
0269     if (swreg_type(lreg) == NN_REG_GPR_B ||
0270         swreg_type(rreg) == NN_REG_GPR_A) {
0271         reg->areg = nfp_swreg_to_rereg(rreg, false, has_imm8, &reg->i8);
0272         reg->breg = nfp_swreg_to_rereg(lreg, false, has_imm8, &reg->i8);
0273         reg->swap = true;
0274     } else {
0275         reg->areg = nfp_swreg_to_rereg(lreg, false, has_imm8, &reg->i8);
0276         reg->breg = nfp_swreg_to_rereg(rreg, false, has_imm8, &reg->i8);
0277     }
0278
0279     reg->dst_lmextn = swreg_lmextn(dst);
0280     reg->src_lmextn = swreg_lmextn(lreg) || swreg_lmextn(rreg);
0281
0282     return 0;
0283 }
0284
0285 #define NFP_USTORE_ECC_POLY_WORDS       7
0286 #define NFP_USTORE_OP_BITS          45
0287
0288 static const u64 nfp_ustore_ecc_polynomials[NFP_USTORE_ECC_POLY_WORDS] = {
0289     0x0ff800007fffULL,
0290     0x11f801ff801fULL,
0291     0x1e387e0781e1ULL,
0292     0x17cb8e388e22ULL,
0293     0x1af5b2c93244ULL,
0294     0x1f56d5525488ULL,
0295     0x0daf69a46910ULL,
0296 };
0297
0298 static bool parity(u64 value)
0299 {
0300     return hweight64(value) & 1;
0301 }
0302
0303 int nfp_ustore_check_valid_no_ecc(u64 insn)
0304 {
0305     if (insn & ~GENMASK_ULL(NFP_USTORE_OP_BITS, 0))
0306         return -EINVAL;
0307
0308     return 0;
0309 }
0310
0311 u64 nfp_ustore_calc_ecc_insn(u64 insn)
0312 {
0313     u8 ecc = 0;
0314     int i;
0315
0316     for (i = 0; i < NFP_USTORE_ECC_POLY_WORDS; i++)
0317         ecc |= parity(nfp_ustore_ecc_polynomials[i] & insn) << i;
0318
0319     return insn | (u64)ecc << NFP_USTORE_OP_BITS;
0320 }