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0001 /************************************************************************
0002  * s2io.h: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
0003  * Copyright(c) 2002-2010 Exar Corp.
0004 
0005  * This software may be used and distributed according to the terms of
0006  * the GNU General Public License (GPL), incorporated herein by reference.
0007  * Drivers based on or derived from this code fall under the GPL and must
0008  * retain the authorship, copyright and license notice.  This file is not
0009  * a complete program and may only be used when the entire operating
0010  * system is licensed under the GPL.
0011  * See the file COPYING in this distribution for more information.
0012  ************************************************************************/
0013 #include <linux/io-64-nonatomic-lo-hi.h>
0014 #ifndef _S2IO_H
0015 #define _S2IO_H
0016 
0017 #define TBD 0
0018 #define s2BIT(loc)      (0x8000000000000000ULL >> (loc))
0019 #define vBIT(val, loc, sz)  (((u64)val) << (64-loc-sz))
0020 #define INV(d)  ((d&0xff)<<24) | (((d>>8)&0xff)<<16) | (((d>>16)&0xff)<<8)| ((d>>24)&0xff)
0021 
0022 #undef SUCCESS
0023 #define SUCCESS 0
0024 #define FAILURE -1
0025 #define S2IO_MINUS_ONE 0xFFFFFFFFFFFFFFFFULL
0026 #define S2IO_DISABLE_MAC_ENTRY 0xFFFFFFFFFFFFULL
0027 #define S2IO_MAX_PCI_CONFIG_SPACE_REINIT 100
0028 #define S2IO_BIT_RESET 1
0029 #define S2IO_BIT_SET 2
0030 #define CHECKBIT(value, nbit) (value & (1 << nbit))
0031 
0032 /* Maximum time to flicker LED when asked to identify NIC using ethtool */
0033 #define MAX_FLICKER_TIME    60000 /* 60 Secs */
0034 
0035 /* Maximum outstanding splits to be configured into xena. */
0036 enum {
0037     XENA_ONE_SPLIT_TRANSACTION = 0,
0038     XENA_TWO_SPLIT_TRANSACTION = 1,
0039     XENA_THREE_SPLIT_TRANSACTION = 2,
0040     XENA_FOUR_SPLIT_TRANSACTION = 3,
0041     XENA_EIGHT_SPLIT_TRANSACTION = 4,
0042     XENA_TWELVE_SPLIT_TRANSACTION = 5,
0043     XENA_SIXTEEN_SPLIT_TRANSACTION = 6,
0044     XENA_THIRTYTWO_SPLIT_TRANSACTION = 7
0045 };
0046 #define XENA_MAX_OUTSTANDING_SPLITS(n) (n << 4)
0047 
0048 /*  OS concerned variables and constants */
0049 #define WATCH_DOG_TIMEOUT       15*HZ
0050 #define EFILL               0x1234
0051 #define ALIGN_SIZE          127
0052 #define PCIX_COMMAND_REGISTER       0x62
0053 
0054 /*
0055  * Debug related variables.
0056  */
0057 /* different debug levels. */
0058 #define ERR_DBG     0
0059 #define INIT_DBG    1
0060 #define INFO_DBG    2
0061 #define TX_DBG      3
0062 #define INTR_DBG    4
0063 
0064 /* Global variable that defines the present debug level of the driver. */
0065 static int debug_level = ERR_DBG;
0066 
0067 /* DEBUG message print. */
0068 #define DBG_PRINT(dbg_level, fmt, args...) do {         \
0069     if (dbg_level <= debug_level)               \
0070         pr_info(fmt, ##args);               \
0071     } while (0)
0072 
0073 /* Protocol assist features of the NIC */
0074 #define L3_CKSUM_OK 0xFFFF
0075 #define L4_CKSUM_OK 0xFFFF
0076 #define S2IO_JUMBO_SIZE 9600
0077 
0078 /* Driver statistics maintained by driver */
0079 struct swStat {
0080     unsigned long long single_ecc_errs;
0081     unsigned long long double_ecc_errs;
0082     unsigned long long parity_err_cnt;
0083     unsigned long long serious_err_cnt;
0084     unsigned long long soft_reset_cnt;
0085     unsigned long long fifo_full_cnt;
0086     unsigned long long ring_full_cnt[8];
0087     /* LRO statistics */
0088     unsigned long long clubbed_frms_cnt;
0089     unsigned long long sending_both;
0090     unsigned long long outof_sequence_pkts;
0091     unsigned long long flush_max_pkts;
0092     unsigned long long sum_avg_pkts_aggregated;
0093     unsigned long long num_aggregations;
0094     /* Other statistics */
0095     unsigned long long mem_alloc_fail_cnt;
0096     unsigned long long pci_map_fail_cnt;
0097     unsigned long long watchdog_timer_cnt;
0098     unsigned long long mem_allocated;
0099     unsigned long long mem_freed;
0100     unsigned long long link_up_cnt;
0101     unsigned long long link_down_cnt;
0102     unsigned long long link_up_time;
0103     unsigned long long link_down_time;
0104 
0105     /* Transfer Code statistics */
0106     unsigned long long tx_buf_abort_cnt;
0107     unsigned long long tx_desc_abort_cnt;
0108     unsigned long long tx_parity_err_cnt;
0109     unsigned long long tx_link_loss_cnt;
0110     unsigned long long tx_list_proc_err_cnt;
0111 
0112     unsigned long long rx_parity_err_cnt;
0113     unsigned long long rx_abort_cnt;
0114     unsigned long long rx_parity_abort_cnt;
0115     unsigned long long rx_rda_fail_cnt;
0116     unsigned long long rx_unkn_prot_cnt;
0117     unsigned long long rx_fcs_err_cnt;
0118     unsigned long long rx_buf_size_err_cnt;
0119     unsigned long long rx_rxd_corrupt_cnt;
0120     unsigned long long rx_unkn_err_cnt;
0121 
0122     /* Error/alarm statistics*/
0123     unsigned long long tda_err_cnt;
0124     unsigned long long pfc_err_cnt;
0125     unsigned long long pcc_err_cnt;
0126     unsigned long long tti_err_cnt;
0127     unsigned long long lso_err_cnt;
0128     unsigned long long tpa_err_cnt;
0129     unsigned long long sm_err_cnt;
0130     unsigned long long mac_tmac_err_cnt;
0131     unsigned long long mac_rmac_err_cnt;
0132     unsigned long long xgxs_txgxs_err_cnt;
0133     unsigned long long xgxs_rxgxs_err_cnt;
0134     unsigned long long rc_err_cnt;
0135     unsigned long long prc_pcix_err_cnt;
0136     unsigned long long rpa_err_cnt;
0137     unsigned long long rda_err_cnt;
0138     unsigned long long rti_err_cnt;
0139     unsigned long long mc_err_cnt;
0140 
0141 };
0142 
0143 /* Xpak releated alarm and warnings */
0144 struct xpakStat {
0145     u64 alarm_transceiver_temp_high;
0146     u64 alarm_transceiver_temp_low;
0147     u64 alarm_laser_bias_current_high;
0148     u64 alarm_laser_bias_current_low;
0149     u64 alarm_laser_output_power_high;
0150     u64 alarm_laser_output_power_low;
0151     u64 warn_transceiver_temp_high;
0152     u64 warn_transceiver_temp_low;
0153     u64 warn_laser_bias_current_high;
0154     u64 warn_laser_bias_current_low;
0155     u64 warn_laser_output_power_high;
0156     u64 warn_laser_output_power_low;
0157     u64 xpak_regs_stat;
0158     u32 xpak_timer_count;
0159 };
0160 
0161 
0162 /* The statistics block of Xena */
0163 struct stat_block {
0164 /* Tx MAC statistics counters. */
0165     __le32 tmac_data_octets;
0166     __le32 tmac_frms;
0167     __le64 tmac_drop_frms;
0168     __le32 tmac_bcst_frms;
0169     __le32 tmac_mcst_frms;
0170     __le64 tmac_pause_ctrl_frms;
0171     __le32 tmac_ucst_frms;
0172     __le32 tmac_ttl_octets;
0173     __le32 tmac_any_err_frms;
0174     __le32 tmac_nucst_frms;
0175     __le64 tmac_ttl_less_fb_octets;
0176     __le64 tmac_vld_ip_octets;
0177     __le32 tmac_drop_ip;
0178     __le32 tmac_vld_ip;
0179     __le32 tmac_rst_tcp;
0180     __le32 tmac_icmp;
0181     __le64 tmac_tcp;
0182     __le32 reserved_0;
0183     __le32 tmac_udp;
0184 
0185 /* Rx MAC Statistics counters. */
0186     __le32 rmac_data_octets;
0187     __le32 rmac_vld_frms;
0188     __le64 rmac_fcs_err_frms;
0189     __le64 rmac_drop_frms;
0190     __le32 rmac_vld_bcst_frms;
0191     __le32 rmac_vld_mcst_frms;
0192     __le32 rmac_out_rng_len_err_frms;
0193     __le32 rmac_in_rng_len_err_frms;
0194     __le64 rmac_long_frms;
0195     __le64 rmac_pause_ctrl_frms;
0196     __le64 rmac_unsup_ctrl_frms;
0197     __le32 rmac_accepted_ucst_frms;
0198     __le32 rmac_ttl_octets;
0199     __le32 rmac_discarded_frms;
0200     __le32 rmac_accepted_nucst_frms;
0201     __le32 reserved_1;
0202     __le32 rmac_drop_events;
0203     __le64 rmac_ttl_less_fb_octets;
0204     __le64 rmac_ttl_frms;
0205     __le64 reserved_2;
0206     __le32 rmac_usized_frms;
0207     __le32 reserved_3;
0208     __le32 rmac_frag_frms;
0209     __le32 rmac_osized_frms;
0210     __le32 reserved_4;
0211     __le32 rmac_jabber_frms;
0212     __le64 rmac_ttl_64_frms;
0213     __le64 rmac_ttl_65_127_frms;
0214     __le64 reserved_5;
0215     __le64 rmac_ttl_128_255_frms;
0216     __le64 rmac_ttl_256_511_frms;
0217     __le64 reserved_6;
0218     __le64 rmac_ttl_512_1023_frms;
0219     __le64 rmac_ttl_1024_1518_frms;
0220     __le32 rmac_ip;
0221     __le32 reserved_7;
0222     __le64 rmac_ip_octets;
0223     __le32 rmac_drop_ip;
0224     __le32 rmac_hdr_err_ip;
0225     __le32 reserved_8;
0226     __le32 rmac_icmp;
0227     __le64 rmac_tcp;
0228     __le32 rmac_err_drp_udp;
0229     __le32 rmac_udp;
0230     __le64 rmac_xgmii_err_sym;
0231     __le64 rmac_frms_q0;
0232     __le64 rmac_frms_q1;
0233     __le64 rmac_frms_q2;
0234     __le64 rmac_frms_q3;
0235     __le64 rmac_frms_q4;
0236     __le64 rmac_frms_q5;
0237     __le64 rmac_frms_q6;
0238     __le64 rmac_frms_q7;
0239     __le16 rmac_full_q3;
0240     __le16 rmac_full_q2;
0241     __le16 rmac_full_q1;
0242     __le16 rmac_full_q0;
0243     __le16 rmac_full_q7;
0244     __le16 rmac_full_q6;
0245     __le16 rmac_full_q5;
0246     __le16 rmac_full_q4;
0247     __le32 reserved_9;
0248     __le32 rmac_pause_cnt;
0249     __le64 rmac_xgmii_data_err_cnt;
0250     __le64 rmac_xgmii_ctrl_err_cnt;
0251     __le32 rmac_err_tcp;
0252     __le32 rmac_accepted_ip;
0253 
0254 /* PCI/PCI-X Read transaction statistics. */
0255     __le32 new_rd_req_cnt;
0256     __le32 rd_req_cnt;
0257     __le32 rd_rtry_cnt;
0258     __le32 new_rd_req_rtry_cnt;
0259 
0260 /* PCI/PCI-X Write/Read transaction statistics. */
0261     __le32 wr_req_cnt;
0262     __le32 wr_rtry_rd_ack_cnt;
0263     __le32 new_wr_req_rtry_cnt;
0264     __le32 new_wr_req_cnt;
0265     __le32 wr_disc_cnt;
0266     __le32 wr_rtry_cnt;
0267 
0268 /*  PCI/PCI-X Write / DMA Transaction statistics. */
0269     __le32 txp_wr_cnt;
0270     __le32 rd_rtry_wr_ack_cnt;
0271     __le32 txd_wr_cnt;
0272     __le32 txd_rd_cnt;
0273     __le32 rxd_wr_cnt;
0274     __le32 rxd_rd_cnt;
0275     __le32 rxf_wr_cnt;
0276     __le32 txf_rd_cnt;
0277 
0278 /* Tx MAC statistics overflow counters. */
0279     __le32 tmac_data_octets_oflow;
0280     __le32 tmac_frms_oflow;
0281     __le32 tmac_bcst_frms_oflow;
0282     __le32 tmac_mcst_frms_oflow;
0283     __le32 tmac_ucst_frms_oflow;
0284     __le32 tmac_ttl_octets_oflow;
0285     __le32 tmac_any_err_frms_oflow;
0286     __le32 tmac_nucst_frms_oflow;
0287     __le64 tmac_vlan_frms;
0288     __le32 tmac_drop_ip_oflow;
0289     __le32 tmac_vld_ip_oflow;
0290     __le32 tmac_rst_tcp_oflow;
0291     __le32 tmac_icmp_oflow;
0292     __le32 tpa_unknown_protocol;
0293     __le32 tmac_udp_oflow;
0294     __le32 reserved_10;
0295     __le32 tpa_parse_failure;
0296 
0297 /* Rx MAC Statistics overflow counters. */
0298     __le32 rmac_data_octets_oflow;
0299     __le32 rmac_vld_frms_oflow;
0300     __le32 rmac_vld_bcst_frms_oflow;
0301     __le32 rmac_vld_mcst_frms_oflow;
0302     __le32 rmac_accepted_ucst_frms_oflow;
0303     __le32 rmac_ttl_octets_oflow;
0304     __le32 rmac_discarded_frms_oflow;
0305     __le32 rmac_accepted_nucst_frms_oflow;
0306     __le32 rmac_usized_frms_oflow;
0307     __le32 rmac_drop_events_oflow;
0308     __le32 rmac_frag_frms_oflow;
0309     __le32 rmac_osized_frms_oflow;
0310     __le32 rmac_ip_oflow;
0311     __le32 rmac_jabber_frms_oflow;
0312     __le32 rmac_icmp_oflow;
0313     __le32 rmac_drop_ip_oflow;
0314     __le32 rmac_err_drp_udp_oflow;
0315     __le32 rmac_udp_oflow;
0316     __le32 reserved_11;
0317     __le32 rmac_pause_cnt_oflow;
0318     __le64 rmac_ttl_1519_4095_frms;
0319     __le64 rmac_ttl_4096_8191_frms;
0320     __le64 rmac_ttl_8192_max_frms;
0321     __le64 rmac_ttl_gt_max_frms;
0322     __le64 rmac_osized_alt_frms;
0323     __le64 rmac_jabber_alt_frms;
0324     __le64 rmac_gt_max_alt_frms;
0325     __le64 rmac_vlan_frms;
0326     __le32 rmac_len_discard;
0327     __le32 rmac_fcs_discard;
0328     __le32 rmac_pf_discard;
0329     __le32 rmac_da_discard;
0330     __le32 rmac_red_discard;
0331     __le32 rmac_rts_discard;
0332     __le32 reserved_12;
0333     __le32 rmac_ingm_full_discard;
0334     __le32 reserved_13;
0335     __le32 rmac_accepted_ip_oflow;
0336     __le32 reserved_14;
0337     __le32 link_fault_cnt;
0338     u8  buffer[20];
0339     struct swStat sw_stat;
0340     struct xpakStat xpak_stat;
0341 };
0342 
0343 /* Default value for 'vlan_strip_tag' configuration parameter */
0344 #define NO_STRIP_IN_PROMISC 2
0345 
0346 /*
0347  * Structures representing different init time configuration
0348  * parameters of the NIC.
0349  */
0350 
0351 #define MAX_TX_FIFOS 8
0352 #define MAX_RX_RINGS 8
0353 
0354 #define FIFO_DEFAULT_NUM    5
0355 #define FIFO_UDP_MAX_NUM            2 /* 0 - even, 1 -odd ports */
0356 #define FIFO_OTHER_MAX_NUM          1
0357 
0358 
0359 #define MAX_RX_DESC_1  (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 128)
0360 #define MAX_RX_DESC_2  (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 86)
0361 #define MAX_TX_DESC    (MAX_AVAILABLE_TXDS)
0362 
0363 /* FIFO mappings for all possible number of fifos configured */
0364 static const int fifo_map[][MAX_TX_FIFOS] = {
0365     {0, 0, 0, 0, 0, 0, 0, 0},
0366     {0, 0, 0, 0, 1, 1, 1, 1},
0367     {0, 0, 0, 1, 1, 1, 2, 2},
0368     {0, 0, 1, 1, 2, 2, 3, 3},
0369     {0, 0, 1, 1, 2, 2, 3, 4},
0370     {0, 0, 1, 1, 2, 3, 4, 5},
0371     {0, 0, 1, 2, 3, 4, 5, 6},
0372     {0, 1, 2, 3, 4, 5, 6, 7},
0373 };
0374 
0375 static const u16 fifo_selector[MAX_TX_FIFOS] = {0, 1, 3, 3, 7, 7, 7, 7};
0376 
0377 /* Maintains Per FIFO related information. */
0378 struct tx_fifo_config {
0379 #define MAX_AVAILABLE_TXDS  8192
0380     u32 fifo_len;       /* specifies len of FIFO up to 8192, ie no of TxDLs */
0381 /* Priority definition */
0382 #define TX_FIFO_PRI_0               0   /*Highest */
0383 #define TX_FIFO_PRI_1               1
0384 #define TX_FIFO_PRI_2               2
0385 #define TX_FIFO_PRI_3               3
0386 #define TX_FIFO_PRI_4               4
0387 #define TX_FIFO_PRI_5               5
0388 #define TX_FIFO_PRI_6               6
0389 #define TX_FIFO_PRI_7               7   /*lowest */
0390     u8 fifo_priority;   /* specifies pointer level for FIFO */
0391     /* user should not set twos fifos with same pri */
0392     u8 f_no_snoop;
0393 #define NO_SNOOP_TXD                0x01
0394 #define NO_SNOOP_TXD_BUFFER          0x02
0395 };
0396 
0397 
0398 /* Maintains per Ring related information */
0399 struct rx_ring_config {
0400     u32 num_rxd;        /*No of RxDs per Rx Ring */
0401 #define RX_RING_PRI_0               0   /* highest */
0402 #define RX_RING_PRI_1               1
0403 #define RX_RING_PRI_2               2
0404 #define RX_RING_PRI_3               3
0405 #define RX_RING_PRI_4               4
0406 #define RX_RING_PRI_5               5
0407 #define RX_RING_PRI_6               6
0408 #define RX_RING_PRI_7               7   /* lowest */
0409 
0410     u8 ring_priority;   /*Specifies service priority of ring */
0411     /* OSM should not set any two rings with same priority */
0412     u8 ring_org;        /*Organization of ring */
0413 #define RING_ORG_BUFF1      0x01
0414 #define RX_RING_ORG_BUFF3   0x03
0415 #define RX_RING_ORG_BUFF5   0x05
0416 
0417     u8 f_no_snoop;
0418 #define NO_SNOOP_RXD                0x01
0419 #define NO_SNOOP_RXD_BUFFER         0x02
0420 };
0421 
0422 /* This structure provides contains values of the tunable parameters
0423  * of the H/W
0424  */
0425 struct config_param {
0426 /* Tx Side */
0427     u32 tx_fifo_num;    /*Number of Tx FIFOs */
0428 
0429     /* 0-No steering, 1-Priority steering, 2-Default fifo map */
0430 #define NO_STEERING             0
0431 #define TX_PRIORITY_STEERING            0x1
0432 #define TX_DEFAULT_STEERING             0x2
0433     u8 tx_steering_type;
0434 
0435     u8 fifo_mapping[MAX_TX_FIFOS];
0436     struct tx_fifo_config tx_cfg[MAX_TX_FIFOS]; /*Per-Tx FIFO config */
0437     u32 max_txds;       /*Max no. of Tx buffer descriptor per TxDL */
0438     u64 tx_intr_type;
0439 #define INTA    0
0440 #define MSI_X   2
0441     u8 intr_type;
0442     u8 napi;
0443 
0444     /* Specifies if Tx Intr is UTILZ or PER_LIST type. */
0445 
0446 /* Rx Side */
0447     u32 rx_ring_num;    /*Number of receive rings */
0448 #define MAX_RX_BLOCKS_PER_RING  150
0449 
0450     struct rx_ring_config rx_cfg[MAX_RX_RINGS]; /*Per-Rx Ring config */
0451 
0452 #define HEADER_ETHERNET_II_802_3_SIZE 14
0453 #define HEADER_802_2_SIZE              3
0454 #define HEADER_SNAP_SIZE               5
0455 #define HEADER_VLAN_SIZE               4
0456 
0457 #define MIN_MTU                       46
0458 #define MAX_PYLD                    1500
0459 #define MAX_MTU                     (MAX_PYLD+18)
0460 #define MAX_MTU_VLAN                (MAX_PYLD+22)
0461 #define MAX_PYLD_JUMBO              9600
0462 #define MAX_MTU_JUMBO               (MAX_PYLD_JUMBO+18)
0463 #define MAX_MTU_JUMBO_VLAN          (MAX_PYLD_JUMBO+22)
0464     u16 bus_speed;
0465     int max_mc_addr;    /* xena=64 herc=256 */
0466     int max_mac_addr;   /* xena=16 herc=64 */
0467     int mc_start_offset;    /* xena=16 herc=64 */
0468     u8 multiq;
0469 };
0470 
0471 /* Structure representing MAC Addrs */
0472 struct mac_addr {
0473     u8 mac_addr[ETH_ALEN];
0474 };
0475 
0476 /* Structure that represent every FIFO element in the BAR1
0477  * Address location.
0478  */
0479 struct TxFIFO_element {
0480     u64 TxDL_Pointer;
0481 
0482     u64 List_Control;
0483 #define TX_FIFO_LAST_TXD_NUM( val)     vBIT(val,0,8)
0484 #define TX_FIFO_FIRST_LIST             s2BIT(14)
0485 #define TX_FIFO_LAST_LIST              s2BIT(15)
0486 #define TX_FIFO_FIRSTNLAST_LIST        vBIT(3,14,2)
0487 #define TX_FIFO_SPECIAL_FUNC           s2BIT(23)
0488 #define TX_FIFO_DS_NO_SNOOP            s2BIT(31)
0489 #define TX_FIFO_BUFF_NO_SNOOP          s2BIT(30)
0490 };
0491 
0492 /* Tx descriptor structure */
0493 struct TxD {
0494     u64 Control_1;
0495 /* bit mask */
0496 #define TXD_LIST_OWN_XENA       s2BIT(7)
0497 #define TXD_T_CODE              (s2BIT(12)|s2BIT(13)|s2BIT(14)|s2BIT(15))
0498 #define TXD_T_CODE_OK(val)      (|(val & TXD_T_CODE))
0499 #define GET_TXD_T_CODE(val)     ((val & TXD_T_CODE)<<12)
0500 #define TXD_GATHER_CODE         (s2BIT(22) | s2BIT(23))
0501 #define TXD_GATHER_CODE_FIRST   s2BIT(22)
0502 #define TXD_GATHER_CODE_LAST    s2BIT(23)
0503 #define TXD_TCP_LSO_EN          s2BIT(30)
0504 #define TXD_UDP_COF_EN          s2BIT(31)
0505 #define TXD_UFO_EN      s2BIT(31) | s2BIT(30)
0506 #define TXD_TCP_LSO_MSS(val)    vBIT(val,34,14)
0507 #define TXD_UFO_MSS(val)    vBIT(val,34,14)
0508 #define TXD_BUFFER0_SIZE(val)   vBIT(val,48,16)
0509 
0510     u64 Control_2;
0511 #define TXD_TX_CKO_CONTROL      (s2BIT(5)|s2BIT(6)|s2BIT(7))
0512 #define TXD_TX_CKO_IPV4_EN      s2BIT(5)
0513 #define TXD_TX_CKO_TCP_EN       s2BIT(6)
0514 #define TXD_TX_CKO_UDP_EN       s2BIT(7)
0515 #define TXD_VLAN_ENABLE         s2BIT(15)
0516 #define TXD_VLAN_TAG(val)       vBIT(val,16,16)
0517 #define TXD_INT_NUMBER(val)     vBIT(val,34,6)
0518 #define TXD_INT_TYPE_PER_LIST   s2BIT(47)
0519 #define TXD_INT_TYPE_UTILZ      s2BIT(46)
0520 #define TXD_SET_MARKER         vBIT(0x6,0,4)
0521 
0522     u64 Buffer_Pointer;
0523     u64 Host_Control;   /* reserved for host */
0524 };
0525 
0526 /* Structure to hold the phy and virt addr of every TxDL. */
0527 struct list_info_hold {
0528     dma_addr_t list_phy_addr;
0529     void *list_virt_addr;
0530 };
0531 
0532 /* Rx descriptor structure for 1 buffer mode */
0533 struct RxD_t {
0534     u64 Host_Control;   /* reserved for host */
0535     u64 Control_1;
0536 #define RXD_OWN_XENA            s2BIT(7)
0537 #define RXD_T_CODE              (s2BIT(12)|s2BIT(13)|s2BIT(14)|s2BIT(15))
0538 #define RXD_FRAME_PROTO         vBIT(0xFFFF,24,8)
0539 #define RXD_FRAME_VLAN_TAG      s2BIT(24)
0540 #define RXD_FRAME_PROTO_IPV4    s2BIT(27)
0541 #define RXD_FRAME_PROTO_IPV6    s2BIT(28)
0542 #define RXD_FRAME_IP_FRAG   s2BIT(29)
0543 #define RXD_FRAME_PROTO_TCP     s2BIT(30)
0544 #define RXD_FRAME_PROTO_UDP     s2BIT(31)
0545 #define TCP_OR_UDP_FRAME        (RXD_FRAME_PROTO_TCP | RXD_FRAME_PROTO_UDP)
0546 #define RXD_GET_L3_CKSUM(val)   ((u16)(val>> 16) & 0xFFFF)
0547 #define RXD_GET_L4_CKSUM(val)   ((u16)(val) & 0xFFFF)
0548 
0549     u64 Control_2;
0550 #define THE_RXD_MARK        0x3
0551 #define SET_RXD_MARKER      vBIT(THE_RXD_MARK, 0, 2)
0552 #define GET_RXD_MARKER(ctrl)    ((ctrl & SET_RXD_MARKER) >> 62)
0553 
0554 #define MASK_VLAN_TAG           vBIT(0xFFFF,48,16)
0555 #define SET_VLAN_TAG(val)       vBIT(val,48,16)
0556 #define SET_NUM_TAG(val)       vBIT(val,16,32)
0557 
0558 
0559 };
0560 /* Rx descriptor structure for 1 buffer mode */
0561 struct RxD1 {
0562     struct RxD_t h;
0563 
0564 #define MASK_BUFFER0_SIZE_1       vBIT(0x3FFF,2,14)
0565 #define SET_BUFFER0_SIZE_1(val)   vBIT(val,2,14)
0566 #define RXD_GET_BUFFER0_SIZE_1(_Control_2) \
0567     (u16)((_Control_2 & MASK_BUFFER0_SIZE_1) >> 48)
0568     u64 Buffer0_ptr;
0569 };
0570 /* Rx descriptor structure for 3 or 2 buffer mode */
0571 
0572 struct RxD3 {
0573     struct RxD_t h;
0574 
0575 #define MASK_BUFFER0_SIZE_3       vBIT(0xFF,2,14)
0576 #define MASK_BUFFER1_SIZE_3       vBIT(0xFFFF,16,16)
0577 #define MASK_BUFFER2_SIZE_3       vBIT(0xFFFF,32,16)
0578 #define SET_BUFFER0_SIZE_3(val)   vBIT(val,8,8)
0579 #define SET_BUFFER1_SIZE_3(val)   vBIT(val,16,16)
0580 #define SET_BUFFER2_SIZE_3(val)   vBIT(val,32,16)
0581 #define RXD_GET_BUFFER0_SIZE_3(Control_2) \
0582     (u8)((Control_2 & MASK_BUFFER0_SIZE_3) >> 48)
0583 #define RXD_GET_BUFFER1_SIZE_3(Control_2) \
0584     (u16)((Control_2 & MASK_BUFFER1_SIZE_3) >> 32)
0585 #define RXD_GET_BUFFER2_SIZE_3(Control_2) \
0586     (u16)((Control_2 & MASK_BUFFER2_SIZE_3) >> 16)
0587 #define BUF0_LEN    40
0588 #define BUF1_LEN    1
0589 
0590     u64 Buffer0_ptr;
0591     u64 Buffer1_ptr;
0592     u64 Buffer2_ptr;
0593 };
0594 
0595 
0596 /* Structure that represents the Rx descriptor block which contains
0597  * 128 Rx descriptors.
0598  */
0599 struct RxD_block {
0600 #define MAX_RXDS_PER_BLOCK_1            127
0601     struct RxD1 rxd[MAX_RXDS_PER_BLOCK_1];
0602 
0603     u64 reserved_0;
0604 #define END_OF_BLOCK    0xFEFFFFFFFFFFFFFFULL
0605     u64 reserved_1;     /* 0xFEFFFFFFFFFFFFFF to mark last
0606                  * Rxd in this blk */
0607     u64 reserved_2_pNext_RxD_block; /* Logical ptr to next */
0608     u64 pNext_RxD_Blk_physical; /* Buff0_ptr.In a 32 bit arch
0609                      * the upper 32 bits should
0610                      * be 0 */
0611 };
0612 
0613 #define SIZE_OF_BLOCK   4096
0614 
0615 #define RXD_MODE_1  0 /* One Buffer mode */
0616 #define RXD_MODE_3B 1 /* Two Buffer mode */
0617 
0618 /* Structure to hold virtual addresses of Buf0 and Buf1 in
0619  * 2buf mode. */
0620 struct buffAdd {
0621     void *ba_0_org;
0622     void *ba_1_org;
0623     void *ba_0;
0624     void *ba_1;
0625 };
0626 
0627 /* Structure which stores all the MAC control parameters */
0628 
0629 /* This structure stores the offset of the RxD in the ring
0630  * from which the Rx Interrupt processor can start picking
0631  * up the RxDs for processing.
0632  */
0633 struct rx_curr_get_info {
0634     u32 block_index;
0635     u32 offset;
0636     u32 ring_len;
0637 };
0638 
0639 struct rx_curr_put_info {
0640     u32 block_index;
0641     u32 offset;
0642     u32 ring_len;
0643 };
0644 
0645 /* This structure stores the offset of the TxDl in the FIFO
0646  * from which the Tx Interrupt processor can start picking
0647  * up the TxDLs for send complete interrupt processing.
0648  */
0649 struct tx_curr_get_info {
0650     u32 offset;
0651     u32 fifo_len;
0652 };
0653 
0654 struct tx_curr_put_info {
0655     u32 offset;
0656     u32 fifo_len;
0657 };
0658 
0659 struct rxd_info {
0660     void *virt_addr;
0661     dma_addr_t dma_addr;
0662 };
0663 
0664 /* Structure that holds the Phy and virt addresses of the Blocks */
0665 struct rx_block_info {
0666     void *block_virt_addr;
0667     dma_addr_t block_dma_addr;
0668     struct rxd_info *rxds;
0669 };
0670 
0671 /* Data structure to represent a LRO session */
0672 struct lro {
0673     struct sk_buff  *parent;
0674     struct sk_buff  *last_frag;
0675     u8      *l2h;
0676     struct iphdr    *iph;
0677     struct tcphdr   *tcph;
0678     u32     tcp_next_seq;
0679     __be32      tcp_ack;
0680     int     total_len;
0681     int     frags_len;
0682     int     sg_num;
0683     int     in_use;
0684     __be16      window;
0685     u16             vlan_tag;
0686     u32     cur_tsval;
0687     __be32      cur_tsecr;
0688     u8      saw_ts;
0689 } ____cacheline_aligned;
0690 
0691 /* Ring specific structure */
0692 struct ring_info {
0693     /* The ring number */
0694     int ring_no;
0695 
0696     /* per-ring buffer counter */
0697     u32 rx_bufs_left;
0698 
0699 #define MAX_LRO_SESSIONS       32
0700     struct lro lro0_n[MAX_LRO_SESSIONS];
0701     u8      lro;
0702 
0703     /* copy of sp->rxd_mode flag */
0704     int rxd_mode;
0705 
0706     /* Number of rxds per block for the rxd_mode */
0707     int rxd_count;
0708 
0709     /* copy of sp pointer */
0710     struct s2io_nic *nic;
0711 
0712     /* copy of sp->dev pointer */
0713     struct net_device *dev;
0714 
0715     /* copy of sp->pdev pointer */
0716     struct pci_dev *pdev;
0717 
0718     /* Per ring napi struct */
0719     struct napi_struct napi;
0720 
0721     unsigned long interrupt_count;
0722 
0723     /*
0724      *  Place holders for the virtual and physical addresses of
0725      *  all the Rx Blocks
0726      */
0727     struct rx_block_info rx_blocks[MAX_RX_BLOCKS_PER_RING];
0728     int block_count;
0729     int pkt_cnt;
0730 
0731     /*
0732      * Put pointer info which indictes which RxD has to be replenished
0733      * with a new buffer.
0734      */
0735     struct rx_curr_put_info rx_curr_put_info;
0736 
0737     /*
0738      * Get pointer info which indictes which is the last RxD that was
0739      * processed by the driver.
0740      */
0741     struct rx_curr_get_info rx_curr_get_info;
0742 
0743     /* interface MTU value */
0744         unsigned mtu;
0745 
0746     /* Buffer Address store. */
0747     struct buffAdd **ba;
0748 } ____cacheline_aligned;
0749 
0750 /* Fifo specific structure */
0751 struct fifo_info {
0752     /* FIFO number */
0753     int fifo_no;
0754 
0755     /* Maximum TxDs per TxDL */
0756     int max_txds;
0757 
0758     /* Place holder of all the TX List's Phy and Virt addresses. */
0759     struct list_info_hold *list_info;
0760 
0761     /*
0762      * Current offset within the tx FIFO where driver would write
0763      * new Tx frame
0764      */
0765     struct tx_curr_put_info tx_curr_put_info;
0766 
0767     /*
0768      * Current offset within tx FIFO from where the driver would start freeing
0769      * the buffers
0770      */
0771     struct tx_curr_get_info tx_curr_get_info;
0772 #define FIFO_QUEUE_START 0
0773 #define FIFO_QUEUE_STOP 1
0774     int queue_state;
0775 
0776     /* copy of sp->dev pointer */
0777     struct net_device *dev;
0778 
0779     /* copy of multiq status */
0780     u8 multiq;
0781 
0782     /* Per fifo lock */
0783     spinlock_t tx_lock;
0784 
0785     /* Per fifo UFO in band structure */
0786     u64 *ufo_in_band_v;
0787 
0788     struct s2io_nic *nic;
0789 } ____cacheline_aligned;
0790 
0791 /* Information related to the Tx and Rx FIFOs and Rings of Xena
0792  * is maintained in this structure.
0793  */
0794 struct mac_info {
0795 /* tx side stuff */
0796     /* logical pointer of start of each Tx FIFO */
0797     struct TxFIFO_element __iomem *tx_FIFO_start[MAX_TX_FIFOS];
0798 
0799     /* Fifo specific structure */
0800     struct fifo_info fifos[MAX_TX_FIFOS];
0801 
0802     /* Save virtual address of TxD page with zero DMA addr(if any) */
0803     void *zerodma_virt_addr;
0804 
0805 /* rx side stuff */
0806     /* Ring specific structure */
0807     struct ring_info rings[MAX_RX_RINGS];
0808 
0809     u16 rmac_pause_time;
0810     u16 mc_pause_threshold_q0q3;
0811     u16 mc_pause_threshold_q4q7;
0812 
0813     void *stats_mem;    /* orignal pointer to allocated mem */
0814     dma_addr_t stats_mem_phy;   /* Physical address of the stat block */
0815     u32 stats_mem_sz;
0816     struct stat_block *stats_info;  /* Logical address of the stat block */
0817 };
0818 
0819 /* Default Tunable parameters of the NIC. */
0820 #define DEFAULT_FIFO_0_LEN 4096
0821 #define DEFAULT_FIFO_1_7_LEN 512
0822 #define SMALL_BLK_CNT   30
0823 #define LARGE_BLK_CNT   100
0824 
0825 /*
0826  * Structure to keep track of the MSI-X vectors and the corresponding
0827  * argument registered against each vector
0828  */
0829 #define MAX_REQUESTED_MSI_X 9
0830 struct s2io_msix_entry
0831 {
0832     u16 vector;
0833     u16 entry;
0834     void *arg;
0835 
0836     u8 type;
0837 #define        MSIX_ALARM_TYPE         1
0838 #define        MSIX_RING_TYPE          2
0839 
0840     u8 in_use;
0841 #define MSIX_REGISTERED_SUCCESS 0xAA
0842 };
0843 
0844 struct msix_info_st {
0845     u64 addr;
0846     u64 data;
0847 };
0848 
0849 /* These flags represent the devices temporary state */
0850 enum s2io_device_state_t
0851 {
0852     __S2IO_STATE_LINK_TASK=0,
0853     __S2IO_STATE_CARD_UP
0854 };
0855 
0856 /* Structure representing one instance of the NIC */
0857 struct s2io_nic {
0858     int rxd_mode;
0859     /*
0860      * Count of packets to be processed in a given iteration, it will be indicated
0861      * by the quota field of the device structure when NAPI is enabled.
0862      */
0863     int pkts_to_process;
0864     struct net_device *dev;
0865     struct mac_info mac_control;
0866     struct config_param config;
0867     struct pci_dev *pdev;
0868     void __iomem *bar0;
0869     void __iomem *bar1;
0870 #define MAX_MAC_SUPPORTED   16
0871 #define MAX_SUPPORTED_MULTICASTS MAX_MAC_SUPPORTED
0872 
0873     struct mac_addr def_mac_addr[256];
0874 
0875     struct net_device_stats stats;
0876     int device_enabled_once;
0877 
0878     char name[60];
0879 
0880     /* Timer that handles I/O errors/exceptions */
0881     struct timer_list alarm_timer;
0882 
0883     /* Space to back up the PCI config space */
0884     u32 config_space[256 / sizeof(u32)];
0885 
0886 #define PROMISC     1
0887 #define ALL_MULTI   2
0888 
0889 #define MAX_ADDRS_SUPPORTED 64
0890     u16 mc_addr_count;
0891 
0892     u16 m_cast_flg;
0893     u16 all_multi_pos;
0894     u16 promisc_flg;
0895 
0896     /*  Restart timer, used to restart NIC if the device is stuck and
0897      *  a schedule task that will set the correct Link state once the
0898      *  NIC's PHY has stabilized after a state change.
0899      */
0900     struct work_struct rst_timer_task;
0901     struct work_struct set_link_task;
0902 
0903     /* Flag that can be used to turn on or turn off the Rx checksum
0904      * offload feature.
0905      */
0906     int rx_csum;
0907 
0908     /* Below variables are used for fifo selection to transmit a packet */
0909     u16 fifo_selector[MAX_TX_FIFOS];
0910 
0911     /* Total fifos for tcp packets */
0912     u8 total_tcp_fifos;
0913 
0914     /*
0915     * Beginning index of udp for udp packets
0916     * Value will be equal to
0917     * (tx_fifo_num - FIFO_UDP_MAX_NUM - FIFO_OTHER_MAX_NUM)
0918     */
0919     u8 udp_fifo_idx;
0920 
0921     u8 total_udp_fifos;
0922 
0923     /*
0924      * Beginning index of fifo for all other packets
0925      * Value will be equal to (tx_fifo_num - FIFO_OTHER_MAX_NUM)
0926     */
0927     u8 other_fifo_idx;
0928 
0929     struct napi_struct napi;
0930     /*  after blink, the adapter must be restored with original
0931      *  values.
0932      */
0933     u64 adapt_ctrl_org;
0934 
0935     /* Last known link state. */
0936     u16 last_link_state;
0937 #define LINK_DOWN   1
0938 #define LINK_UP     2
0939 
0940     int task_flag;
0941     unsigned long long start_time;
0942     int vlan_strip_flag;
0943 #define MSIX_FLG                0xA5
0944     int num_entries;
0945     struct msix_entry *entries;
0946     int msi_detected;
0947     wait_queue_head_t msi_wait;
0948     struct s2io_msix_entry *s2io_entries;
0949     char desc[MAX_REQUESTED_MSI_X][25];
0950 
0951     int avail_msix_vectors; /* No. of MSI-X vectors granted by system */
0952 
0953     struct msix_info_st msix_info[0x3f];
0954 
0955 #define XFRAME_I_DEVICE     1
0956 #define XFRAME_II_DEVICE    2
0957     u8 device_type;
0958 
0959     unsigned long   clubbed_frms_cnt;
0960     unsigned long   sending_both;
0961     u16     lro_max_aggr_per_sess;
0962     volatile unsigned long state;
0963     u64     general_int_mask;
0964 
0965 #define VPD_STRING_LEN 80
0966     u8  product_name[VPD_STRING_LEN];
0967     u8  serial_num[VPD_STRING_LEN];
0968 };
0969 
0970 #define RESET_ERROR 1
0971 #define CMD_ERROR   2
0972 
0973 /*
0974  * Some registers have to be written in a particular order to
0975  * expect correct hardware operation. The macro SPECIAL_REG_WRITE
0976  * is used to perform such ordered writes. Defines UF (Upper First)
0977  * and LF (Lower First) will be used to specify the required write order.
0978  */
0979 #define UF  1
0980 #define LF  2
0981 static inline void SPECIAL_REG_WRITE(u64 val, void __iomem *addr, int order)
0982 {
0983     if (order == LF) {
0984         writel((u32) (val), addr);
0985         (void) readl(addr);
0986         writel((u32) (val >> 32), (addr + 4));
0987         (void) readl(addr + 4);
0988     } else {
0989         writel((u32) (val >> 32), (addr + 4));
0990         (void) readl(addr + 4);
0991         writel((u32) (val), addr);
0992         (void) readl(addr);
0993     }
0994 }
0995 
0996 /*  Interrupt related values of Xena */
0997 
0998 #define ENABLE_INTRS    1
0999 #define DISABLE_INTRS   2
1000 
1001 /*  Highest level interrupt blocks */
1002 #define TX_PIC_INTR     (0x0001<<0)
1003 #define TX_DMA_INTR     (0x0001<<1)
1004 #define TX_MAC_INTR     (0x0001<<2)
1005 #define TX_XGXS_INTR    (0x0001<<3)
1006 #define TX_TRAFFIC_INTR (0x0001<<4)
1007 #define RX_PIC_INTR     (0x0001<<5)
1008 #define RX_DMA_INTR     (0x0001<<6)
1009 #define RX_MAC_INTR     (0x0001<<7)
1010 #define RX_XGXS_INTR    (0x0001<<8)
1011 #define RX_TRAFFIC_INTR (0x0001<<9)
1012 #define MC_INTR         (0x0001<<10)
1013 #define ENA_ALL_INTRS    (   TX_PIC_INTR     | \
1014                             TX_DMA_INTR     | \
1015                             TX_MAC_INTR     | \
1016                             TX_XGXS_INTR    | \
1017                             TX_TRAFFIC_INTR | \
1018                             RX_PIC_INTR     | \
1019                             RX_DMA_INTR     | \
1020                             RX_MAC_INTR     | \
1021                             RX_XGXS_INTR    | \
1022                             RX_TRAFFIC_INTR | \
1023                             MC_INTR )
1024 
1025 /*  Interrupt masks for the general interrupt mask register */
1026 #define DISABLE_ALL_INTRS   0xFFFFFFFFFFFFFFFFULL
1027 
1028 #define TXPIC_INT_M         s2BIT(0)
1029 #define TXDMA_INT_M         s2BIT(1)
1030 #define TXMAC_INT_M         s2BIT(2)
1031 #define TXXGXS_INT_M        s2BIT(3)
1032 #define TXTRAFFIC_INT_M     s2BIT(8)
1033 #define PIC_RX_INT_M        s2BIT(32)
1034 #define RXDMA_INT_M         s2BIT(33)
1035 #define RXMAC_INT_M         s2BIT(34)
1036 #define MC_INT_M            s2BIT(35)
1037 #define RXXGXS_INT_M        s2BIT(36)
1038 #define RXTRAFFIC_INT_M     s2BIT(40)
1039 
1040 /*  PIC level Interrupts TODO*/
1041 
1042 /*  DMA level Inressupts */
1043 #define TXDMA_PFC_INT_M     s2BIT(0)
1044 #define TXDMA_PCC_INT_M     s2BIT(2)
1045 
1046 /*  PFC block interrupts */
1047 #define PFC_MISC_ERR_1      s2BIT(0)    /* Interrupt to indicate FIFO full */
1048 
1049 /* PCC block interrupts. */
1050 #define PCC_FB_ECC_ERR     vBIT(0xff, 16, 8)    /* Interrupt to indicate
1051                            PCC_FB_ECC Error. */
1052 
1053 #define RXD_GET_VLAN_TAG(Control_2) (u16)(Control_2 & MASK_VLAN_TAG)
1054 /*
1055  * Prototype declaration.
1056  */
1057 static int s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre);
1058 static void s2io_rem_nic(struct pci_dev *pdev);
1059 static int init_shared_mem(struct s2io_nic *sp);
1060 static void free_shared_mem(struct s2io_nic *sp);
1061 static int init_nic(struct s2io_nic *nic);
1062 static int rx_intr_handler(struct ring_info *ring_data, int budget);
1063 static void s2io_txpic_intr_handle(struct s2io_nic *sp);
1064 static void tx_intr_handler(struct fifo_info *fifo_data);
1065 static void s2io_handle_errors(void * dev_id);
1066 
1067 static void s2io_tx_watchdog(struct net_device *dev, unsigned int txqueue);
1068 static void s2io_set_multicast(struct net_device *dev, bool may_sleep);
1069 static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp);
1070 static void s2io_link(struct s2io_nic * sp, int link);
1071 static void s2io_reset(struct s2io_nic * sp);
1072 static int s2io_poll_msix(struct napi_struct *napi, int budget);
1073 static int s2io_poll_inta(struct napi_struct *napi, int budget);
1074 static void s2io_init_pci(struct s2io_nic * sp);
1075 static int do_s2io_prog_unicast(struct net_device *dev, const u8 *addr);
1076 static void s2io_alarm_handle(struct timer_list *t);
1077 static irqreturn_t
1078 s2io_msix_ring_handle(int irq, void *dev_id);
1079 static irqreturn_t
1080 s2io_msix_fifo_handle(int irq, void *dev_id);
1081 static irqreturn_t s2io_isr(int irq, void *dev_id);
1082 static int verify_xena_quiescence(struct s2io_nic *sp);
1083 static const struct ethtool_ops netdev_ethtool_ops;
1084 static void s2io_set_link(struct work_struct *work);
1085 static int s2io_set_swapper(struct s2io_nic * sp);
1086 static void s2io_card_down(struct s2io_nic *nic);
1087 static int s2io_card_up(struct s2io_nic *nic);
1088 static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
1089                  int bit_state, bool may_sleep);
1090 static int s2io_add_isr(struct s2io_nic * sp);
1091 static void s2io_rem_isr(struct s2io_nic * sp);
1092 
1093 static void restore_xmsi_data(struct s2io_nic *nic);
1094 static void do_s2io_store_unicast_mc(struct s2io_nic *sp);
1095 static void do_s2io_restore_unicast_mc(struct s2io_nic *sp);
1096 static u64 do_s2io_read_unicast_mc(struct s2io_nic *sp, int offset);
1097 static int do_s2io_add_mc(struct s2io_nic *sp, u8 *addr);
1098 static int do_s2io_add_mac(struct s2io_nic *sp, u64 addr, int offset);
1099 static int do_s2io_delete_unicast_mc(struct s2io_nic *sp, u64 addr);
1100 
1101 static int s2io_club_tcp_session(struct ring_info *ring_data, u8 *buffer,
1102     u8 **tcp, u32 *tcp_len, struct lro **lro, struct RxD_t *rxdp,
1103     struct s2io_nic *sp);
1104 static void clear_lro_session(struct lro *lro);
1105 static void queue_rx_frame(struct sk_buff *skb, u16 vlan_tag);
1106 static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro);
1107 static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
1108                struct sk_buff *skb, u32 tcp_len);
1109 static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring);
1110 
1111 static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev,
1112                                   pci_channel_state_t state);
1113 static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev);
1114 static void s2io_io_resume(struct pci_dev *pdev);
1115 
1116 #define s2io_tcp_mss(skb) skb_shinfo(skb)->gso_size
1117 #define s2io_udp_mss(skb) skb_shinfo(skb)->gso_size
1118 #define s2io_offload_type(skb) skb_shinfo(skb)->gso_type
1119 
1120 #define S2IO_PARM_INT(X, def_val) \
1121     static unsigned int X = def_val;\
1122         module_param(X , uint, 0);
1123 
1124 #endif              /* _S2IO_H */
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