myricom/myri10ge/myri10ge_mcp.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef __MYRI10GE_MCP_H__
0003 #define __MYRI10GE_MCP_H__
0004
0005 #define MXGEFW_VERSION_MAJOR    1
0006 #define MXGEFW_VERSION_MINOR    4
0007
0008 /* 8 Bytes */
0009 struct mcp_dma_addr {
0010     __be32 high;
0011     __be32 low;
0012 };
0013
0014 /* 4 Bytes */
0015 struct mcp_slot {
0016     __sum16 checksum;
0017     __be16 length;
0018 };
0019
0020 /* 64 Bytes */
0021 struct mcp_cmd {
0022     __be32 cmd;
0023     __be32 data0;       /* will be low portion if data > 32 bits */
0024     /* 8 */
0025     __be32 data1;       /* will be high portion if data > 32 bits */
0026     __be32 data2;       /* currently unused.. */
0027     /* 16 */
0028     struct mcp_dma_addr response_addr;
0029     /* 24 */
0030     u8 pad[40];
0031 };
0032
0033 /* 8 Bytes */
0034 struct mcp_cmd_response {
0035     __be32 data;
0036     __be32 result;
0037 };
0038
0039 /*
0040  * flags used in mcp_kreq_ether_send_t:
0041  *
0042  * The SMALL flag is only needed in the first segment. It is raised
0043  * for packets that are total less or equal 512 bytes.
0044  *
0045  * The CKSUM flag must be set in all segments.
0046  *
0047  * The PADDED flags is set if the packet needs to be padded, and it
0048  * must be set for all segments.
0049  *
0050  * The  MXGEFW_FLAGS_ALIGN_ODD must be set if the cumulative
0051  * length of all previous segments was odd.
0052  */
0053
0054 #define MXGEFW_FLAGS_SMALL      0x1
0055 #define MXGEFW_FLAGS_TSO_HDR    0x1
0056 #define MXGEFW_FLAGS_FIRST      0x2
0057 #define MXGEFW_FLAGS_ALIGN_ODD  0x4
0058 #define MXGEFW_FLAGS_CKSUM      0x8
0059 #define MXGEFW_FLAGS_TSO_LAST   0x8
0060 #define MXGEFW_FLAGS_NO_TSO     0x10
0061 #define MXGEFW_FLAGS_TSO_CHOP   0x10
0062 #define MXGEFW_FLAGS_TSO_PLD    0x20
0063
0064 #define MXGEFW_SEND_SMALL_SIZE  1520
0065 #define MXGEFW_MAX_MTU          9400
0066
0067 union mcp_pso_or_cumlen {
0068     u16 pseudo_hdr_offset;
0069     u16 cum_len;
0070 };
0071
0072 #define MXGEFW_MAX_SEND_DESC 12
0073 #define MXGEFW_PAD      2
0074
0075 /* 16 Bytes */
0076 struct mcp_kreq_ether_send {
0077     __be32 addr_high;
0078     __be32 addr_low;
0079     __be16 pseudo_hdr_offset;
0080     __be16 length;
0081     u8 pad;
0082     u8 rdma_count;
0083     u8 cksum_offset;    /* where to start computing cksum */
0084     u8 flags;       /* as defined above */
0085 };
0086
0087 /* 8 Bytes */
0088 struct mcp_kreq_ether_recv {
0089     __be32 addr_high;
0090     __be32 addr_low;
0091 };
0092
0093 /* Commands */
0094
0095 #define MXGEFW_BOOT_HANDOFF 0xfc0000
0096 #define MXGEFW_BOOT_DUMMY_RDMA  0xfc01c0
0097
0098 #define MXGEFW_ETH_CMD      0xf80000
0099 #define MXGEFW_ETH_SEND_4   0x200000
0100 #define MXGEFW_ETH_SEND_1   0x240000
0101 #define MXGEFW_ETH_SEND_2   0x280000
0102 #define MXGEFW_ETH_SEND_3   0x2c0000
0103 #define MXGEFW_ETH_RECV_SMALL   0x300000
0104 #define MXGEFW_ETH_RECV_BIG 0x340000
0105 #define MXGEFW_ETH_SEND_GO  0x380000
0106 #define MXGEFW_ETH_SEND_STOP    0x3C0000
0107
0108 #define MXGEFW_ETH_SEND(n)      (0x200000 + (((n) & 0x03) * 0x40000))
0109 #define MXGEFW_ETH_SEND_OFFSET(n)   (MXGEFW_ETH_SEND(n) - MXGEFW_ETH_SEND_4)
0110
0111 enum myri10ge_mcp_cmd_type {
0112     MXGEFW_CMD_NONE = 0,
0113     /* Reset the mcp, it is left in a safe state, waiting
0114      * for the driver to set all its parameters */
0115     MXGEFW_CMD_RESET = 1,
0116
0117     /* get the version number of the current firmware..
0118      * (may be available in the eeprom strings..? */
0119     MXGEFW_GET_MCP_VERSION = 2,
0120
0121     /* Parameters which must be set by the driver before it can
0122      * issue MXGEFW_CMD_ETHERNET_UP. They persist until the next
0123      * MXGEFW_CMD_RESET is issued */
0124
0125     MXGEFW_CMD_SET_INTRQ_DMA = 3,
0126     /* data0 = LSW of the host address
0127      * data1 = MSW of the host address
0128      * data2 = slice number if multiple slices are used
0129      */
0130
0131     MXGEFW_CMD_SET_BIG_BUFFER_SIZE = 4, /* in bytes, power of 2 */
0132     MXGEFW_CMD_SET_SMALL_BUFFER_SIZE = 5,   /* in bytes */
0133
0134     /* Parameters which refer to lanai SRAM addresses where the
0135      * driver must issue PIO writes for various things */
0136
0137     MXGEFW_CMD_GET_SEND_OFFSET = 6,
0138     MXGEFW_CMD_GET_SMALL_RX_OFFSET = 7,
0139     MXGEFW_CMD_GET_BIG_RX_OFFSET = 8,
0140     /* data0 = slice number if multiple slices are used */
0141
0142     MXGEFW_CMD_GET_IRQ_ACK_OFFSET = 9,
0143     MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET = 10,
0144
0145     /* Parameters which refer to rings stored on the MCP,
0146      * and whose size is controlled by the mcp */
0147
0148     MXGEFW_CMD_GET_SEND_RING_SIZE = 11, /* in bytes */
0149     MXGEFW_CMD_GET_RX_RING_SIZE = 12,   /* in bytes */
0150
0151     /* Parameters which refer to rings stored in the host,
0152      * and whose size is controlled by the host.  Note that
0153      * all must be physically contiguous and must contain
0154      * a power of 2 number of entries.  */
0155
0156     MXGEFW_CMD_SET_INTRQ_SIZE = 13, /* in bytes */
0157 #define MXGEFW_CMD_SET_INTRQ_SIZE_FLAG_NO_STRICT_SIZE_CHECK  (1 << 31)
0158
0159     /* command to bring ethernet interface up.  Above parameters
0160      * (plus mtu & mac address) must have been exchanged prior
0161      * to issuing this command  */
0162     MXGEFW_CMD_ETHERNET_UP = 14,
0163
0164     /* command to bring ethernet interface down.  No further sends
0165      * or receives may be processed until an MXGEFW_CMD_ETHERNET_UP
0166      * is issued, and all interrupt queues must be flushed prior
0167      * to ack'ing this command */
0168
0169     MXGEFW_CMD_ETHERNET_DOWN = 15,
0170
0171     /* commands the driver may issue live, without resetting
0172      * the nic.  Note that increasing the mtu "live" should
0173      * only be done if the driver has already supplied buffers
0174      * sufficiently large to handle the new mtu.  Decreasing
0175      * the mtu live is safe */
0176
0177     MXGEFW_CMD_SET_MTU = 16,
0178     MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET = 17, /* in microseconds */
0179     MXGEFW_CMD_SET_STATS_INTERVAL = 18, /* in microseconds */
0180     MXGEFW_CMD_SET_STATS_DMA_OBSOLETE = 19, /* replaced by SET_STATS_DMA_V2 */
0181
0182     MXGEFW_ENABLE_PROMISC = 20,
0183     MXGEFW_DISABLE_PROMISC = 21,
0184     MXGEFW_SET_MAC_ADDRESS = 22,
0185
0186     MXGEFW_ENABLE_FLOW_CONTROL = 23,
0187     MXGEFW_DISABLE_FLOW_CONTROL = 24,
0188
0189     /* do a DMA test
0190      * data0,data1 = DMA address
0191      * data2       = RDMA length (MSH), WDMA length (LSH)
0192      * command return data = repetitions (MSH), 0.5-ms ticks (LSH)
0193      */
0194     MXGEFW_DMA_TEST = 25,
0195
0196     MXGEFW_ENABLE_ALLMULTI = 26,
0197     MXGEFW_DISABLE_ALLMULTI = 27,
0198
0199     /* returns MXGEFW_CMD_ERROR_MULTICAST
0200      * if there is no room in the cache
0201      * data0,MSH(data1) = multicast group address */
0202     MXGEFW_JOIN_MULTICAST_GROUP = 28,
0203     /* returns MXGEFW_CMD_ERROR_MULTICAST
0204      * if the address is not in the cache,
0205      * or is equal to FF-FF-FF-FF-FF-FF
0206      * data0,MSH(data1) = multicast group address */
0207     MXGEFW_LEAVE_MULTICAST_GROUP = 29,
0208     MXGEFW_LEAVE_ALL_MULTICAST_GROUPS = 30,
0209
0210     MXGEFW_CMD_SET_STATS_DMA_V2 = 31,
0211     /* data0, data1 = bus addr,
0212      * data2 = sizeof(struct mcp_irq_data) from driver point of view, allows
0213      * adding new stuff to mcp_irq_data without changing the ABI
0214      *
0215      * If multiple slices are used, data2 contains both the size of the
0216      * structure (in the lower 16 bits) and the slice number
0217      * (in the upper 16 bits).
0218      */
0219
0220     MXGEFW_CMD_UNALIGNED_TEST = 32,
0221     /* same than DMA_TEST (same args) but abort with UNALIGNED on unaligned
0222      * chipset */
0223
0224     MXGEFW_CMD_UNALIGNED_STATUS = 33,
0225     /* return data = boolean, true if the chipset is known to be unaligned */
0226
0227     MXGEFW_CMD_ALWAYS_USE_N_BIG_BUFFERS = 34,
0228     /* data0 = number of big buffers to use.  It must be 0 or a power of 2.
0229      * 0 indicates that the NIC consumes as many buffers as they are required
0230      * for packet. This is the default behavior.
0231      * A power of 2 number indicates that the NIC always uses the specified
0232      * number of buffers for each big receive packet.
0233      * It is up to the driver to ensure that this value is big enough for
0234      * the NIC to be able to receive maximum-sized packets.
0235      */
0236
0237     MXGEFW_CMD_GET_MAX_RSS_QUEUES = 35,
0238     MXGEFW_CMD_ENABLE_RSS_QUEUES = 36,
0239     /* data0 = number of slices n (0, 1, ..., n-1) to enable
0240      * data1 = interrupt mode | use of multiple transmit queues.
0241      * 0=share one INTx/MSI.
0242      * 1=use one MSI-X per queue.
0243      * If all queues share one interrupt, the driver must have set
0244      * RSS_SHARED_INTERRUPT_DMA before enabling queues.
0245      * 2=enable both receive and send queues.
0246      * Without this bit set, only one send queue (slice 0's send queue)
0247      * is enabled.  The receive queues are always enabled.
0248      */
0249 #define MXGEFW_SLICE_INTR_MODE_SHARED          0x0
0250 #define MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE   0x1
0251 #define MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES 0x2
0252
0253     MXGEFW_CMD_GET_RSS_SHARED_INTERRUPT_MASK_OFFSET = 37,
0254     MXGEFW_CMD_SET_RSS_SHARED_INTERRUPT_DMA = 38,
0255     /* data0, data1 = bus address lsw, msw */
0256     MXGEFW_CMD_GET_RSS_TABLE_OFFSET = 39,
0257     /* get the offset of the indirection table */
0258     MXGEFW_CMD_SET_RSS_TABLE_SIZE = 40,
0259     /* set the size of the indirection table */
0260     MXGEFW_CMD_GET_RSS_KEY_OFFSET = 41,
0261     /* get the offset of the secret key */
0262     MXGEFW_CMD_RSS_KEY_UPDATED = 42,
0263     /* tell nic that the secret key's been updated */
0264     MXGEFW_CMD_SET_RSS_ENABLE = 43,
0265     /* data0 = enable/disable rss
0266      * 0: disable rss.  nic does not distribute receive packets.
0267      * 1: enable rss.  nic distributes receive packets among queues.
0268      * data1 = hash type
0269      * 1: IPV4            (required by RSS)
0270      * 2: TCP_IPV4        (required by RSS)
0271      * 3: IPV4 | TCP_IPV4 (required by RSS)
0272      * 4: source port
0273      * 5: source port + destination port
0274      */
0275 #define MXGEFW_RSS_HASH_TYPE_IPV4      0x1
0276 #define MXGEFW_RSS_HASH_TYPE_TCP_IPV4  0x2
0277 #define MXGEFW_RSS_HASH_TYPE_SRC_PORT  0x4
0278 #define MXGEFW_RSS_HASH_TYPE_SRC_DST_PORT 0x5
0279 #define MXGEFW_RSS_HASH_TYPE_MAX 0x5
0280
0281     MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE = 44,
0282     /* Return data = the max. size of the entire headers of a IPv6 TSO packet.
0283      * If the header size of a IPv6 TSO packet is larger than the specified
0284      * value, then the driver must not use TSO.
0285      * This size restriction only applies to IPv6 TSO.
0286      * For IPv4 TSO, the maximum size of the headers is fixed, and the NIC
0287      * always has enough header buffer to store maximum-sized headers.
0288      */
0289
0290     MXGEFW_CMD_SET_TSO_MODE = 45,
0291     /* data0 = TSO mode.
0292      * 0: Linux/FreeBSD style (NIC default)
0293      * 1: NDIS/NetBSD style
0294      */
0295 #define MXGEFW_TSO_MODE_LINUX  0
0296 #define MXGEFW_TSO_MODE_NDIS   1
0297
0298     MXGEFW_CMD_MDIO_READ = 46,
0299     /* data0 = dev_addr (PMA/PMD or PCS ...), data1 = register/addr */
0300     MXGEFW_CMD_MDIO_WRITE = 47,
0301     /* data0 = dev_addr,  data1 = register/addr, data2 = value  */
0302
0303     MXGEFW_CMD_I2C_READ = 48,
0304     /* Starts to get a fresh copy of one byte or of the module i2c table, the
0305      * obtained data is cached inside the xaui-xfi chip :
0306      *   data0 :  0 => get one byte, 1=> get 256 bytes
0307      *   data1 :  If data0 == 0: location to refresh
0308      *               bit 7:0  register location
0309      *               bit 8:15 is the i2c slave addr (0 is interpreted as 0xA1)
0310      *               bit 23:16 is the i2c bus number (for multi-port NICs)
0311      *            If data0 == 1: unused
0312      * The operation might take ~1ms for a single byte or ~65ms when refreshing all 256 bytes
0313      * During the i2c operation,  MXGEFW_CMD_I2C_READ or MXGEFW_CMD_I2C_BYTE attempts
0314      *  will return MXGEFW_CMD_ERROR_BUSY
0315      */
0316     MXGEFW_CMD_I2C_BYTE = 49,
0317     /* Return the last obtained copy of a given byte in the xfp i2c table
0318      * (copy cached during the last relevant MXGEFW_CMD_I2C_READ)
0319      *   data0 : index of the desired table entry
0320      *  Return data = the byte stored at the requested index in the table
0321      */
0322
0323     MXGEFW_CMD_GET_VPUMP_OFFSET = 50,
0324     /* Return data = NIC memory offset of mcp_vpump_public_global */
0325     MXGEFW_CMD_RESET_VPUMP = 51,
0326     /* Resets the VPUMP state */
0327
0328     MXGEFW_CMD_SET_RSS_MCP_SLOT_TYPE = 52,
0329     /* data0 = mcp_slot type to use.
0330      * 0 = the default 4B mcp_slot
0331      * 1 = 8B mcp_slot_8
0332      */
0333 #define MXGEFW_RSS_MCP_SLOT_TYPE_MIN        0
0334 #define MXGEFW_RSS_MCP_SLOT_TYPE_WITH_HASH  1
0335
0336     MXGEFW_CMD_SET_THROTTLE_FACTOR = 53,
0337     /* set the throttle factor for ethp_z8e
0338      * data0 = throttle_factor
0339      * throttle_factor = 256 * pcie-raw-speed / tx_speed
0340      * tx_speed = 256 * pcie-raw-speed / throttle_factor
0341      *
0342      * For PCI-E x8: pcie-raw-speed == 16Gb/s
0343      * For PCI-E x4: pcie-raw-speed == 8Gb/s
0344      *
0345      * ex1: throttle_factor == 0x1a0 (416), tx_speed == 1.23GB/s == 9.846 Gb/s
0346      * ex2: throttle_factor == 0x200 (512), tx_speed == 1.0GB/s == 8 Gb/s
0347      *
0348      * with tx_boundary == 2048, max-throttle-factor == 8191 => min-speed == 500Mb/s
0349      * with tx_boundary == 4096, max-throttle-factor == 4095 => min-speed == 1Gb/s
0350      */
0351
0352     MXGEFW_CMD_VPUMP_UP = 54,
0353     /* Allocates VPump Connection, Send Request and Zero copy buffer address tables */
0354     MXGEFW_CMD_GET_VPUMP_CLK = 55,
0355     /* Get the lanai clock */
0356
0357     MXGEFW_CMD_GET_DCA_OFFSET = 56,
0358     /* offset of dca control for WDMAs */
0359
0360     /* VMware NetQueue commands */
0361     MXGEFW_CMD_NETQ_GET_FILTERS_PER_QUEUE = 57,
0362     MXGEFW_CMD_NETQ_ADD_FILTER = 58,
0363     /* data0 = filter_id << 16 | queue << 8 | type */
0364     /* data1 = MS4 of MAC Addr */
0365     /* data2 = LS2_MAC << 16 | VLAN_tag */
0366     MXGEFW_CMD_NETQ_DEL_FILTER = 59,
0367     /* data0 = filter_id */
0368     MXGEFW_CMD_NETQ_QUERY1 = 60,
0369     MXGEFW_CMD_NETQ_QUERY2 = 61,
0370     MXGEFW_CMD_NETQ_QUERY3 = 62,
0371     MXGEFW_CMD_NETQ_QUERY4 = 63,
0372
0373     MXGEFW_CMD_RELAX_RXBUFFER_ALIGNMENT = 64,
0374     /* When set, small receive buffers can cross page boundaries.
0375      * Both small and big receive buffers may start at any address.
0376      * This option has performance implications, so use with caution.
0377      */
0378 };
0379
0380 enum myri10ge_mcp_cmd_status {
0381     MXGEFW_CMD_OK = 0,
0382     MXGEFW_CMD_UNKNOWN = 1,
0383     MXGEFW_CMD_ERROR_RANGE = 2,
0384     MXGEFW_CMD_ERROR_BUSY = 3,
0385     MXGEFW_CMD_ERROR_EMPTY = 4,
0386     MXGEFW_CMD_ERROR_CLOSED = 5,
0387     MXGEFW_CMD_ERROR_HASH_ERROR = 6,
0388     MXGEFW_CMD_ERROR_BAD_PORT = 7,
0389     MXGEFW_CMD_ERROR_RESOURCES = 8,
0390     MXGEFW_CMD_ERROR_MULTICAST = 9,
0391     MXGEFW_CMD_ERROR_UNALIGNED = 10,
0392     MXGEFW_CMD_ERROR_NO_MDIO = 11,
0393     MXGEFW_CMD_ERROR_I2C_FAILURE = 12,
0394     MXGEFW_CMD_ERROR_I2C_ABSENT = 13,
0395     MXGEFW_CMD_ERROR_BAD_PCIE_LINK = 14
0396 };
0397
0398 #define MXGEFW_OLD_IRQ_DATA_LEN 40
0399
0400 struct mcp_irq_data {
0401     /* add new counters at the beginning */
0402     __be32 future_use[1];
0403     __be32 dropped_pause;
0404     __be32 dropped_unicast_filtered;
0405     __be32 dropped_bad_crc32;
0406     __be32 dropped_bad_phy;
0407     __be32 dropped_multicast_filtered;
0408     /* 40 Bytes */
0409     __be32 send_done_count;
0410
0411 #define MXGEFW_LINK_DOWN 0
0412 #define MXGEFW_LINK_UP 1
0413 #define MXGEFW_LINK_MYRINET 2
0414 #define MXGEFW_LINK_UNKNOWN 3
0415     __be32 link_up;
0416     __be32 dropped_link_overflow;
0417     __be32 dropped_link_error_or_filtered;
0418     __be32 dropped_runt;
0419     __be32 dropped_overrun;
0420     __be32 dropped_no_small_buffer;
0421     __be32 dropped_no_big_buffer;
0422     __be32 rdma_tags_available;
0423
0424     u8 tx_stopped;
0425     u8 link_down;
0426     u8 stats_updated;
0427     u8 valid;
0428 };
0429
0430 /* definitions for NETQ filter type */
0431 #define MXGEFW_NETQ_FILTERTYPE_NONE 0
0432 #define MXGEFW_NETQ_FILTERTYPE_MACADDR 1
0433 #define MXGEFW_NETQ_FILTERTYPE_VLAN 2
0434 #define MXGEFW_NETQ_FILTERTYPE_VLANMACADDR 3
0435
0436 #endif              /* __MYRI10GE_MCP_H__ */