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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
0002 /*
0003  * Microsemi Ocelot Switch driver
0004  *
0005  * Copyright (c) 2017 Microsemi Corporation
0006  * Copyright (c) 2021 Innovative Advantage
0007  */
0008 #include <soc/mscc/ocelot_vcap.h>
0009 #include <soc/mscc/vsc7514_regs.h>
0010 #include "ocelot.h"
0011 
0012 const u32 vsc7514_ana_regmap[] = {
0013     REG(ANA_ADVLEARN,               0x009000),
0014     REG(ANA_VLANMASK,               0x009004),
0015     REG(ANA_PORT_B_DOMAIN,              0x009008),
0016     REG(ANA_ANAGEFIL,               0x00900c),
0017     REG(ANA_ANEVENTS,               0x009010),
0018     REG(ANA_STORMLIMIT_BURST,           0x009014),
0019     REG(ANA_STORMLIMIT_CFG,             0x009018),
0020     REG(ANA_ISOLATED_PORTS,             0x009028),
0021     REG(ANA_COMMUNITY_PORTS,            0x00902c),
0022     REG(ANA_AUTOAGE,                0x009030),
0023     REG(ANA_MACTOPTIONS,                0x009034),
0024     REG(ANA_LEARNDISC,              0x009038),
0025     REG(ANA_AGENCTRL,               0x00903c),
0026     REG(ANA_MIRRORPORTS,                0x009040),
0027     REG(ANA_EMIRRORPORTS,               0x009044),
0028     REG(ANA_FLOODING,               0x009048),
0029     REG(ANA_FLOODING_IPMC,              0x00904c),
0030     REG(ANA_SFLOW_CFG,              0x009050),
0031     REG(ANA_PORT_MODE,              0x009080),
0032     REG(ANA_PGID_PGID,              0x008c00),
0033     REG(ANA_TABLES_ANMOVED,             0x008b30),
0034     REG(ANA_TABLES_MACHDATA,            0x008b34),
0035     REG(ANA_TABLES_MACLDATA,            0x008b38),
0036     REG(ANA_TABLES_MACACCESS,           0x008b3c),
0037     REG(ANA_TABLES_MACTINDX,            0x008b40),
0038     REG(ANA_TABLES_VLANACCESS,          0x008b44),
0039     REG(ANA_TABLES_VLANTIDX,            0x008b48),
0040     REG(ANA_TABLES_ISDXACCESS,          0x008b4c),
0041     REG(ANA_TABLES_ISDXTIDX,            0x008b50),
0042     REG(ANA_TABLES_ENTRYLIM,            0x008b00),
0043     REG(ANA_TABLES_PTP_ID_HIGH,         0x008b54),
0044     REG(ANA_TABLES_PTP_ID_LOW,          0x008b58),
0045     REG(ANA_MSTI_STATE,             0x008e00),
0046     REG(ANA_PORT_VLAN_CFG,              0x007000),
0047     REG(ANA_PORT_DROP_CFG,              0x007004),
0048     REG(ANA_PORT_QOS_CFG,               0x007008),
0049     REG(ANA_PORT_VCAP_CFG,              0x00700c),
0050     REG(ANA_PORT_VCAP_S1_KEY_CFG,           0x007010),
0051     REG(ANA_PORT_VCAP_S2_CFG,           0x00701c),
0052     REG(ANA_PORT_PCP_DEI_MAP,           0x007020),
0053     REG(ANA_PORT_CPU_FWD_CFG,           0x007060),
0054     REG(ANA_PORT_CPU_FWD_BPDU_CFG,          0x007064),
0055     REG(ANA_PORT_CPU_FWD_GARP_CFG,          0x007068),
0056     REG(ANA_PORT_CPU_FWD_CCM_CFG,           0x00706c),
0057     REG(ANA_PORT_PORT_CFG,              0x007070),
0058     REG(ANA_PORT_POL_CFG,               0x007074),
0059     REG(ANA_PORT_PTP_CFG,               0x007078),
0060     REG(ANA_PORT_PTP_DLY1_CFG,          0x00707c),
0061     REG(ANA_OAM_UPM_LM_CNT,             0x007c00),
0062     REG(ANA_PORT_PTP_DLY2_CFG,          0x007080),
0063     REG(ANA_PFC_PFC_CFG,                0x008800),
0064     REG(ANA_PFC_PFC_TIMER,              0x008804),
0065     REG(ANA_IPT_OAM_MEP_CFG,            0x008000),
0066     REG(ANA_IPT_IPT,                0x008004),
0067     REG(ANA_PPT_PPT,                0x008ac0),
0068     REG(ANA_FID_MAP_FID_MAP,            0x000000),
0069     REG(ANA_AGGR_CFG,               0x0090b4),
0070     REG(ANA_CPUQ_CFG,               0x0090b8),
0071     REG(ANA_CPUQ_CFG2,              0x0090bc),
0072     REG(ANA_CPUQ_8021_CFG,              0x0090c0),
0073     REG(ANA_DSCP_CFG,               0x009100),
0074     REG(ANA_DSCP_REWR_CFG,              0x009200),
0075     REG(ANA_VCAP_RNG_TYPE_CFG,          0x009240),
0076     REG(ANA_VCAP_RNG_VAL_CFG,           0x009260),
0077     REG(ANA_VRAP_CFG,               0x009280),
0078     REG(ANA_VRAP_HDR_DATA,              0x009284),
0079     REG(ANA_VRAP_HDR_MASK,              0x009288),
0080     REG(ANA_DISCARD_CFG,                0x00928c),
0081     REG(ANA_FID_CFG,                0x009290),
0082     REG(ANA_POL_PIR_CFG,                0x004000),
0083     REG(ANA_POL_CIR_CFG,                0x004004),
0084     REG(ANA_POL_MODE_CFG,               0x004008),
0085     REG(ANA_POL_PIR_STATE,              0x00400c),
0086     REG(ANA_POL_CIR_STATE,              0x004010),
0087     REG(ANA_POL_STATE,              0x004014),
0088     REG(ANA_POL_FLOWC,              0x008b80),
0089     REG(ANA_POL_HYST,               0x008bec),
0090     REG(ANA_POL_MISC_CFG,               0x008bf0),
0091 };
0092 EXPORT_SYMBOL(vsc7514_ana_regmap);
0093 
0094 const u32 vsc7514_qs_regmap[] = {
0095     REG(QS_XTR_GRP_CFG,             0x000000),
0096     REG(QS_XTR_RD,                  0x000008),
0097     REG(QS_XTR_FRM_PRUNING,             0x000010),
0098     REG(QS_XTR_FLUSH,               0x000018),
0099     REG(QS_XTR_DATA_PRESENT,            0x00001c),
0100     REG(QS_XTR_CFG,                 0x000020),
0101     REG(QS_INJ_GRP_CFG,             0x000024),
0102     REG(QS_INJ_WR,                  0x00002c),
0103     REG(QS_INJ_CTRL,                0x000034),
0104     REG(QS_INJ_STATUS,              0x00003c),
0105     REG(QS_INJ_ERR,                 0x000040),
0106     REG(QS_INH_DBG,                 0x000048),
0107 };
0108 EXPORT_SYMBOL(vsc7514_qs_regmap);
0109 
0110 const u32 vsc7514_qsys_regmap[] = {
0111     REG(QSYS_PORT_MODE,             0x011200),
0112     REG(QSYS_SWITCH_PORT_MODE,          0x011234),
0113     REG(QSYS_STAT_CNT_CFG,              0x011264),
0114     REG(QSYS_EEE_CFG,               0x011268),
0115     REG(QSYS_EEE_THRES,             0x011294),
0116     REG(QSYS_IGR_NO_SHARING,            0x011298),
0117     REG(QSYS_EGR_NO_SHARING,            0x01129c),
0118     REG(QSYS_SW_STATUS,             0x0112a0),
0119     REG(QSYS_EXT_CPU_CFG,               0x0112d0),
0120     REG(QSYS_PAD_CFG,               0x0112d4),
0121     REG(QSYS_CPU_GROUP_MAP,             0x0112d8),
0122     REG(QSYS_QMAP,                  0x0112dc),
0123     REG(QSYS_ISDX_SGRP,             0x011400),
0124     REG(QSYS_TIMED_FRAME_ENTRY,         0x014000),
0125     REG(QSYS_TFRM_MISC,             0x011310),
0126     REG(QSYS_TFRM_PORT_DLY,             0x011314),
0127     REG(QSYS_TFRM_TIMER_CFG_1,          0x011318),
0128     REG(QSYS_TFRM_TIMER_CFG_2,          0x01131c),
0129     REG(QSYS_TFRM_TIMER_CFG_3,          0x011320),
0130     REG(QSYS_TFRM_TIMER_CFG_4,          0x011324),
0131     REG(QSYS_TFRM_TIMER_CFG_5,          0x011328),
0132     REG(QSYS_TFRM_TIMER_CFG_6,          0x01132c),
0133     REG(QSYS_TFRM_TIMER_CFG_7,          0x011330),
0134     REG(QSYS_TFRM_TIMER_CFG_8,          0x011334),
0135     REG(QSYS_RED_PROFILE,               0x011338),
0136     REG(QSYS_RES_QOS_MODE,              0x011378),
0137     REG(QSYS_RES_CFG,               0x012000),
0138     REG(QSYS_RES_STAT,              0x012004),
0139     REG(QSYS_EGR_DROP_MODE,             0x01137c),
0140     REG(QSYS_EQ_CTRL,               0x011380),
0141     REG(QSYS_EVENTS_CORE,               0x011384),
0142     REG(QSYS_CIR_CFG,               0x000000),
0143     REG(QSYS_EIR_CFG,               0x000004),
0144     REG(QSYS_SE_CFG,                0x000008),
0145     REG(QSYS_SE_DWRR_CFG,               0x00000c),
0146     REG(QSYS_SE_CONNECT,                0x00003c),
0147     REG(QSYS_SE_DLB_SENSE,              0x000040),
0148     REG(QSYS_CIR_STATE,             0x000044),
0149     REG(QSYS_EIR_STATE,             0x000048),
0150     REG(QSYS_SE_STATE,              0x00004c),
0151     REG(QSYS_HSCH_MISC_CFG,             0x011388),
0152 };
0153 EXPORT_SYMBOL(vsc7514_qsys_regmap);
0154 
0155 const u32 vsc7514_rew_regmap[] = {
0156     REG(REW_PORT_VLAN_CFG,              0x000000),
0157     REG(REW_TAG_CFG,                0x000004),
0158     REG(REW_PORT_CFG,               0x000008),
0159     REG(REW_DSCP_CFG,               0x00000c),
0160     REG(REW_PCP_DEI_QOS_MAP_CFG,            0x000010),
0161     REG(REW_PTP_CFG,                0x000050),
0162     REG(REW_PTP_DLY1_CFG,               0x000054),
0163     REG(REW_DSCP_REMAP_DP1_CFG,         0x000690),
0164     REG(REW_DSCP_REMAP_CFG,             0x000790),
0165     REG(REW_STAT_CFG,               0x000890),
0166     REG(REW_PPT,                    0x000680),
0167 };
0168 EXPORT_SYMBOL(vsc7514_rew_regmap);
0169 
0170 const u32 vsc7514_sys_regmap[] = {
0171     REG(SYS_COUNT_RX_OCTETS,            0x000000),
0172     REG(SYS_COUNT_RX_UNICAST,           0x000004),
0173     REG(SYS_COUNT_RX_MULTICAST,         0x000008),
0174     REG(SYS_COUNT_RX_BROADCAST,         0x00000c),
0175     REG(SYS_COUNT_RX_SHORTS,            0x000010),
0176     REG(SYS_COUNT_RX_FRAGMENTS,         0x000014),
0177     REG(SYS_COUNT_RX_JABBERS,           0x000018),
0178     REG(SYS_COUNT_RX_CRC_ALIGN_ERRS,        0x00001c),
0179     REG(SYS_COUNT_RX_SYM_ERRS,          0x000020),
0180     REG(SYS_COUNT_RX_64,                0x000024),
0181     REG(SYS_COUNT_RX_65_127,            0x000028),
0182     REG(SYS_COUNT_RX_128_255,           0x00002c),
0183     REG(SYS_COUNT_RX_256_511,           0x000030),
0184     REG(SYS_COUNT_RX_512_1023,          0x000034),
0185     REG(SYS_COUNT_RX_1024_1526,         0x000038),
0186     REG(SYS_COUNT_RX_1527_MAX,          0x00003c),
0187     REG(SYS_COUNT_RX_PAUSE,             0x000040),
0188     REG(SYS_COUNT_RX_CONTROL,           0x000044),
0189     REG(SYS_COUNT_RX_LONGS,             0x000048),
0190     REG(SYS_COUNT_RX_CLASSIFIED_DROPS,      0x00004c),
0191     REG(SYS_COUNT_RX_RED_PRIO_0,            0x000050),
0192     REG(SYS_COUNT_RX_RED_PRIO_1,            0x000054),
0193     REG(SYS_COUNT_RX_RED_PRIO_2,            0x000058),
0194     REG(SYS_COUNT_RX_RED_PRIO_3,            0x00005c),
0195     REG(SYS_COUNT_RX_RED_PRIO_4,            0x000060),
0196     REG(SYS_COUNT_RX_RED_PRIO_5,            0x000064),
0197     REG(SYS_COUNT_RX_RED_PRIO_6,            0x000068),
0198     REG(SYS_COUNT_RX_RED_PRIO_7,            0x00006c),
0199     REG(SYS_COUNT_RX_YELLOW_PRIO_0,         0x000070),
0200     REG(SYS_COUNT_RX_YELLOW_PRIO_1,         0x000074),
0201     REG(SYS_COUNT_RX_YELLOW_PRIO_2,         0x000078),
0202     REG(SYS_COUNT_RX_YELLOW_PRIO_3,         0x00007c),
0203     REG(SYS_COUNT_RX_YELLOW_PRIO_4,         0x000080),
0204     REG(SYS_COUNT_RX_YELLOW_PRIO_5,         0x000084),
0205     REG(SYS_COUNT_RX_YELLOW_PRIO_6,         0x000088),
0206     REG(SYS_COUNT_RX_YELLOW_PRIO_7,         0x00008c),
0207     REG(SYS_COUNT_RX_GREEN_PRIO_0,          0x000090),
0208     REG(SYS_COUNT_RX_GREEN_PRIO_1,          0x000094),
0209     REG(SYS_COUNT_RX_GREEN_PRIO_2,          0x000098),
0210     REG(SYS_COUNT_RX_GREEN_PRIO_3,          0x00009c),
0211     REG(SYS_COUNT_RX_GREEN_PRIO_4,          0x0000a0),
0212     REG(SYS_COUNT_RX_GREEN_PRIO_5,          0x0000a4),
0213     REG(SYS_COUNT_RX_GREEN_PRIO_6,          0x0000a8),
0214     REG(SYS_COUNT_RX_GREEN_PRIO_7,          0x0000ac),
0215     REG(SYS_COUNT_TX_OCTETS,            0x000100),
0216     REG(SYS_COUNT_TX_UNICAST,           0x000104),
0217     REG(SYS_COUNT_TX_MULTICAST,         0x000108),
0218     REG(SYS_COUNT_TX_BROADCAST,         0x00010c),
0219     REG(SYS_COUNT_TX_COLLISION,         0x000110),
0220     REG(SYS_COUNT_TX_DROPS,             0x000114),
0221     REG(SYS_COUNT_TX_PAUSE,             0x000118),
0222     REG(SYS_COUNT_TX_64,                0x00011c),
0223     REG(SYS_COUNT_TX_65_127,            0x000120),
0224     REG(SYS_COUNT_TX_128_255,           0x000124),
0225     REG(SYS_COUNT_TX_256_511,           0x000128),
0226     REG(SYS_COUNT_TX_512_1023,          0x00012c),
0227     REG(SYS_COUNT_TX_1024_1526,         0x000130),
0228     REG(SYS_COUNT_TX_1527_MAX,          0x000134),
0229     REG(SYS_COUNT_TX_YELLOW_PRIO_0,         0x000138),
0230     REG(SYS_COUNT_TX_YELLOW_PRIO_1,         0x00013c),
0231     REG(SYS_COUNT_TX_YELLOW_PRIO_2,         0x000140),
0232     REG(SYS_COUNT_TX_YELLOW_PRIO_3,         0x000144),
0233     REG(SYS_COUNT_TX_YELLOW_PRIO_4,         0x000148),
0234     REG(SYS_COUNT_TX_YELLOW_PRIO_5,         0x00014c),
0235     REG(SYS_COUNT_TX_YELLOW_PRIO_6,         0x000150),
0236     REG(SYS_COUNT_TX_YELLOW_PRIO_7,         0x000154),
0237     REG(SYS_COUNT_TX_GREEN_PRIO_0,          0x000158),
0238     REG(SYS_COUNT_TX_GREEN_PRIO_1,          0x00015c),
0239     REG(SYS_COUNT_TX_GREEN_PRIO_2,          0x000160),
0240     REG(SYS_COUNT_TX_GREEN_PRIO_3,          0x000164),
0241     REG(SYS_COUNT_TX_GREEN_PRIO_4,          0x000168),
0242     REG(SYS_COUNT_TX_GREEN_PRIO_5,          0x00016c),
0243     REG(SYS_COUNT_TX_GREEN_PRIO_6,          0x000170),
0244     REG(SYS_COUNT_TX_GREEN_PRIO_7,          0x000174),
0245     REG(SYS_COUNT_TX_AGING,             0x000178),
0246     REG(SYS_COUNT_DROP_LOCAL,           0x000200),
0247     REG(SYS_COUNT_DROP_TAIL,            0x000204),
0248     REG(SYS_COUNT_DROP_YELLOW_PRIO_0,       0x000208),
0249     REG(SYS_COUNT_DROP_YELLOW_PRIO_1,       0x00020c),
0250     REG(SYS_COUNT_DROP_YELLOW_PRIO_2,       0x000210),
0251     REG(SYS_COUNT_DROP_YELLOW_PRIO_3,       0x000214),
0252     REG(SYS_COUNT_DROP_YELLOW_PRIO_4,       0x000218),
0253     REG(SYS_COUNT_DROP_YELLOW_PRIO_5,       0x00021c),
0254     REG(SYS_COUNT_DROP_YELLOW_PRIO_6,       0x000220),
0255     REG(SYS_COUNT_DROP_YELLOW_PRIO_7,       0x000214),
0256     REG(SYS_COUNT_DROP_GREEN_PRIO_0,        0x000218),
0257     REG(SYS_COUNT_DROP_GREEN_PRIO_1,        0x00021c),
0258     REG(SYS_COUNT_DROP_GREEN_PRIO_2,        0x000220),
0259     REG(SYS_COUNT_DROP_GREEN_PRIO_3,        0x000224),
0260     REG(SYS_COUNT_DROP_GREEN_PRIO_4,        0x000228),
0261     REG(SYS_COUNT_DROP_GREEN_PRIO_5,        0x00022c),
0262     REG(SYS_COUNT_DROP_GREEN_PRIO_6,        0x000230),
0263     REG(SYS_COUNT_DROP_GREEN_PRIO_7,        0x000234),
0264     REG(SYS_RESET_CFG,              0x000508),
0265     REG(SYS_CMID,                   0x00050c),
0266     REG(SYS_VLAN_ETYPE_CFG,             0x000510),
0267     REG(SYS_PORT_MODE,              0x000514),
0268     REG(SYS_FRONT_PORT_MODE,            0x000548),
0269     REG(SYS_FRM_AGING,              0x000574),
0270     REG(SYS_STAT_CFG,               0x000578),
0271     REG(SYS_SW_STATUS,              0x00057c),
0272     REG(SYS_MISC_CFG,               0x0005ac),
0273     REG(SYS_REW_MAC_HIGH_CFG,           0x0005b0),
0274     REG(SYS_REW_MAC_LOW_CFG,            0x0005dc),
0275     REG(SYS_CM_ADDR,                0x000500),
0276     REG(SYS_CM_DATA,                0x000504),
0277     REG(SYS_PAUSE_CFG,              0x000608),
0278     REG(SYS_PAUSE_TOT_CFG,              0x000638),
0279     REG(SYS_ATOP,                   0x00063c),
0280     REG(SYS_ATOP_TOT_CFG,               0x00066c),
0281     REG(SYS_MAC_FC_CFG,             0x000670),
0282     REG(SYS_MMGT,                   0x00069c),
0283     REG(SYS_MMGT_FAST,              0x0006a0),
0284     REG(SYS_EVENTS_DIF,             0x0006a4),
0285     REG(SYS_EVENTS_CORE,                0x0006b4),
0286     REG(SYS_CNT,                    0x000000),
0287     REG(SYS_PTP_STATUS,             0x0006b8),
0288     REG(SYS_PTP_TXSTAMP,                0x0006bc),
0289     REG(SYS_PTP_NXT,                0x0006c0),
0290     REG(SYS_PTP_CFG,                0x0006c4),
0291 };
0292 EXPORT_SYMBOL(vsc7514_sys_regmap);
0293 
0294 const u32 vsc7514_vcap_regmap[] = {
0295     /* VCAP_CORE_CFG */
0296     REG(VCAP_CORE_UPDATE_CTRL,          0x000000),
0297     REG(VCAP_CORE_MV_CFG,               0x000004),
0298     /* VCAP_CORE_CACHE */
0299     REG(VCAP_CACHE_ENTRY_DAT,           0x000008),
0300     REG(VCAP_CACHE_MASK_DAT,            0x000108),
0301     REG(VCAP_CACHE_ACTION_DAT,          0x000208),
0302     REG(VCAP_CACHE_CNT_DAT,             0x000308),
0303     REG(VCAP_CACHE_TG_DAT,              0x000388),
0304     /* VCAP_CONST */
0305     REG(VCAP_CONST_VCAP_VER,            0x000398),
0306     REG(VCAP_CONST_ENTRY_WIDTH,         0x00039c),
0307     REG(VCAP_CONST_ENTRY_CNT,           0x0003a0),
0308     REG(VCAP_CONST_ENTRY_SWCNT,         0x0003a4),
0309     REG(VCAP_CONST_ENTRY_TG_WIDTH,          0x0003a8),
0310     REG(VCAP_CONST_ACTION_DEF_CNT,          0x0003ac),
0311     REG(VCAP_CONST_ACTION_WIDTH,            0x0003b0),
0312     REG(VCAP_CONST_CNT_WIDTH,           0x0003b4),
0313     REG(VCAP_CONST_CORE_CNT,            0x0003b8),
0314     REG(VCAP_CONST_IF_CNT,              0x0003bc),
0315 };
0316 EXPORT_SYMBOL(vsc7514_vcap_regmap);
0317 
0318 const u32 vsc7514_ptp_regmap[] = {
0319     REG(PTP_PIN_CFG,                0x000000),
0320     REG(PTP_PIN_TOD_SEC_MSB,            0x000004),
0321     REG(PTP_PIN_TOD_SEC_LSB,            0x000008),
0322     REG(PTP_PIN_TOD_NSEC,               0x00000c),
0323     REG(PTP_PIN_WF_HIGH_PERIOD,         0x000014),
0324     REG(PTP_PIN_WF_LOW_PERIOD,          0x000018),
0325     REG(PTP_CFG_MISC,               0x0000a0),
0326     REG(PTP_CLK_CFG_ADJ_CFG,            0x0000a4),
0327     REG(PTP_CLK_CFG_ADJ_FREQ,           0x0000a8),
0328 };
0329 EXPORT_SYMBOL(vsc7514_ptp_regmap);
0330 
0331 const u32 vsc7514_dev_gmii_regmap[] = {
0332     REG(DEV_CLOCK_CFG,              0x0),
0333     REG(DEV_PORT_MISC,              0x4),
0334     REG(DEV_EVENTS,                 0x8),
0335     REG(DEV_EEE_CFG,                0xc),
0336     REG(DEV_RX_PATH_DELAY,              0x10),
0337     REG(DEV_TX_PATH_DELAY,              0x14),
0338     REG(DEV_PTP_PREDICT_CFG,            0x18),
0339     REG(DEV_MAC_ENA_CFG,                0x1c),
0340     REG(DEV_MAC_MODE_CFG,               0x20),
0341     REG(DEV_MAC_MAXLEN_CFG,             0x24),
0342     REG(DEV_MAC_TAGS_CFG,               0x28),
0343     REG(DEV_MAC_ADV_CHK_CFG,            0x2c),
0344     REG(DEV_MAC_IFG_CFG,                0x30),
0345     REG(DEV_MAC_HDX_CFG,                0x34),
0346     REG(DEV_MAC_DBG_CFG,                0x38),
0347     REG(DEV_MAC_FC_MAC_LOW_CFG,         0x3c),
0348     REG(DEV_MAC_FC_MAC_HIGH_CFG,            0x40),
0349     REG(DEV_MAC_STICKY,             0x44),
0350     REG(PCS1G_CFG,                  0x48),
0351     REG(PCS1G_MODE_CFG,             0x4c),
0352     REG(PCS1G_SD_CFG,               0x50),
0353     REG(PCS1G_ANEG_CFG,             0x54),
0354     REG(PCS1G_ANEG_NP_CFG,              0x58),
0355     REG(PCS1G_LB_CFG,               0x5c),
0356     REG(PCS1G_DBG_CFG,              0x60),
0357     REG(PCS1G_CDET_CFG,             0x64),
0358     REG(PCS1G_ANEG_STATUS,              0x68),
0359     REG(PCS1G_ANEG_NP_STATUS,           0x6c),
0360     REG(PCS1G_LINK_STATUS,              0x70),
0361     REG(PCS1G_LINK_DOWN_CNT,            0x74),
0362     REG(PCS1G_STICKY,               0x78),
0363     REG(PCS1G_DEBUG_STATUS,             0x7c),
0364     REG(PCS1G_LPI_CFG,              0x80),
0365     REG(PCS1G_LPI_WAKE_ERROR_CNT,           0x84),
0366     REG(PCS1G_LPI_STATUS,               0x88),
0367     REG(PCS1G_TSTPAT_MODE_CFG,          0x8c),
0368     REG(PCS1G_TSTPAT_STATUS,            0x90),
0369     REG(DEV_PCS_FX100_CFG,              0x94),
0370     REG(DEV_PCS_FX100_STATUS,           0x98),
0371 };
0372 EXPORT_SYMBOL(vsc7514_dev_gmii_regmap);
0373 
0374 const struct vcap_field vsc7514_vcap_es0_keys[] = {
0375     [VCAP_ES0_EGR_PORT]         = { 0,   4 },
0376     [VCAP_ES0_IGR_PORT]         = { 4,   4 },
0377     [VCAP_ES0_RSV]              = { 8,   2 },
0378     [VCAP_ES0_L2_MC]            = { 10,  1 },
0379     [VCAP_ES0_L2_BC]            = { 11,  1 },
0380     [VCAP_ES0_VID]              = { 12, 12 },
0381     [VCAP_ES0_DP]               = { 24,  1 },
0382     [VCAP_ES0_PCP]              = { 25,  3 },
0383 };
0384 EXPORT_SYMBOL(vsc7514_vcap_es0_keys);
0385 
0386 const struct vcap_field vsc7514_vcap_es0_actions[]   = {
0387     [VCAP_ES0_ACT_PUSH_OUTER_TAG]       = { 0,   2 },
0388     [VCAP_ES0_ACT_PUSH_INNER_TAG]       = { 2,   1 },
0389     [VCAP_ES0_ACT_TAG_A_TPID_SEL]       = { 3,   2 },
0390     [VCAP_ES0_ACT_TAG_A_VID_SEL]        = { 5,   1 },
0391     [VCAP_ES0_ACT_TAG_A_PCP_SEL]        = { 6,   2 },
0392     [VCAP_ES0_ACT_TAG_A_DEI_SEL]        = { 8,   2 },
0393     [VCAP_ES0_ACT_TAG_B_TPID_SEL]       = { 10,  2 },
0394     [VCAP_ES0_ACT_TAG_B_VID_SEL]        = { 12,  1 },
0395     [VCAP_ES0_ACT_TAG_B_PCP_SEL]        = { 13,  2 },
0396     [VCAP_ES0_ACT_TAG_B_DEI_SEL]        = { 15,  2 },
0397     [VCAP_ES0_ACT_VID_A_VAL]        = { 17, 12 },
0398     [VCAP_ES0_ACT_PCP_A_VAL]        = { 29,  3 },
0399     [VCAP_ES0_ACT_DEI_A_VAL]        = { 32,  1 },
0400     [VCAP_ES0_ACT_VID_B_VAL]        = { 33, 12 },
0401     [VCAP_ES0_ACT_PCP_B_VAL]        = { 45,  3 },
0402     [VCAP_ES0_ACT_DEI_B_VAL]        = { 48,  1 },
0403     [VCAP_ES0_ACT_RSV]          = { 49, 24 },
0404     [VCAP_ES0_ACT_HIT_STICKY]       = { 73,  1 },
0405 };
0406 EXPORT_SYMBOL(vsc7514_vcap_es0_actions);
0407 
0408 const struct vcap_field vsc7514_vcap_is1_keys[] = {
0409     [VCAP_IS1_HK_TYPE]          = { 0,    1 },
0410     [VCAP_IS1_HK_LOOKUP]            = { 1,    2 },
0411     [VCAP_IS1_HK_IGR_PORT_MASK]     = { 3,   12 },
0412     [VCAP_IS1_HK_RSV]           = { 15,   9 },
0413     [VCAP_IS1_HK_OAM_Y1731]         = { 24,   1 },
0414     [VCAP_IS1_HK_L2_MC]         = { 25,   1 },
0415     [VCAP_IS1_HK_L2_BC]         = { 26,   1 },
0416     [VCAP_IS1_HK_IP_MC]         = { 27,   1 },
0417     [VCAP_IS1_HK_VLAN_TAGGED]       = { 28,   1 },
0418     [VCAP_IS1_HK_VLAN_DBL_TAGGED]       = { 29,   1 },
0419     [VCAP_IS1_HK_TPID]          = { 30,   1 },
0420     [VCAP_IS1_HK_VID]           = { 31,  12 },
0421     [VCAP_IS1_HK_DEI]           = { 43,   1 },
0422     [VCAP_IS1_HK_PCP]           = { 44,   3 },
0423     /* Specific Fields for IS1 Half Key S1_NORMAL */
0424     [VCAP_IS1_HK_L2_SMAC]           = { 47,  48 },
0425     [VCAP_IS1_HK_ETYPE_LEN]         = { 95,   1 },
0426     [VCAP_IS1_HK_ETYPE]         = { 96,  16 },
0427     [VCAP_IS1_HK_IP_SNAP]           = { 112,  1 },
0428     [VCAP_IS1_HK_IP4]           = { 113,  1 },
0429     /* Layer-3 Information */
0430     [VCAP_IS1_HK_L3_FRAGMENT]       = { 114,  1 },
0431     [VCAP_IS1_HK_L3_FRAG_OFS_GT0]       = { 115,  1 },
0432     [VCAP_IS1_HK_L3_OPTIONS]        = { 116,  1 },
0433     [VCAP_IS1_HK_L3_DSCP]           = { 117,  6 },
0434     [VCAP_IS1_HK_L3_IP4_SIP]        = { 123, 32 },
0435     /* Layer-4 Information */
0436     [VCAP_IS1_HK_TCP_UDP]           = { 155,  1 },
0437     [VCAP_IS1_HK_TCP]           = { 156,  1 },
0438     [VCAP_IS1_HK_L4_SPORT]          = { 157, 16 },
0439     [VCAP_IS1_HK_L4_RNG]            = { 173,  8 },
0440     /* Specific Fields for IS1 Half Key S1_5TUPLE_IP4 */
0441     [VCAP_IS1_HK_IP4_INNER_TPID]        = { 47,   1 },
0442     [VCAP_IS1_HK_IP4_INNER_VID]     = { 48,  12 },
0443     [VCAP_IS1_HK_IP4_INNER_DEI]     = { 60,   1 },
0444     [VCAP_IS1_HK_IP4_INNER_PCP]     = { 61,   3 },
0445     [VCAP_IS1_HK_IP4_IP4]           = { 64,   1 },
0446     [VCAP_IS1_HK_IP4_L3_FRAGMENT]       = { 65,   1 },
0447     [VCAP_IS1_HK_IP4_L3_FRAG_OFS_GT0]   = { 66,   1 },
0448     [VCAP_IS1_HK_IP4_L3_OPTIONS]        = { 67,   1 },
0449     [VCAP_IS1_HK_IP4_L3_DSCP]       = { 68,   6 },
0450     [VCAP_IS1_HK_IP4_L3_IP4_DIP]        = { 74,  32 },
0451     [VCAP_IS1_HK_IP4_L3_IP4_SIP]        = { 106, 32 },
0452     [VCAP_IS1_HK_IP4_L3_PROTO]      = { 138,  8 },
0453     [VCAP_IS1_HK_IP4_TCP_UDP]       = { 146,  1 },
0454     [VCAP_IS1_HK_IP4_TCP]           = { 147,  1 },
0455     [VCAP_IS1_HK_IP4_L4_RNG]        = { 148,  8 },
0456     [VCAP_IS1_HK_IP4_IP_PAYLOAD_S1_5TUPLE]  = { 156, 32 },
0457 };
0458 EXPORT_SYMBOL(vsc7514_vcap_is1_keys);
0459 
0460 const struct vcap_field vsc7514_vcap_is1_actions[] = {
0461     [VCAP_IS1_ACT_DSCP_ENA]         = { 0,   1 },
0462     [VCAP_IS1_ACT_DSCP_VAL]         = { 1,   6 },
0463     [VCAP_IS1_ACT_QOS_ENA]          = { 7,   1 },
0464     [VCAP_IS1_ACT_QOS_VAL]          = { 8,   3 },
0465     [VCAP_IS1_ACT_DP_ENA]           = { 11,  1 },
0466     [VCAP_IS1_ACT_DP_VAL]           = { 12,  1 },
0467     [VCAP_IS1_ACT_PAG_OVERRIDE_MASK]    = { 13,  8 },
0468     [VCAP_IS1_ACT_PAG_VAL]          = { 21,  8 },
0469     [VCAP_IS1_ACT_RSV]          = { 29,  9 },
0470     /* The fields below are incorrectly shifted by 2 in the manual */
0471     [VCAP_IS1_ACT_VID_REPLACE_ENA]      = { 38,  1 },
0472     [VCAP_IS1_ACT_VID_ADD_VAL]      = { 39, 12 },
0473     [VCAP_IS1_ACT_FID_SEL]          = { 51,  2 },
0474     [VCAP_IS1_ACT_FID_VAL]          = { 53, 13 },
0475     [VCAP_IS1_ACT_PCP_DEI_ENA]      = { 66,  1 },
0476     [VCAP_IS1_ACT_PCP_VAL]          = { 67,  3 },
0477     [VCAP_IS1_ACT_DEI_VAL]          = { 70,  1 },
0478     [VCAP_IS1_ACT_VLAN_POP_CNT_ENA]     = { 71,  1 },
0479     [VCAP_IS1_ACT_VLAN_POP_CNT]     = { 72,  2 },
0480     [VCAP_IS1_ACT_CUSTOM_ACE_TYPE_ENA]  = { 74,  4 },
0481     [VCAP_IS1_ACT_HIT_STICKY]       = { 78,  1 },
0482 };
0483 EXPORT_SYMBOL(vsc7514_vcap_is1_actions);
0484 
0485 const struct vcap_field vsc7514_vcap_is2_keys[] = {
0486     /* Common: 46 bits */
0487     [VCAP_IS2_TYPE]             = { 0,    4 },
0488     [VCAP_IS2_HK_FIRST]         = { 4,    1 },
0489     [VCAP_IS2_HK_PAG]           = { 5,    8 },
0490     [VCAP_IS2_HK_IGR_PORT_MASK]     = { 13,  12 },
0491     [VCAP_IS2_HK_RSV2]          = { 25,   1 },
0492     [VCAP_IS2_HK_HOST_MATCH]        = { 26,   1 },
0493     [VCAP_IS2_HK_L2_MC]         = { 27,   1 },
0494     [VCAP_IS2_HK_L2_BC]         = { 28,   1 },
0495     [VCAP_IS2_HK_VLAN_TAGGED]       = { 29,   1 },
0496     [VCAP_IS2_HK_VID]           = { 30,  12 },
0497     [VCAP_IS2_HK_DEI]           = { 42,   1 },
0498     [VCAP_IS2_HK_PCP]           = { 43,   3 },
0499     /* MAC_ETYPE / MAC_LLC / MAC_SNAP / OAM common */
0500     [VCAP_IS2_HK_L2_DMAC]           = { 46,  48 },
0501     [VCAP_IS2_HK_L2_SMAC]           = { 94,  48 },
0502     /* MAC_ETYPE (TYPE=000) */
0503     [VCAP_IS2_HK_MAC_ETYPE_ETYPE]       = { 142, 16 },
0504     [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0] = { 158, 16 },
0505     [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD1] = { 174,  8 },
0506     [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD2] = { 182,  3 },
0507     /* MAC_LLC (TYPE=001) */
0508     [VCAP_IS2_HK_MAC_LLC_L2_LLC]        = { 142, 40 },
0509     /* MAC_SNAP (TYPE=010) */
0510     [VCAP_IS2_HK_MAC_SNAP_L2_SNAP]      = { 142, 40 },
0511     /* MAC_ARP (TYPE=011) */
0512     [VCAP_IS2_HK_MAC_ARP_SMAC]      = { 46,  48 },
0513     [VCAP_IS2_HK_MAC_ARP_ADDR_SPACE_OK] = { 94,   1 },
0514     [VCAP_IS2_HK_MAC_ARP_PROTO_SPACE_OK]    = { 95,   1 },
0515     [VCAP_IS2_HK_MAC_ARP_LEN_OK]        = { 96,   1 },
0516     [VCAP_IS2_HK_MAC_ARP_TARGET_MATCH]  = { 97,   1 },
0517     [VCAP_IS2_HK_MAC_ARP_SENDER_MATCH]  = { 98,   1 },
0518     [VCAP_IS2_HK_MAC_ARP_OPCODE_UNKNOWN]    = { 99,   1 },
0519     [VCAP_IS2_HK_MAC_ARP_OPCODE]        = { 100,  2 },
0520     [VCAP_IS2_HK_MAC_ARP_L3_IP4_DIP]    = { 102, 32 },
0521     [VCAP_IS2_HK_MAC_ARP_L3_IP4_SIP]    = { 134, 32 },
0522     [VCAP_IS2_HK_MAC_ARP_DIP_EQ_SIP]    = { 166,  1 },
0523     /* IP4_TCP_UDP / IP4_OTHER common */
0524     [VCAP_IS2_HK_IP4]           = { 46,   1 },
0525     [VCAP_IS2_HK_L3_FRAGMENT]       = { 47,   1 },
0526     [VCAP_IS2_HK_L3_FRAG_OFS_GT0]       = { 48,   1 },
0527     [VCAP_IS2_HK_L3_OPTIONS]        = { 49,   1 },
0528     [VCAP_IS2_HK_IP4_L3_TTL_GT0]        = { 50,   1 },
0529     [VCAP_IS2_HK_L3_TOS]            = { 51,   8 },
0530     [VCAP_IS2_HK_L3_IP4_DIP]        = { 59,  32 },
0531     [VCAP_IS2_HK_L3_IP4_SIP]        = { 91,  32 },
0532     [VCAP_IS2_HK_DIP_EQ_SIP]        = { 123,  1 },
0533     /* IP4_TCP_UDP (TYPE=100) */
0534     [VCAP_IS2_HK_TCP]           = { 124,  1 },
0535     [VCAP_IS2_HK_L4_DPORT]          = { 125, 16 },
0536     [VCAP_IS2_HK_L4_SPORT]          = { 141, 16 },
0537     [VCAP_IS2_HK_L4_RNG]            = { 157,  8 },
0538     [VCAP_IS2_HK_L4_SPORT_EQ_DPORT]     = { 165,  1 },
0539     [VCAP_IS2_HK_L4_SEQUENCE_EQ0]       = { 166,  1 },
0540     [VCAP_IS2_HK_L4_FIN]            = { 167,  1 },
0541     [VCAP_IS2_HK_L4_SYN]            = { 168,  1 },
0542     [VCAP_IS2_HK_L4_RST]            = { 169,  1 },
0543     [VCAP_IS2_HK_L4_PSH]            = { 170,  1 },
0544     [VCAP_IS2_HK_L4_ACK]            = { 171,  1 },
0545     [VCAP_IS2_HK_L4_URG]            = { 172,  1 },
0546     [VCAP_IS2_HK_L4_1588_DOM]       = { 173,  8 },
0547     [VCAP_IS2_HK_L4_1588_VER]       = { 181,  4 },
0548     /* IP4_OTHER (TYPE=101) */
0549     [VCAP_IS2_HK_IP4_L3_PROTO]      = { 124,  8 },
0550     [VCAP_IS2_HK_L3_PAYLOAD]        = { 132, 56 },
0551     /* IP6_STD (TYPE=110) */
0552     [VCAP_IS2_HK_IP6_L3_TTL_GT0]        = { 46,   1 },
0553     [VCAP_IS2_HK_L3_IP6_SIP]        = { 47, 128 },
0554     [VCAP_IS2_HK_IP6_L3_PROTO]      = { 175,  8 },
0555     /* OAM (TYPE=111) */
0556     [VCAP_IS2_HK_OAM_MEL_FLAGS]     = { 142,  7 },
0557     [VCAP_IS2_HK_OAM_VER]           = { 149,  5 },
0558     [VCAP_IS2_HK_OAM_OPCODE]        = { 154,  8 },
0559     [VCAP_IS2_HK_OAM_FLAGS]         = { 162,  8 },
0560     [VCAP_IS2_HK_OAM_MEPID]         = { 170, 16 },
0561     [VCAP_IS2_HK_OAM_CCM_CNTS_EQ0]      = { 186,  1 },
0562     [VCAP_IS2_HK_OAM_IS_Y1731]      = { 187,  1 },
0563 };
0564 EXPORT_SYMBOL(vsc7514_vcap_is2_keys);
0565 
0566 const struct vcap_field vsc7514_vcap_is2_actions[] = {
0567     [VCAP_IS2_ACT_HIT_ME_ONCE]      = { 0,   1 },
0568     [VCAP_IS2_ACT_CPU_COPY_ENA]     = { 1,   1 },
0569     [VCAP_IS2_ACT_CPU_QU_NUM]       = { 2,   3 },
0570     [VCAP_IS2_ACT_MASK_MODE]        = { 5,   2 },
0571     [VCAP_IS2_ACT_MIRROR_ENA]       = { 7,   1 },
0572     [VCAP_IS2_ACT_LRN_DIS]          = { 8,   1 },
0573     [VCAP_IS2_ACT_POLICE_ENA]       = { 9,   1 },
0574     [VCAP_IS2_ACT_POLICE_IDX]       = { 10,  9 },
0575     [VCAP_IS2_ACT_POLICE_VCAP_ONLY]     = { 19,  1 },
0576     [VCAP_IS2_ACT_PORT_MASK]        = { 20, 11 },
0577     [VCAP_IS2_ACT_REW_OP]           = { 31,  9 },
0578     [VCAP_IS2_ACT_SMAC_REPLACE_ENA]     = { 40,  1 },
0579     [VCAP_IS2_ACT_RSV]          = { 41,  2 },
0580     [VCAP_IS2_ACT_ACL_ID]           = { 43,  6 },
0581     [VCAP_IS2_ACT_HIT_CNT]          = { 49, 32 },
0582 };
0583 EXPORT_SYMBOL(vsc7514_vcap_is2_actions);
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