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0007 #include <linux/dsa/ocelot.h>
0008 #include <linux/interrupt.h>
0009 #include <linux/module.h>
0010 #include <linux/of_net.h>
0011 #include <linux/netdevice.h>
0012 #include <linux/phylink.h>
0013 #include <linux/of_mdio.h>
0014 #include <linux/of_platform.h>
0015 #include <linux/mfd/syscon.h>
0016 #include <linux/skbuff.h>
0017 #include <net/switchdev.h>
0018
0019 #include <soc/mscc/ocelot_vcap.h>
0020 #include <soc/mscc/ocelot_hsio.h>
0021 #include <soc/mscc/vsc7514_regs.h>
0022 #include "ocelot_fdma.h"
0023 #include "ocelot.h"
0024
0025 #define VSC7514_VCAP_POLICER_BASE 128
0026 #define VSC7514_VCAP_POLICER_MAX 191
0027
0028 static const u32 *ocelot_regmap[TARGET_MAX] = {
0029 [ANA] = vsc7514_ana_regmap,
0030 [QS] = vsc7514_qs_regmap,
0031 [QSYS] = vsc7514_qsys_regmap,
0032 [REW] = vsc7514_rew_regmap,
0033 [SYS] = vsc7514_sys_regmap,
0034 [S0] = vsc7514_vcap_regmap,
0035 [S1] = vsc7514_vcap_regmap,
0036 [S2] = vsc7514_vcap_regmap,
0037 [PTP] = vsc7514_ptp_regmap,
0038 [DEV_GMII] = vsc7514_dev_gmii_regmap,
0039 };
0040
0041 static const struct reg_field ocelot_regfields[REGFIELD_MAX] = {
0042 [ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 11, 11),
0043 [ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 10),
0044 [ANA_ANEVENTS_MSTI_DROP] = REG_FIELD(ANA_ANEVENTS, 27, 27),
0045 [ANA_ANEVENTS_ACLKILL] = REG_FIELD(ANA_ANEVENTS, 26, 26),
0046 [ANA_ANEVENTS_ACLUSED] = REG_FIELD(ANA_ANEVENTS, 25, 25),
0047 [ANA_ANEVENTS_AUTOAGE] = REG_FIELD(ANA_ANEVENTS, 24, 24),
0048 [ANA_ANEVENTS_VS2TTL1] = REG_FIELD(ANA_ANEVENTS, 23, 23),
0049 [ANA_ANEVENTS_STORM_DROP] = REG_FIELD(ANA_ANEVENTS, 22, 22),
0050 [ANA_ANEVENTS_LEARN_DROP] = REG_FIELD(ANA_ANEVENTS, 21, 21),
0051 [ANA_ANEVENTS_AGED_ENTRY] = REG_FIELD(ANA_ANEVENTS, 20, 20),
0052 [ANA_ANEVENTS_CPU_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 19, 19),
0053 [ANA_ANEVENTS_AUTO_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 18, 18),
0054 [ANA_ANEVENTS_LEARN_REMOVE] = REG_FIELD(ANA_ANEVENTS, 17, 17),
0055 [ANA_ANEVENTS_AUTO_LEARNED] = REG_FIELD(ANA_ANEVENTS, 16, 16),
0056 [ANA_ANEVENTS_AUTO_MOVED] = REG_FIELD(ANA_ANEVENTS, 15, 15),
0057 [ANA_ANEVENTS_DROPPED] = REG_FIELD(ANA_ANEVENTS, 14, 14),
0058 [ANA_ANEVENTS_CLASSIFIED_DROP] = REG_FIELD(ANA_ANEVENTS, 13, 13),
0059 [ANA_ANEVENTS_CLASSIFIED_COPY] = REG_FIELD(ANA_ANEVENTS, 12, 12),
0060 [ANA_ANEVENTS_VLAN_DISCARD] = REG_FIELD(ANA_ANEVENTS, 11, 11),
0061 [ANA_ANEVENTS_FWD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 10, 10),
0062 [ANA_ANEVENTS_MULTICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 9, 9),
0063 [ANA_ANEVENTS_UNICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 8, 8),
0064 [ANA_ANEVENTS_DEST_KNOWN] = REG_FIELD(ANA_ANEVENTS, 7, 7),
0065 [ANA_ANEVENTS_BUCKET3_MATCH] = REG_FIELD(ANA_ANEVENTS, 6, 6),
0066 [ANA_ANEVENTS_BUCKET2_MATCH] = REG_FIELD(ANA_ANEVENTS, 5, 5),
0067 [ANA_ANEVENTS_BUCKET1_MATCH] = REG_FIELD(ANA_ANEVENTS, 4, 4),
0068 [ANA_ANEVENTS_BUCKET0_MATCH] = REG_FIELD(ANA_ANEVENTS, 3, 3),
0069 [ANA_ANEVENTS_CPU_OPERATION] = REG_FIELD(ANA_ANEVENTS, 2, 2),
0070 [ANA_ANEVENTS_DMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 1, 1),
0071 [ANA_ANEVENTS_SMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 0, 0),
0072 [ANA_TABLES_MACACCESS_B_DOM] = REG_FIELD(ANA_TABLES_MACACCESS, 18, 18),
0073 [ANA_TABLES_MACTINDX_BUCKET] = REG_FIELD(ANA_TABLES_MACTINDX, 10, 11),
0074 [ANA_TABLES_MACTINDX_M_INDEX] = REG_FIELD(ANA_TABLES_MACTINDX, 0, 9),
0075 [QSYS_TIMED_FRAME_ENTRY_TFRM_VLD] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 20, 20),
0076 [QSYS_TIMED_FRAME_ENTRY_TFRM_FP] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 8, 19),
0077 [QSYS_TIMED_FRAME_ENTRY_TFRM_PORTNO] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 4, 7),
0078 [QSYS_TIMED_FRAME_ENTRY_TFRM_TM_SEL] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 1, 3),
0079 [QSYS_TIMED_FRAME_ENTRY_TFRM_TM_T] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 0, 0),
0080 [SYS_RESET_CFG_CORE_ENA] = REG_FIELD(SYS_RESET_CFG, 2, 2),
0081 [SYS_RESET_CFG_MEM_ENA] = REG_FIELD(SYS_RESET_CFG, 1, 1),
0082 [SYS_RESET_CFG_MEM_INIT] = REG_FIELD(SYS_RESET_CFG, 0, 0),
0083
0084 [QSYS_SWITCH_PORT_MODE_PORT_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 14, 14, 12, 4),
0085 [QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 11, 13, 12, 4),
0086 [QSYS_SWITCH_PORT_MODE_YEL_RSRVD] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 10, 10, 12, 4),
0087 [QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 9, 9, 12, 4),
0088 [QSYS_SWITCH_PORT_MODE_TX_PFC_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 1, 8, 12, 4),
0089 [QSYS_SWITCH_PORT_MODE_TX_PFC_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 0, 0, 12, 4),
0090 [SYS_PORT_MODE_DATA_WO_TS] = REG_FIELD_ID(SYS_PORT_MODE, 5, 6, 12, 4),
0091 [SYS_PORT_MODE_INCL_INJ_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 3, 4, 12, 4),
0092 [SYS_PORT_MODE_INCL_XTR_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 1, 2, 12, 4),
0093 [SYS_PORT_MODE_INCL_HDR_ERR] = REG_FIELD_ID(SYS_PORT_MODE, 0, 0, 12, 4),
0094 [SYS_PAUSE_CFG_PAUSE_START] = REG_FIELD_ID(SYS_PAUSE_CFG, 10, 18, 12, 4),
0095 [SYS_PAUSE_CFG_PAUSE_STOP] = REG_FIELD_ID(SYS_PAUSE_CFG, 1, 9, 12, 4),
0096 [SYS_PAUSE_CFG_PAUSE_ENA] = REG_FIELD_ID(SYS_PAUSE_CFG, 0, 1, 12, 4),
0097 };
0098
0099 static const struct ocelot_stat_layout ocelot_stats_layout[OCELOT_NUM_STATS] = {
0100 [OCELOT_STAT_RX_OCTETS] = {
0101 .name = "rx_octets",
0102 .reg = SYS_COUNT_RX_OCTETS,
0103 },
0104 [OCELOT_STAT_RX_UNICAST] = {
0105 .name = "rx_unicast",
0106 .reg = SYS_COUNT_RX_UNICAST,
0107 },
0108 [OCELOT_STAT_RX_MULTICAST] = {
0109 .name = "rx_multicast",
0110 .reg = SYS_COUNT_RX_MULTICAST,
0111 },
0112 [OCELOT_STAT_RX_BROADCAST] = {
0113 .name = "rx_broadcast",
0114 .reg = SYS_COUNT_RX_BROADCAST,
0115 },
0116 [OCELOT_STAT_RX_SHORTS] = {
0117 .name = "rx_shorts",
0118 .reg = SYS_COUNT_RX_SHORTS,
0119 },
0120 [OCELOT_STAT_RX_FRAGMENTS] = {
0121 .name = "rx_fragments",
0122 .reg = SYS_COUNT_RX_FRAGMENTS,
0123 },
0124 [OCELOT_STAT_RX_JABBERS] = {
0125 .name = "rx_jabbers",
0126 .reg = SYS_COUNT_RX_JABBERS,
0127 },
0128 [OCELOT_STAT_RX_CRC_ALIGN_ERRS] = {
0129 .name = "rx_crc_align_errs",
0130 .reg = SYS_COUNT_RX_CRC_ALIGN_ERRS,
0131 },
0132 [OCELOT_STAT_RX_SYM_ERRS] = {
0133 .name = "rx_sym_errs",
0134 .reg = SYS_COUNT_RX_SYM_ERRS,
0135 },
0136 [OCELOT_STAT_RX_64] = {
0137 .name = "rx_frames_below_65_octets",
0138 .reg = SYS_COUNT_RX_64,
0139 },
0140 [OCELOT_STAT_RX_65_127] = {
0141 .name = "rx_frames_65_to_127_octets",
0142 .reg = SYS_COUNT_RX_65_127,
0143 },
0144 [OCELOT_STAT_RX_128_255] = {
0145 .name = "rx_frames_128_to_255_octets",
0146 .reg = SYS_COUNT_RX_128_255,
0147 },
0148 [OCELOT_STAT_RX_256_511] = {
0149 .name = "rx_frames_256_to_511_octets",
0150 .reg = SYS_COUNT_RX_256_511,
0151 },
0152 [OCELOT_STAT_RX_512_1023] = {
0153 .name = "rx_frames_512_to_1023_octets",
0154 .reg = SYS_COUNT_RX_512_1023,
0155 },
0156 [OCELOT_STAT_RX_1024_1526] = {
0157 .name = "rx_frames_1024_to_1526_octets",
0158 .reg = SYS_COUNT_RX_1024_1526,
0159 },
0160 [OCELOT_STAT_RX_1527_MAX] = {
0161 .name = "rx_frames_over_1526_octets",
0162 .reg = SYS_COUNT_RX_1527_MAX,
0163 },
0164 [OCELOT_STAT_RX_PAUSE] = {
0165 .name = "rx_pause",
0166 .reg = SYS_COUNT_RX_PAUSE,
0167 },
0168 [OCELOT_STAT_RX_CONTROL] = {
0169 .name = "rx_control",
0170 .reg = SYS_COUNT_RX_CONTROL,
0171 },
0172 [OCELOT_STAT_RX_LONGS] = {
0173 .name = "rx_longs",
0174 .reg = SYS_COUNT_RX_LONGS,
0175 },
0176 [OCELOT_STAT_RX_CLASSIFIED_DROPS] = {
0177 .name = "rx_classified_drops",
0178 .reg = SYS_COUNT_RX_CLASSIFIED_DROPS,
0179 },
0180 [OCELOT_STAT_RX_RED_PRIO_0] = {
0181 .name = "rx_red_prio_0",
0182 .reg = SYS_COUNT_RX_RED_PRIO_0,
0183 },
0184 [OCELOT_STAT_RX_RED_PRIO_1] = {
0185 .name = "rx_red_prio_1",
0186 .reg = SYS_COUNT_RX_RED_PRIO_1,
0187 },
0188 [OCELOT_STAT_RX_RED_PRIO_2] = {
0189 .name = "rx_red_prio_2",
0190 .reg = SYS_COUNT_RX_RED_PRIO_2,
0191 },
0192 [OCELOT_STAT_RX_RED_PRIO_3] = {
0193 .name = "rx_red_prio_3",
0194 .reg = SYS_COUNT_RX_RED_PRIO_3,
0195 },
0196 [OCELOT_STAT_RX_RED_PRIO_4] = {
0197 .name = "rx_red_prio_4",
0198 .reg = SYS_COUNT_RX_RED_PRIO_4,
0199 },
0200 [OCELOT_STAT_RX_RED_PRIO_5] = {
0201 .name = "rx_red_prio_5",
0202 .reg = SYS_COUNT_RX_RED_PRIO_5,
0203 },
0204 [OCELOT_STAT_RX_RED_PRIO_6] = {
0205 .name = "rx_red_prio_6",
0206 .reg = SYS_COUNT_RX_RED_PRIO_6,
0207 },
0208 [OCELOT_STAT_RX_RED_PRIO_7] = {
0209 .name = "rx_red_prio_7",
0210 .reg = SYS_COUNT_RX_RED_PRIO_7,
0211 },
0212 [OCELOT_STAT_RX_YELLOW_PRIO_0] = {
0213 .name = "rx_yellow_prio_0",
0214 .reg = SYS_COUNT_RX_YELLOW_PRIO_0,
0215 },
0216 [OCELOT_STAT_RX_YELLOW_PRIO_1] = {
0217 .name = "rx_yellow_prio_1",
0218 .reg = SYS_COUNT_RX_YELLOW_PRIO_1,
0219 },
0220 [OCELOT_STAT_RX_YELLOW_PRIO_2] = {
0221 .name = "rx_yellow_prio_2",
0222 .reg = SYS_COUNT_RX_YELLOW_PRIO_2,
0223 },
0224 [OCELOT_STAT_RX_YELLOW_PRIO_3] = {
0225 .name = "rx_yellow_prio_3",
0226 .reg = SYS_COUNT_RX_YELLOW_PRIO_3,
0227 },
0228 [OCELOT_STAT_RX_YELLOW_PRIO_4] = {
0229 .name = "rx_yellow_prio_4",
0230 .reg = SYS_COUNT_RX_YELLOW_PRIO_4,
0231 },
0232 [OCELOT_STAT_RX_YELLOW_PRIO_5] = {
0233 .name = "rx_yellow_prio_5",
0234 .reg = SYS_COUNT_RX_YELLOW_PRIO_5,
0235 },
0236 [OCELOT_STAT_RX_YELLOW_PRIO_6] = {
0237 .name = "rx_yellow_prio_6",
0238 .reg = SYS_COUNT_RX_YELLOW_PRIO_6,
0239 },
0240 [OCELOT_STAT_RX_YELLOW_PRIO_7] = {
0241 .name = "rx_yellow_prio_7",
0242 .reg = SYS_COUNT_RX_YELLOW_PRIO_7,
0243 },
0244 [OCELOT_STAT_RX_GREEN_PRIO_0] = {
0245 .name = "rx_green_prio_0",
0246 .reg = SYS_COUNT_RX_GREEN_PRIO_0,
0247 },
0248 [OCELOT_STAT_RX_GREEN_PRIO_1] = {
0249 .name = "rx_green_prio_1",
0250 .reg = SYS_COUNT_RX_GREEN_PRIO_1,
0251 },
0252 [OCELOT_STAT_RX_GREEN_PRIO_2] = {
0253 .name = "rx_green_prio_2",
0254 .reg = SYS_COUNT_RX_GREEN_PRIO_2,
0255 },
0256 [OCELOT_STAT_RX_GREEN_PRIO_3] = {
0257 .name = "rx_green_prio_3",
0258 .reg = SYS_COUNT_RX_GREEN_PRIO_3,
0259 },
0260 [OCELOT_STAT_RX_GREEN_PRIO_4] = {
0261 .name = "rx_green_prio_4",
0262 .reg = SYS_COUNT_RX_GREEN_PRIO_4,
0263 },
0264 [OCELOT_STAT_RX_GREEN_PRIO_5] = {
0265 .name = "rx_green_prio_5",
0266 .reg = SYS_COUNT_RX_GREEN_PRIO_5,
0267 },
0268 [OCELOT_STAT_RX_GREEN_PRIO_6] = {
0269 .name = "rx_green_prio_6",
0270 .reg = SYS_COUNT_RX_GREEN_PRIO_6,
0271 },
0272 [OCELOT_STAT_RX_GREEN_PRIO_7] = {
0273 .name = "rx_green_prio_7",
0274 .reg = SYS_COUNT_RX_GREEN_PRIO_7,
0275 },
0276 [OCELOT_STAT_TX_OCTETS] = {
0277 .name = "tx_octets",
0278 .reg = SYS_COUNT_TX_OCTETS,
0279 },
0280 [OCELOT_STAT_TX_UNICAST] = {
0281 .name = "tx_unicast",
0282 .reg = SYS_COUNT_TX_UNICAST,
0283 },
0284 [OCELOT_STAT_TX_MULTICAST] = {
0285 .name = "tx_multicast",
0286 .reg = SYS_COUNT_TX_MULTICAST,
0287 },
0288 [OCELOT_STAT_TX_BROADCAST] = {
0289 .name = "tx_broadcast",
0290 .reg = SYS_COUNT_TX_BROADCAST,
0291 },
0292 [OCELOT_STAT_TX_COLLISION] = {
0293 .name = "tx_collision",
0294 .reg = SYS_COUNT_TX_COLLISION,
0295 },
0296 [OCELOT_STAT_TX_DROPS] = {
0297 .name = "tx_drops",
0298 .reg = SYS_COUNT_TX_DROPS,
0299 },
0300 [OCELOT_STAT_TX_PAUSE] = {
0301 .name = "tx_pause",
0302 .reg = SYS_COUNT_TX_PAUSE,
0303 },
0304 [OCELOT_STAT_TX_64] = {
0305 .name = "tx_frames_below_65_octets",
0306 .reg = SYS_COUNT_TX_64,
0307 },
0308 [OCELOT_STAT_TX_65_127] = {
0309 .name = "tx_frames_65_to_127_octets",
0310 .reg = SYS_COUNT_TX_65_127,
0311 },
0312 [OCELOT_STAT_TX_128_255] = {
0313 .name = "tx_frames_128_255_octets",
0314 .reg = SYS_COUNT_TX_128_255,
0315 },
0316 [OCELOT_STAT_TX_256_511] = {
0317 .name = "tx_frames_256_511_octets",
0318 .reg = SYS_COUNT_TX_256_511,
0319 },
0320 [OCELOT_STAT_TX_512_1023] = {
0321 .name = "tx_frames_512_1023_octets",
0322 .reg = SYS_COUNT_TX_512_1023,
0323 },
0324 [OCELOT_STAT_TX_1024_1526] = {
0325 .name = "tx_frames_1024_1526_octets",
0326 .reg = SYS_COUNT_TX_1024_1526,
0327 },
0328 [OCELOT_STAT_TX_1527_MAX] = {
0329 .name = "tx_frames_over_1526_octets",
0330 .reg = SYS_COUNT_TX_1527_MAX,
0331 },
0332 [OCELOT_STAT_TX_YELLOW_PRIO_0] = {
0333 .name = "tx_yellow_prio_0",
0334 .reg = SYS_COUNT_TX_YELLOW_PRIO_0,
0335 },
0336 [OCELOT_STAT_TX_YELLOW_PRIO_1] = {
0337 .name = "tx_yellow_prio_1",
0338 .reg = SYS_COUNT_TX_YELLOW_PRIO_1,
0339 },
0340 [OCELOT_STAT_TX_YELLOW_PRIO_2] = {
0341 .name = "tx_yellow_prio_2",
0342 .reg = SYS_COUNT_TX_YELLOW_PRIO_2,
0343 },
0344 [OCELOT_STAT_TX_YELLOW_PRIO_3] = {
0345 .name = "tx_yellow_prio_3",
0346 .reg = SYS_COUNT_TX_YELLOW_PRIO_3,
0347 },
0348 [OCELOT_STAT_TX_YELLOW_PRIO_4] = {
0349 .name = "tx_yellow_prio_4",
0350 .reg = SYS_COUNT_TX_YELLOW_PRIO_4,
0351 },
0352 [OCELOT_STAT_TX_YELLOW_PRIO_5] = {
0353 .name = "tx_yellow_prio_5",
0354 .reg = SYS_COUNT_TX_YELLOW_PRIO_5,
0355 },
0356 [OCELOT_STAT_TX_YELLOW_PRIO_6] = {
0357 .name = "tx_yellow_prio_6",
0358 .reg = SYS_COUNT_TX_YELLOW_PRIO_6,
0359 },
0360 [OCELOT_STAT_TX_YELLOW_PRIO_7] = {
0361 .name = "tx_yellow_prio_7",
0362 .reg = SYS_COUNT_TX_YELLOW_PRIO_7,
0363 },
0364 [OCELOT_STAT_TX_GREEN_PRIO_0] = {
0365 .name = "tx_green_prio_0",
0366 .reg = SYS_COUNT_TX_GREEN_PRIO_0,
0367 },
0368 [OCELOT_STAT_TX_GREEN_PRIO_1] = {
0369 .name = "tx_green_prio_1",
0370 .reg = SYS_COUNT_TX_GREEN_PRIO_1,
0371 },
0372 [OCELOT_STAT_TX_GREEN_PRIO_2] = {
0373 .name = "tx_green_prio_2",
0374 .reg = SYS_COUNT_TX_GREEN_PRIO_2,
0375 },
0376 [OCELOT_STAT_TX_GREEN_PRIO_3] = {
0377 .name = "tx_green_prio_3",
0378 .reg = SYS_COUNT_TX_GREEN_PRIO_3,
0379 },
0380 [OCELOT_STAT_TX_GREEN_PRIO_4] = {
0381 .name = "tx_green_prio_4",
0382 .reg = SYS_COUNT_TX_GREEN_PRIO_4,
0383 },
0384 [OCELOT_STAT_TX_GREEN_PRIO_5] = {
0385 .name = "tx_green_prio_5",
0386 .reg = SYS_COUNT_TX_GREEN_PRIO_5,
0387 },
0388 [OCELOT_STAT_TX_GREEN_PRIO_6] = {
0389 .name = "tx_green_prio_6",
0390 .reg = SYS_COUNT_TX_GREEN_PRIO_6,
0391 },
0392 [OCELOT_STAT_TX_GREEN_PRIO_7] = {
0393 .name = "tx_green_prio_7",
0394 .reg = SYS_COUNT_TX_GREEN_PRIO_7,
0395 },
0396 [OCELOT_STAT_TX_AGED] = {
0397 .name = "tx_aged",
0398 .reg = SYS_COUNT_TX_AGING,
0399 },
0400 [OCELOT_STAT_DROP_LOCAL] = {
0401 .name = "drop_local",
0402 .reg = SYS_COUNT_DROP_LOCAL,
0403 },
0404 [OCELOT_STAT_DROP_TAIL] = {
0405 .name = "drop_tail",
0406 .reg = SYS_COUNT_DROP_TAIL,
0407 },
0408 [OCELOT_STAT_DROP_YELLOW_PRIO_0] = {
0409 .name = "drop_yellow_prio_0",
0410 .reg = SYS_COUNT_DROP_YELLOW_PRIO_0,
0411 },
0412 [OCELOT_STAT_DROP_YELLOW_PRIO_1] = {
0413 .name = "drop_yellow_prio_1",
0414 .reg = SYS_COUNT_DROP_YELLOW_PRIO_1,
0415 },
0416 [OCELOT_STAT_DROP_YELLOW_PRIO_2] = {
0417 .name = "drop_yellow_prio_2",
0418 .reg = SYS_COUNT_DROP_YELLOW_PRIO_2,
0419 },
0420 [OCELOT_STAT_DROP_YELLOW_PRIO_3] = {
0421 .name = "drop_yellow_prio_3",
0422 .reg = SYS_COUNT_DROP_YELLOW_PRIO_3,
0423 },
0424 [OCELOT_STAT_DROP_YELLOW_PRIO_4] = {
0425 .name = "drop_yellow_prio_4",
0426 .reg = SYS_COUNT_DROP_YELLOW_PRIO_4,
0427 },
0428 [OCELOT_STAT_DROP_YELLOW_PRIO_5] = {
0429 .name = "drop_yellow_prio_5",
0430 .reg = SYS_COUNT_DROP_YELLOW_PRIO_5,
0431 },
0432 [OCELOT_STAT_DROP_YELLOW_PRIO_6] = {
0433 .name = "drop_yellow_prio_6",
0434 .reg = SYS_COUNT_DROP_YELLOW_PRIO_6,
0435 },
0436 [OCELOT_STAT_DROP_YELLOW_PRIO_7] = {
0437 .name = "drop_yellow_prio_7",
0438 .reg = SYS_COUNT_DROP_YELLOW_PRIO_7,
0439 },
0440 [OCELOT_STAT_DROP_GREEN_PRIO_0] = {
0441 .name = "drop_green_prio_0",
0442 .reg = SYS_COUNT_DROP_GREEN_PRIO_0,
0443 },
0444 [OCELOT_STAT_DROP_GREEN_PRIO_1] = {
0445 .name = "drop_green_prio_1",
0446 .reg = SYS_COUNT_DROP_GREEN_PRIO_1,
0447 },
0448 [OCELOT_STAT_DROP_GREEN_PRIO_2] = {
0449 .name = "drop_green_prio_2",
0450 .reg = SYS_COUNT_DROP_GREEN_PRIO_2,
0451 },
0452 [OCELOT_STAT_DROP_GREEN_PRIO_3] = {
0453 .name = "drop_green_prio_3",
0454 .reg = SYS_COUNT_DROP_GREEN_PRIO_3,
0455 },
0456 [OCELOT_STAT_DROP_GREEN_PRIO_4] = {
0457 .name = "drop_green_prio_4",
0458 .reg = SYS_COUNT_DROP_GREEN_PRIO_4,
0459 },
0460 [OCELOT_STAT_DROP_GREEN_PRIO_5] = {
0461 .name = "drop_green_prio_5",
0462 .reg = SYS_COUNT_DROP_GREEN_PRIO_5,
0463 },
0464 [OCELOT_STAT_DROP_GREEN_PRIO_6] = {
0465 .name = "drop_green_prio_6",
0466 .reg = SYS_COUNT_DROP_GREEN_PRIO_6,
0467 },
0468 [OCELOT_STAT_DROP_GREEN_PRIO_7] = {
0469 .name = "drop_green_prio_7",
0470 .reg = SYS_COUNT_DROP_GREEN_PRIO_7,
0471 },
0472 };
0473
0474 static void ocelot_pll5_init(struct ocelot *ocelot)
0475 {
0476
0477
0478
0479 regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG4,
0480 HSIO_PLL5G_CFG4_IB_CTRL(0x7600) |
0481 HSIO_PLL5G_CFG4_IB_BIAS_CTRL(0x8));
0482 regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG0,
0483 HSIO_PLL5G_CFG0_CORE_CLK_DIV(0x11) |
0484 HSIO_PLL5G_CFG0_CPU_CLK_DIV(2) |
0485 HSIO_PLL5G_CFG0_ENA_BIAS |
0486 HSIO_PLL5G_CFG0_ENA_VCO_BUF |
0487 HSIO_PLL5G_CFG0_ENA_CP1 |
0488 HSIO_PLL5G_CFG0_SELCPI(2) |
0489 HSIO_PLL5G_CFG0_LOOP_BW_RES(0xe) |
0490 HSIO_PLL5G_CFG0_SELBGV820(4) |
0491 HSIO_PLL5G_CFG0_DIV4 |
0492 HSIO_PLL5G_CFG0_ENA_CLKTREE |
0493 HSIO_PLL5G_CFG0_ENA_LANE);
0494 regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG2,
0495 HSIO_PLL5G_CFG2_EN_RESET_FRQ_DET |
0496 HSIO_PLL5G_CFG2_EN_RESET_OVERRUN |
0497 HSIO_PLL5G_CFG2_GAIN_TEST(0x8) |
0498 HSIO_PLL5G_CFG2_ENA_AMPCTRL |
0499 HSIO_PLL5G_CFG2_PWD_AMPCTRL_N |
0500 HSIO_PLL5G_CFG2_AMPC_SEL(0x10));
0501 }
0502
0503 static int ocelot_chip_init(struct ocelot *ocelot, const struct ocelot_ops *ops)
0504 {
0505 int ret;
0506
0507 ocelot->map = ocelot_regmap;
0508 ocelot->stats_layout = ocelot_stats_layout;
0509 ocelot->num_mact_rows = 1024;
0510 ocelot->ops = ops;
0511
0512 ret = ocelot_regfields_init(ocelot, ocelot_regfields);
0513 if (ret)
0514 return ret;
0515
0516 ocelot_pll5_init(ocelot);
0517
0518 eth_random_addr(ocelot->base_mac);
0519 ocelot->base_mac[5] &= 0xf0;
0520
0521 return 0;
0522 }
0523
0524 static irqreturn_t ocelot_xtr_irq_handler(int irq, void *arg)
0525 {
0526 struct ocelot *ocelot = arg;
0527 int grp = 0, err;
0528
0529 while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp)) {
0530 struct sk_buff *skb;
0531
0532 err = ocelot_xtr_poll_frame(ocelot, grp, &skb);
0533 if (err)
0534 goto out;
0535
0536 skb->dev->stats.rx_bytes += skb->len;
0537 skb->dev->stats.rx_packets++;
0538
0539 if (!skb_defer_rx_timestamp(skb))
0540 netif_rx(skb);
0541 }
0542
0543 out:
0544 if (err < 0)
0545 ocelot_drain_cpu_queue(ocelot, 0);
0546
0547 return IRQ_HANDLED;
0548 }
0549
0550 static irqreturn_t ocelot_ptp_rdy_irq_handler(int irq, void *arg)
0551 {
0552 struct ocelot *ocelot = arg;
0553
0554 ocelot_get_txtstamp(ocelot);
0555
0556 return IRQ_HANDLED;
0557 }
0558
0559 static const struct of_device_id mscc_ocelot_match[] = {
0560 { .compatible = "mscc,vsc7514-switch" },
0561 { }
0562 };
0563 MODULE_DEVICE_TABLE(of, mscc_ocelot_match);
0564
0565 static int ocelot_reset(struct ocelot *ocelot)
0566 {
0567 int retries = 100;
0568 u32 val;
0569
0570 regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_INIT], 1);
0571 regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_ENA], 1);
0572
0573 do {
0574 msleep(1);
0575 regmap_field_read(ocelot->regfields[SYS_RESET_CFG_MEM_INIT],
0576 &val);
0577 } while (val && --retries);
0578
0579 if (!retries)
0580 return -ETIMEDOUT;
0581
0582 regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_ENA], 1);
0583 regmap_field_write(ocelot->regfields[SYS_RESET_CFG_CORE_ENA], 1);
0584
0585 return 0;
0586 }
0587
0588
0589
0590
0591
0592 static u16 ocelot_wm_enc(u16 value)
0593 {
0594 WARN_ON(value >= 16 * BIT(8));
0595
0596 if (value >= BIT(8))
0597 return BIT(8) | (value / 16);
0598
0599 return value;
0600 }
0601
0602 static u16 ocelot_wm_dec(u16 wm)
0603 {
0604 if (wm & BIT(8))
0605 return (wm & GENMASK(7, 0)) * 16;
0606
0607 return wm;
0608 }
0609
0610 static void ocelot_wm_stat(u32 val, u32 *inuse, u32 *maxuse)
0611 {
0612 *inuse = (val & GENMASK(23, 12)) >> 12;
0613 *maxuse = val & GENMASK(11, 0);
0614 }
0615
0616 static const struct ocelot_ops ocelot_ops = {
0617 .reset = ocelot_reset,
0618 .wm_enc = ocelot_wm_enc,
0619 .wm_dec = ocelot_wm_dec,
0620 .wm_stat = ocelot_wm_stat,
0621 .port_to_netdev = ocelot_port_to_netdev,
0622 .netdev_to_port = ocelot_netdev_to_port,
0623 };
0624
0625 static struct vcap_props vsc7514_vcap_props[] = {
0626 [VCAP_ES0] = {
0627 .action_type_width = 0,
0628 .action_table = {
0629 [ES0_ACTION_TYPE_NORMAL] = {
0630 .width = 73,
0631 .count = 1,
0632 },
0633 },
0634 .target = S0,
0635 .keys = vsc7514_vcap_es0_keys,
0636 .actions = vsc7514_vcap_es0_actions,
0637 },
0638 [VCAP_IS1] = {
0639 .action_type_width = 0,
0640 .action_table = {
0641 [IS1_ACTION_TYPE_NORMAL] = {
0642 .width = 78,
0643 .count = 4,
0644 },
0645 },
0646 .target = S1,
0647 .keys = vsc7514_vcap_is1_keys,
0648 .actions = vsc7514_vcap_is1_actions,
0649 },
0650 [VCAP_IS2] = {
0651 .action_type_width = 1,
0652 .action_table = {
0653 [IS2_ACTION_TYPE_NORMAL] = {
0654 .width = 49,
0655 .count = 2
0656 },
0657 [IS2_ACTION_TYPE_SMAC_SIP] = {
0658 .width = 6,
0659 .count = 4
0660 },
0661 },
0662 .target = S2,
0663 .keys = vsc7514_vcap_is2_keys,
0664 .actions = vsc7514_vcap_is2_actions,
0665 },
0666 };
0667
0668 static struct ptp_clock_info ocelot_ptp_clock_info = {
0669 .owner = THIS_MODULE,
0670 .name = "ocelot ptp",
0671 .max_adj = 0x7fffffff,
0672 .n_alarm = 0,
0673 .n_ext_ts = 0,
0674 .n_per_out = OCELOT_PTP_PINS_NUM,
0675 .n_pins = OCELOT_PTP_PINS_NUM,
0676 .pps = 0,
0677 .gettime64 = ocelot_ptp_gettime64,
0678 .settime64 = ocelot_ptp_settime64,
0679 .adjtime = ocelot_ptp_adjtime,
0680 .adjfine = ocelot_ptp_adjfine,
0681 .verify = ocelot_ptp_verify,
0682 .enable = ocelot_ptp_enable,
0683 };
0684
0685 static void mscc_ocelot_teardown_devlink_ports(struct ocelot *ocelot)
0686 {
0687 int port;
0688
0689 for (port = 0; port < ocelot->num_phys_ports; port++)
0690 ocelot_port_devlink_teardown(ocelot, port);
0691 }
0692
0693 static void mscc_ocelot_release_ports(struct ocelot *ocelot)
0694 {
0695 int port;
0696
0697 for (port = 0; port < ocelot->num_phys_ports; port++) {
0698 struct ocelot_port *ocelot_port;
0699
0700 ocelot_port = ocelot->ports[port];
0701 if (!ocelot_port)
0702 continue;
0703
0704 ocelot_deinit_port(ocelot, port);
0705 ocelot_release_port(ocelot_port);
0706 }
0707 }
0708
0709 static int mscc_ocelot_init_ports(struct platform_device *pdev,
0710 struct device_node *ports)
0711 {
0712 struct ocelot *ocelot = platform_get_drvdata(pdev);
0713 u32 devlink_ports_registered = 0;
0714 struct device_node *portnp;
0715 int port, err;
0716 u32 reg;
0717
0718 ocelot->ports = devm_kcalloc(ocelot->dev, ocelot->num_phys_ports,
0719 sizeof(struct ocelot_port *), GFP_KERNEL);
0720 if (!ocelot->ports)
0721 return -ENOMEM;
0722
0723 ocelot->devlink_ports = devm_kcalloc(ocelot->dev,
0724 ocelot->num_phys_ports,
0725 sizeof(*ocelot->devlink_ports),
0726 GFP_KERNEL);
0727 if (!ocelot->devlink_ports)
0728 return -ENOMEM;
0729
0730 for_each_available_child_of_node(ports, portnp) {
0731 struct ocelot_port_private *priv;
0732 struct ocelot_port *ocelot_port;
0733 struct devlink_port *dlp;
0734 struct regmap *target;
0735 struct resource *res;
0736 char res_name[8];
0737
0738 if (of_property_read_u32(portnp, "reg", ®))
0739 continue;
0740
0741 port = reg;
0742 if (port < 0 || port >= ocelot->num_phys_ports) {
0743 dev_err(ocelot->dev,
0744 "invalid port number: %d >= %d\n", port,
0745 ocelot->num_phys_ports);
0746 continue;
0747 }
0748
0749 snprintf(res_name, sizeof(res_name), "port%d", port);
0750
0751 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
0752 res_name);
0753 target = ocelot_regmap_init(ocelot, res);
0754 if (IS_ERR(target)) {
0755 err = PTR_ERR(target);
0756 of_node_put(portnp);
0757 goto out_teardown;
0758 }
0759
0760 err = ocelot_port_devlink_init(ocelot, port,
0761 DEVLINK_PORT_FLAVOUR_PHYSICAL);
0762 if (err) {
0763 of_node_put(portnp);
0764 goto out_teardown;
0765 }
0766
0767 err = ocelot_probe_port(ocelot, port, target, portnp);
0768 if (err) {
0769 ocelot_port_devlink_teardown(ocelot, port);
0770 continue;
0771 }
0772
0773 devlink_ports_registered |= BIT(port);
0774
0775 ocelot_port = ocelot->ports[port];
0776 priv = container_of(ocelot_port, struct ocelot_port_private,
0777 port);
0778 dlp = &ocelot->devlink_ports[port];
0779 devlink_port_type_eth_set(dlp, priv->dev);
0780 }
0781
0782
0783 for (port = 0; port < ocelot->num_phys_ports; port++) {
0784 if (devlink_ports_registered & BIT(port))
0785 continue;
0786
0787 err = ocelot_port_devlink_init(ocelot, port,
0788 DEVLINK_PORT_FLAVOUR_UNUSED);
0789 if (err)
0790 goto out_teardown;
0791
0792 devlink_ports_registered |= BIT(port);
0793 }
0794
0795 return 0;
0796
0797 out_teardown:
0798
0799 mscc_ocelot_release_ports(ocelot);
0800
0801 for (port = 0; port < ocelot->num_phys_ports; port++) {
0802 if (devlink_ports_registered & BIT(port))
0803 ocelot_port_devlink_teardown(ocelot, port);
0804 }
0805 return err;
0806 }
0807
0808 static int mscc_ocelot_probe(struct platform_device *pdev)
0809 {
0810 struct device_node *np = pdev->dev.of_node;
0811 int err, irq_xtr, irq_ptp_rdy;
0812 struct device_node *ports;
0813 struct devlink *devlink;
0814 struct ocelot *ocelot;
0815 struct regmap *hsio;
0816 unsigned int i;
0817
0818 struct {
0819 enum ocelot_target id;
0820 char *name;
0821 u8 optional:1;
0822 } io_target[] = {
0823 { SYS, "sys" },
0824 { REW, "rew" },
0825 { QSYS, "qsys" },
0826 { ANA, "ana" },
0827 { QS, "qs" },
0828 { S0, "s0" },
0829 { S1, "s1" },
0830 { S2, "s2" },
0831 { PTP, "ptp", 1 },
0832 { FDMA, "fdma", 1 },
0833 };
0834
0835 if (!np && !pdev->dev.platform_data)
0836 return -ENODEV;
0837
0838 devlink =
0839 devlink_alloc(&ocelot_devlink_ops, sizeof(*ocelot), &pdev->dev);
0840 if (!devlink)
0841 return -ENOMEM;
0842
0843 ocelot = devlink_priv(devlink);
0844 ocelot->devlink = priv_to_devlink(ocelot);
0845 platform_set_drvdata(pdev, ocelot);
0846 ocelot->dev = &pdev->dev;
0847
0848 for (i = 0; i < ARRAY_SIZE(io_target); i++) {
0849 struct regmap *target;
0850 struct resource *res;
0851
0852 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
0853 io_target[i].name);
0854
0855 target = ocelot_regmap_init(ocelot, res);
0856 if (IS_ERR(target)) {
0857 if (io_target[i].optional) {
0858 ocelot->targets[io_target[i].id] = NULL;
0859 continue;
0860 }
0861 err = PTR_ERR(target);
0862 goto out_free_devlink;
0863 }
0864
0865 ocelot->targets[io_target[i].id] = target;
0866 }
0867
0868 if (ocelot->targets[FDMA])
0869 ocelot_fdma_init(pdev, ocelot);
0870
0871 hsio = syscon_regmap_lookup_by_compatible("mscc,ocelot-hsio");
0872 if (IS_ERR(hsio)) {
0873 dev_err(&pdev->dev, "missing hsio syscon\n");
0874 err = PTR_ERR(hsio);
0875 goto out_free_devlink;
0876 }
0877
0878 ocelot->targets[HSIO] = hsio;
0879
0880 err = ocelot_chip_init(ocelot, &ocelot_ops);
0881 if (err)
0882 goto out_free_devlink;
0883
0884 irq_xtr = platform_get_irq_byname(pdev, "xtr");
0885 if (irq_xtr < 0) {
0886 err = irq_xtr;
0887 goto out_free_devlink;
0888 }
0889
0890 err = devm_request_threaded_irq(&pdev->dev, irq_xtr, NULL,
0891 ocelot_xtr_irq_handler, IRQF_ONESHOT,
0892 "frame extraction", ocelot);
0893 if (err)
0894 goto out_free_devlink;
0895
0896 irq_ptp_rdy = platform_get_irq_byname(pdev, "ptp_rdy");
0897 if (irq_ptp_rdy > 0 && ocelot->targets[PTP]) {
0898 err = devm_request_threaded_irq(&pdev->dev, irq_ptp_rdy, NULL,
0899 ocelot_ptp_rdy_irq_handler,
0900 IRQF_ONESHOT, "ptp ready",
0901 ocelot);
0902 if (err)
0903 goto out_free_devlink;
0904
0905
0906 ocelot->ptp = 1;
0907 }
0908
0909 ports = of_get_child_by_name(np, "ethernet-ports");
0910 if (!ports) {
0911 dev_err(ocelot->dev, "no ethernet-ports child node found\n");
0912 err = -ENODEV;
0913 goto out_free_devlink;
0914 }
0915
0916 ocelot->num_phys_ports = of_get_child_count(ports);
0917 ocelot->num_flooding_pgids = 1;
0918
0919 ocelot->vcap = vsc7514_vcap_props;
0920
0921 ocelot->vcap_pol.base = VSC7514_VCAP_POLICER_BASE;
0922 ocelot->vcap_pol.max = VSC7514_VCAP_POLICER_MAX;
0923
0924 ocelot->npi = -1;
0925
0926 err = ocelot_init(ocelot);
0927 if (err)
0928 goto out_put_ports;
0929
0930 err = mscc_ocelot_init_ports(pdev, ports);
0931 if (err)
0932 goto out_ocelot_devlink_unregister;
0933
0934 if (ocelot->fdma)
0935 ocelot_fdma_start(ocelot);
0936
0937 err = ocelot_devlink_sb_register(ocelot);
0938 if (err)
0939 goto out_ocelot_release_ports;
0940
0941 if (ocelot->ptp) {
0942 err = ocelot_init_timestamp(ocelot, &ocelot_ptp_clock_info);
0943 if (err) {
0944 dev_err(ocelot->dev,
0945 "Timestamp initialization failed\n");
0946 ocelot->ptp = 0;
0947 }
0948 }
0949
0950 register_netdevice_notifier(&ocelot_netdevice_nb);
0951 register_switchdev_notifier(&ocelot_switchdev_nb);
0952 register_switchdev_blocking_notifier(&ocelot_switchdev_blocking_nb);
0953
0954 of_node_put(ports);
0955 devlink_register(devlink);
0956
0957 dev_info(&pdev->dev, "Ocelot switch probed\n");
0958
0959 return 0;
0960
0961 out_ocelot_release_ports:
0962 mscc_ocelot_release_ports(ocelot);
0963 mscc_ocelot_teardown_devlink_ports(ocelot);
0964 out_ocelot_devlink_unregister:
0965 ocelot_deinit(ocelot);
0966 out_put_ports:
0967 of_node_put(ports);
0968 out_free_devlink:
0969 devlink_free(devlink);
0970 return err;
0971 }
0972
0973 static int mscc_ocelot_remove(struct platform_device *pdev)
0974 {
0975 struct ocelot *ocelot = platform_get_drvdata(pdev);
0976
0977 if (ocelot->fdma)
0978 ocelot_fdma_deinit(ocelot);
0979 devlink_unregister(ocelot->devlink);
0980 ocelot_deinit_timestamp(ocelot);
0981 ocelot_devlink_sb_unregister(ocelot);
0982 mscc_ocelot_release_ports(ocelot);
0983 mscc_ocelot_teardown_devlink_ports(ocelot);
0984 ocelot_deinit(ocelot);
0985 unregister_switchdev_blocking_notifier(&ocelot_switchdev_blocking_nb);
0986 unregister_switchdev_notifier(&ocelot_switchdev_nb);
0987 unregister_netdevice_notifier(&ocelot_netdevice_nb);
0988 devlink_free(ocelot->devlink);
0989
0990 return 0;
0991 }
0992
0993 static struct platform_driver mscc_ocelot_driver = {
0994 .probe = mscc_ocelot_probe,
0995 .remove = mscc_ocelot_remove,
0996 .driver = {
0997 .name = "ocelot-switch",
0998 .of_match_table = mscc_ocelot_match,
0999 },
1000 };
1001
1002 module_platform_driver(mscc_ocelot_driver);
1003
1004 MODULE_DESCRIPTION("Microsemi Ocelot switch driver");
1005 MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@bootlin.com>");
1006 MODULE_LICENSE("Dual MIT/GPL");
