ethernet/mscc/ocelot_qs.h

0001 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
0002 /*
0003  * Microsemi Ocelot Switch driver
0004  *
0005  * Copyright (c) 2017 Microsemi Corporation
0006  */
0007
0008 #ifndef _MSCC_OCELOT_QS_H_
0009 #define _MSCC_OCELOT_QS_H_
0010
0011 /* TODO handle BE */
0012 #define XTR_EOF_0          0x00000080U
0013 #define XTR_EOF_1          0x01000080U
0014 #define XTR_EOF_2          0x02000080U
0015 #define XTR_EOF_3          0x03000080U
0016 #define XTR_PRUNED         0x04000080U
0017 #define XTR_ABORT          0x05000080U
0018 #define XTR_ESCAPE         0x06000080U
0019 #define XTR_NOT_READY      0x07000080U
0020 #define XTR_VALID_BYTES(x) (4 - (((x) >> 24) & 3))
0021
0022 #define QS_XTR_GRP_CFG_RSZ                                0x4
0023
0024 #define QS_XTR_GRP_CFG_MODE(x)                            (((x) << 2) & GENMASK(3, 2))
0025 #define QS_XTR_GRP_CFG_MODE_M                             GENMASK(3, 2)
0026 #define QS_XTR_GRP_CFG_MODE_X(x)                          (((x) & GENMASK(3, 2)) >> 2)
0027 #define QS_XTR_GRP_CFG_STATUS_WORD_POS                    BIT(1)
0028 #define QS_XTR_GRP_CFG_BYTE_SWAP                          BIT(0)
0029
0030 #define QS_XTR_RD_RSZ                                     0x4
0031
0032 #define QS_XTR_FRM_PRUNING_RSZ                            0x4
0033
0034 #define QS_XTR_CFG_DP_WM(x)                               (((x) << 5) & GENMASK(7, 5))
0035 #define QS_XTR_CFG_DP_WM_M                                GENMASK(7, 5)
0036 #define QS_XTR_CFG_DP_WM_X(x)                             (((x) & GENMASK(7, 5)) >> 5)
0037 #define QS_XTR_CFG_SCH_WM(x)                              (((x) << 2) & GENMASK(4, 2))
0038 #define QS_XTR_CFG_SCH_WM_M                               GENMASK(4, 2)
0039 #define QS_XTR_CFG_SCH_WM_X(x)                            (((x) & GENMASK(4, 2)) >> 2)
0040 #define QS_XTR_CFG_OFLW_ERR_STICKY(x)                     ((x) & GENMASK(1, 0))
0041 #define QS_XTR_CFG_OFLW_ERR_STICKY_M                      GENMASK(1, 0)
0042
0043 #define QS_INJ_GRP_CFG_RSZ                                0x4
0044
0045 #define QS_INJ_GRP_CFG_MODE(x)                            (((x) << 2) & GENMASK(3, 2))
0046 #define QS_INJ_GRP_CFG_MODE_M                             GENMASK(3, 2)
0047 #define QS_INJ_GRP_CFG_MODE_X(x)                          (((x) & GENMASK(3, 2)) >> 2)
0048 #define QS_INJ_GRP_CFG_BYTE_SWAP                          BIT(0)
0049
0050 #define QS_INJ_WR_RSZ                                     0x4
0051
0052 #define QS_INJ_CTRL_RSZ                                   0x4
0053
0054 #define QS_INJ_CTRL_GAP_SIZE(x)                           (((x) << 21) & GENMASK(24, 21))
0055 #define QS_INJ_CTRL_GAP_SIZE_M                            GENMASK(24, 21)
0056 #define QS_INJ_CTRL_GAP_SIZE_X(x)                         (((x) & GENMASK(24, 21)) >> 21)
0057 #define QS_INJ_CTRL_ABORT                                 BIT(20)
0058 #define QS_INJ_CTRL_EOF                                   BIT(19)
0059 #define QS_INJ_CTRL_SOF                                   BIT(18)
0060 #define QS_INJ_CTRL_VLD_BYTES(x)                          (((x) << 16) & GENMASK(17, 16))
0061 #define QS_INJ_CTRL_VLD_BYTES_M                           GENMASK(17, 16)
0062 #define QS_INJ_CTRL_VLD_BYTES_X(x)                        (((x) & GENMASK(17, 16)) >> 16)
0063
0064 #define QS_INJ_STATUS_WMARK_REACHED(x)                    (((x) << 4) & GENMASK(5, 4))
0065 #define QS_INJ_STATUS_WMARK_REACHED_M                     GENMASK(5, 4)
0066 #define QS_INJ_STATUS_WMARK_REACHED_X(x)                  (((x) & GENMASK(5, 4)) >> 4)
0067 #define QS_INJ_STATUS_FIFO_RDY(x)                         (((x) << 2) & GENMASK(3, 2))
0068 #define QS_INJ_STATUS_FIFO_RDY_M                          GENMASK(3, 2)
0069 #define QS_INJ_STATUS_FIFO_RDY_X(x)                       (((x) & GENMASK(3, 2)) >> 2)
0070 #define QS_INJ_STATUS_INJ_IN_PROGRESS(x)                  ((x) & GENMASK(1, 0))
0071 #define QS_INJ_STATUS_INJ_IN_PROGRESS_M                   GENMASK(1, 0)
0072
0073 #define QS_INJ_ERR_RSZ                                    0x4
0074
0075 #define QS_INJ_ERR_ABORT_ERR_STICKY                       BIT(1)
0076 #define QS_INJ_ERR_WR_ERR_STICKY                          BIT(0)
0077
0078 #endif