ethernet/moxa/moxart_ether.h

0001 /* MOXA ART Ethernet (RTL8201CP) driver.
0002  *
0003  * Copyright (C) 2013 Jonas Jensen
0004  *
0005  * Jonas Jensen <jonas.jensen@gmail.com>
0006  *
0007  * Based on code from
0008  * Moxa Technology Co., Ltd. <www.moxa.com>
0009  *
0010  * This file is licensed under the terms of the GNU General Public
0011  * License version 2.  This program is licensed "as is" without any
0012  * warranty of any kind, whether express or implied.
0013  */
0014
0015 #ifndef _MOXART_ETHERNET_H
0016 #define _MOXART_ETHERNET_H
0017
0018 #define TX_REG_OFFSET_DESC0 0
0019 #define TX_REG_OFFSET_DESC1 4
0020 #define TX_REG_OFFSET_DESC2 8
0021 #define TX_REG_DESC_SIZE    16
0022
0023 #define RX_REG_OFFSET_DESC0 0
0024 #define RX_REG_OFFSET_DESC1 4
0025 #define RX_REG_OFFSET_DESC2 8
0026 #define RX_REG_DESC_SIZE    16
0027
0028 #define TX_DESC0_PKT_LATE_COL   0x1     /* abort, late collision */
0029 #define TX_DESC0_RX_PKT_EXS_COL 0x2     /* abort, >16 collisions */
0030 #define TX_DESC0_DMA_OWN    0x80000000  /* owned by controller */
0031 #define TX_DESC1_BUF_SIZE_MASK  0x7ff
0032 #define TX_DESC1_LTS        0x8000000   /* last TX packet */
0033 #define TX_DESC1_FTS        0x10000000  /* first TX packet */
0034 #define TX_DESC1_FIFO_COMPLETE  0x20000000
0035 #define TX_DESC1_INTR_COMPLETE  0x40000000
0036 #define TX_DESC1_END        0x80000000
0037 #define TX_DESC2_ADDRESS_PHYS   0
0038 #define TX_DESC2_ADDRESS_VIRT   4
0039
0040 #define RX_DESC0_FRAME_LEN  0
0041 #define RX_DESC0_FRAME_LEN_MASK 0x7FF
0042 #define RX_DESC0_MULTICAST  0x10000
0043 #define RX_DESC0_BROADCAST  0x20000
0044 #define RX_DESC0_ERR        0x40000
0045 #define RX_DESC0_CRC_ERR    0x80000
0046 #define RX_DESC0_FTL        0x100000
0047 #define RX_DESC0_RUNT       0x200000    /* packet less than 64 bytes */
0048 #define RX_DESC0_ODD_NB     0x400000    /* receive odd nibbles */
0049 #define RX_DESC0_LRS        0x10000000  /* last receive segment */
0050 #define RX_DESC0_FRS        0x20000000  /* first receive segment */
0051 #define RX_DESC0_DMA_OWN    0x80000000
0052 #define RX_DESC1_BUF_SIZE_MASK  0x7FF
0053 #define RX_DESC1_END        0x80000000
0054 #define RX_DESC2_ADDRESS_PHYS   0
0055 #define RX_DESC2_ADDRESS_VIRT   4
0056
0057 #define TX_DESC_NUM     64
0058 #define TX_DESC_NUM_MASK    (TX_DESC_NUM - 1)
0059 #define TX_NEXT(N)      (((N) + 1) & (TX_DESC_NUM_MASK))
0060 #define TX_BUF_SIZE     1600
0061 #define TX_BUF_SIZE_MAX     (TX_DESC1_BUF_SIZE_MASK + 1)
0062 #define TX_WAKE_THRESHOLD   16
0063
0064 #define RX_DESC_NUM     64
0065 #define RX_DESC_NUM_MASK    (RX_DESC_NUM - 1)
0066 #define RX_NEXT(N)      (((N) + 1) & (RX_DESC_NUM_MASK))
0067 #define RX_BUF_SIZE     1600
0068 #define RX_BUF_SIZE_MAX     (RX_DESC1_BUF_SIZE_MASK + 1)
0069
0070 #define REG_INTERRUPT_STATUS    0
0071 #define REG_INTERRUPT_MASK  4
0072 #define REG_MAC_MS_ADDRESS  8
0073 #define REG_MAC_LS_ADDRESS  12
0074 #define REG_MCAST_HASH_TABLE0   16
0075 #define REG_MCAST_HASH_TABLE1   20
0076 #define REG_TX_POLL_DEMAND  24
0077 #define REG_RX_POLL_DEMAND  28
0078 #define REG_TXR_BASE_ADDRESS    32
0079 #define REG_RXR_BASE_ADDRESS    36
0080 #define REG_INT_TIMER_CTRL  40
0081 #define REG_APOLL_TIMER_CTRL    44
0082 #define REG_DMA_BLEN_CTRL   48
0083 #define REG_RESERVED1       52
0084 #define REG_MAC_CTRL        136
0085 #define REG_MAC_STATUS      140
0086 #define REG_PHY_CTRL        144
0087 #define REG_PHY_WRITE_DATA  148
0088 #define REG_FLOW_CTRL       152
0089 #define REG_BACK_PRESSURE   156
0090 #define REG_RESERVED2       160
0091 #define REG_TEST_SEED       196
0092 #define REG_DMA_FIFO_STATE  200
0093 #define REG_TEST_MODE       204
0094 #define REG_RESERVED3       208
0095 #define REG_TX_COL_COUNTER  212
0096 #define REG_RPF_AEP_COUNTER 216
0097 #define REG_XM_PG_COUNTER   220
0098 #define REG_RUNT_TLC_COUNTER    224
0099 #define REG_CRC_FTL_COUNTER 228
0100 #define REG_RLC_RCC_COUNTER 232
0101 #define REG_BROC_COUNTER    236
0102 #define REG_MULCA_COUNTER   240
0103 #define REG_RP_COUNTER      244
0104 #define REG_XP_COUNTER      248
0105
0106 #define REG_PHY_CTRL_OFFSET 0x0
0107 #define REG_PHY_STATUS      0x1
0108 #define REG_PHY_ID1     0x2
0109 #define REG_PHY_ID2     0x3
0110 #define REG_PHY_ANA     0x4
0111 #define REG_PHY_ANLPAR      0x5
0112 #define REG_PHY_ANE     0x6
0113 #define REG_PHY_ECTRL1      0x10
0114 #define REG_PHY_QPDS        0x11
0115 #define REG_PHY_10BOP       0x12
0116 #define REG_PHY_ECTRL2      0x13
0117 #define REG_PHY_FTMAC100_WRITE  0x8000000
0118 #define REG_PHY_FTMAC100_READ   0x4000000
0119
0120 /* REG_INTERRUPT_STATUS */
0121 #define RPKT_FINISH     BIT(0)  /* DMA data received */
0122 #define NORXBUF         BIT(1)  /* receive buffer unavailable */
0123 #define XPKT_FINISH     BIT(2)  /* DMA moved data to TX FIFO */
0124 #define NOTXBUF         BIT(3)  /* transmit buffer unavailable */
0125 #define XPKT_OK_INT_STS     BIT(4)  /* transmit to ethernet success */
0126 #define XPKT_LOST_INT_STS   BIT(5)  /* transmit ethernet lost (collision) */
0127 #define RPKT_SAV        BIT(6)  /* FIFO receive success */
0128 #define RPKT_LOST_INT_STS   BIT(7)  /* FIFO full, receive failed */
0129 #define AHB_ERR         BIT(8)  /* AHB error */
0130 #define PHYSTS_CHG      BIT(9)  /* PHY link status change */
0131
0132 /* REG_INTERRUPT_MASK */
0133 #define RPKT_FINISH_M       BIT(0)
0134 #define NORXBUF_M       BIT(1)
0135 #define XPKT_FINISH_M       BIT(2)
0136 #define NOTXBUF_M       BIT(3)
0137 #define XPKT_OK_M       BIT(4)
0138 #define XPKT_LOST_M     BIT(5)
0139 #define RPKT_SAV_M      BIT(6)
0140 #define RPKT_LOST_M     BIT(7)
0141 #define AHB_ERR_M       BIT(8)
0142 #define PHYSTS_CHG_M        BIT(9)
0143
0144 /* REG_MAC_MS_ADDRESS */
0145 #define MAC_MADR_MASK       0xffff  /* 2 MSB MAC address */
0146
0147 /* REG_INT_TIMER_CTRL */
0148 #define TXINT_TIME_SEL      BIT(15) /* TX cycle time period */
0149 #define TXINT_THR_MASK      0x7000
0150 #define TXINT_CNT_MASK      0xf00
0151 #define RXINT_TIME_SEL      BIT(7)  /* RX cycle time period */
0152 #define RXINT_THR_MASK      0x70
0153 #define RXINT_CNT_MASK      0xF
0154
0155 /* REG_APOLL_TIMER_CTRL */
0156 #define TXPOLL_TIME_SEL     BIT(12) /* TX poll time period */
0157 #define TXPOLL_CNT_MASK     0xf00
0158 #define TXPOLL_CNT_SHIFT_BIT    8
0159 #define RXPOLL_TIME_SEL     BIT(4)  /* RX poll time period */
0160 #define RXPOLL_CNT_MASK     0xF
0161 #define RXPOLL_CNT_SHIFT_BIT    0
0162
0163 /* REG_DMA_BLEN_CTRL */
0164 #define RX_THR_EN       BIT(9)  /* RX FIFO threshold arbitration */
0165 #define RXFIFO_HTHR_MASK    0x1c0
0166 #define RXFIFO_LTHR_MASK    0x38
0167 #define INCR16_EN       BIT(2)  /* AHB bus INCR16 burst command */
0168 #define INCR8_EN        BIT(1)  /* AHB bus INCR8 burst command */
0169 #define INCR4_EN        BIT(0)  /* AHB bus INCR4 burst command */
0170
0171 /* REG_MAC_CTRL */
0172 #define RX_BROADPKT     BIT(17) /* receive broadcast packets */
0173 #define RX_MULTIPKT     BIT(16) /* receive all multicast packets */
0174 #define FULLDUP         BIT(15) /* full duplex */
0175 #define CRC_APD         BIT(14) /* append CRC to transmitted packet */
0176 #define RCV_ALL         BIT(12) /* ignore incoming packet destination */
0177 #define RX_FTL          BIT(11) /* accept packets larger than 1518 B */
0178 #define RX_RUNT         BIT(10) /* accept packets smaller than 64 B */
0179 #define HT_MULTI_EN     BIT(9)  /* accept on hash and mcast pass */
0180 #define RCV_EN          BIT(8)  /* receiver enable */
0181 #define ENRX_IN_HALFTX      BIT(6)  /* enable receive in half duplex mode */
0182 #define XMT_EN          BIT(5)  /* transmit enable */
0183 #define CRC_DIS         BIT(4)  /* disable CRC check when receiving */
0184 #define LOOP_EN         BIT(3)  /* internal loop-back */
0185 #define SW_RST          BIT(2)  /* software reset, last 64 AHB clocks */
0186 #define RDMA_EN         BIT(1)  /* enable receive DMA chan */
0187 #define XDMA_EN         BIT(0)  /* enable transmit DMA chan */
0188
0189 /* REG_MAC_STATUS */
0190 #define COL_EXCEED      BIT(11) /* more than 16 collisions */
0191 #define LATE_COL        BIT(10) /* transmit late collision detected */
0192 #define XPKT_LOST       BIT(9)  /* transmit to ethernet lost */
0193 #define XPKT_OK         BIT(8)  /* transmit to ethernet success */
0194 #define RUNT_MAC_STS        BIT(7)  /* receive runt detected */
0195 #define FTL_MAC_STS     BIT(6)  /* receive frame too long detected */
0196 #define CRC_ERR_MAC_STS     BIT(5)
0197 #define RPKT_LOST       BIT(4)  /* RX FIFO full, receive failed */
0198 #define RPKT_SAVE       BIT(3)  /* RX FIFO receive success */
0199 #define COL         BIT(2)  /* collision, incoming packet dropped */
0200 #define MCPU_BROADCAST      BIT(1)
0201 #define MCPU_MULTICAST      BIT(0)
0202
0203 /* REG_PHY_CTRL */
0204 #define MIIWR           BIT(27) /* init write sequence (auto cleared)*/
0205 #define MIIRD           BIT(26)
0206 #define REGAD_MASK      0x3e00000
0207 #define PHYAD_MASK      0x1f0000
0208 #define MIIRDATA_MASK       0xffff
0209
0210 /* REG_PHY_WRITE_DATA */
0211 #define MIIWDATA_MASK       0xffff
0212
0213 /* REG_FLOW_CTRL */
0214 #define PAUSE_TIME_MASK     0xffff0000
0215 #define FC_HIGH_MASK        0xf000
0216 #define FC_LOW_MASK     0xf00
0217 #define RX_PAUSE        BIT(4)  /* receive pause frame */
0218 #define TX_PAUSED       BIT(3)  /* transmit pause due to receive */
0219 #define FCTHR_EN        BIT(2)  /* enable threshold mode. */
0220 #define TX_PAUSE        BIT(1)  /* transmit pause frame */
0221 #define FC_EN           BIT(0)  /* flow control mode enable */
0222
0223 /* REG_BACK_PRESSURE */
0224 #define BACKP_LOW_MASK      0xf00
0225 #define BACKP_JAM_LEN_MASK  0xf0
0226 #define BACKP_MODE      BIT(1)  /* address mode */
0227 #define BACKP_ENABLE        BIT(0)
0228
0229 /* REG_TEST_SEED */
0230 #define TEST_SEED_MASK      0x3fff
0231
0232 /* REG_DMA_FIFO_STATE */
0233 #define TX_DMA_REQUEST      BIT(31)
0234 #define RX_DMA_REQUEST      BIT(30)
0235 #define TX_DMA_GRANT        BIT(29)
0236 #define RX_DMA_GRANT        BIT(28)
0237 #define TX_FIFO_EMPTY       BIT(27)
0238 #define RX_FIFO_EMPTY       BIT(26)
0239 #define TX_DMA2_SM_MASK     0x7000
0240 #define TX_DMA1_SM_MASK     0xf00
0241 #define RX_DMA2_SM_MASK     0x70
0242 #define RX_DMA1_SM_MASK     0xF
0243
0244 /* REG_TEST_MODE */
0245 #define SINGLE_PKT      BIT(26) /* single packet mode */
0246 #define PTIMER_TEST     BIT(25) /* automatic polling timer test mode */
0247 #define ITIMER_TEST     BIT(24) /* interrupt timer test mode */
0248 #define TEST_SEED_SELECT    BIT(22)
0249 #define SEED_SELECT     BIT(21)
0250 #define TEST_MODE       BIT(20)
0251 #define TEST_TIME_MASK      0xffc00
0252 #define TEST_EXCEL_MASK     0x3e0
0253
0254 /* REG_TX_COL_COUNTER */
0255 #define TX_MCOL_MASK        0xffff0000
0256 #define TX_MCOL_SHIFT_BIT   16
0257 #define TX_SCOL_MASK        0xffff
0258 #define TX_SCOL_SHIFT_BIT   0
0259
0260 /* REG_RPF_AEP_COUNTER */
0261 #define RPF_MASK        0xffff0000
0262 #define RPF_SHIFT_BIT       16
0263 #define AEP_MASK        0xffff
0264 #define AEP_SHIFT_BIT       0
0265
0266 /* REG_XM_PG_COUNTER */
0267 #define XM_MASK         0xffff0000
0268 #define XM_SHIFT_BIT        16
0269 #define PG_MASK         0xffff
0270 #define PG_SHIFT_BIT        0
0271
0272 /* REG_RUNT_TLC_COUNTER */
0273 #define RUNT_CNT_MASK       0xffff0000
0274 #define RUNT_CNT_SHIFT_BIT  16
0275 #define TLCC_MASK       0xffff
0276 #define TLCC_SHIFT_BIT      0
0277
0278 /* REG_CRC_FTL_COUNTER */
0279 #define CRCER_CNT_MASK      0xffff0000
0280 #define CRCER_CNT_SHIFT_BIT 16
0281 #define FTL_CNT_MASK        0xffff
0282 #define FTL_CNT_SHIFT_BIT   0
0283
0284 /* REG_RLC_RCC_COUNTER */
0285 #define RLC_MASK        0xffff0000
0286 #define RLC_SHIFT_BIT       16
0287 #define RCC_MASK        0xffff
0288 #define RCC_SHIFT_BIT       0
0289
0290 /* REG_PHY_STATUS */
0291 #define AN_COMPLETE     0x20
0292 #define LINK_STATUS     0x4
0293
0294 struct moxart_mac_priv_t {
0295     struct platform_device *pdev;
0296     void __iomem *base;
0297     unsigned int reg_maccr;
0298     unsigned int reg_imr;
0299     struct napi_struct napi;
0300     struct net_device *ndev;
0301
0302     dma_addr_t rx_base;
0303     dma_addr_t rx_mapping[RX_DESC_NUM];
0304     void *rx_desc_base;
0305     unsigned char *rx_buf_base;
0306     unsigned char *rx_buf[RX_DESC_NUM];
0307     unsigned int rx_head;
0308     unsigned int rx_buf_size;
0309
0310     dma_addr_t tx_base;
0311     dma_addr_t tx_mapping[TX_DESC_NUM];
0312     void *tx_desc_base;
0313     unsigned char *tx_buf_base;
0314     unsigned char *tx_buf[RX_DESC_NUM];
0315     unsigned int tx_head;
0316     unsigned int tx_buf_size;
0317
0318     spinlock_t txlock;
0319     unsigned int tx_len[TX_DESC_NUM];
0320     struct sk_buff *tx_skb[TX_DESC_NUM];
0321     unsigned int tx_tail;
0322 };
0323
0324 #if TX_BUF_SIZE >= TX_BUF_SIZE_MAX
0325 #error MOXA ART Ethernet device driver TX buffer is too large!
0326 #endif
0327 #if RX_BUF_SIZE >= RX_BUF_SIZE_MAX
0328 #error MOXA ART Ethernet device driver RX buffer is too large!
0329 #endif
0330
0331 #endif