ethernet/moxa/moxart_ether.c

0001 /* MOXA ART Ethernet (RTL8201CP) driver.
0002  *
0003  * Copyright (C) 2013 Jonas Jensen
0004  *
0005  * Jonas Jensen <jonas.jensen@gmail.com>
0006  *
0007  * Based on code from
0008  * Moxa Technology Co., Ltd. <www.moxa.com>
0009  *
0010  * This file is licensed under the terms of the GNU General Public
0011  * License version 2.  This program is licensed "as is" without any
0012  * warranty of any kind, whether express or implied.
0013  */
0014
0015 #include <linux/module.h>
0016 #include <linux/netdevice.h>
0017 #include <linux/etherdevice.h>
0018 #include <linux/skbuff.h>
0019 #include <linux/dma-mapping.h>
0020 #include <linux/ethtool.h>
0021 #include <linux/platform_device.h>
0022 #include <linux/interrupt.h>
0023 #include <linux/irq.h>
0024 #include <linux/of_address.h>
0025 #include <linux/of_irq.h>
0026 #include <linux/crc32.h>
0027 #include <linux/crc32c.h>
0028 #include <linux/circ_buf.h>
0029
0030 #include "moxart_ether.h"
0031
0032 static inline void moxart_desc_write(u32 data, u32 *desc)
0033 {
0034     *desc = cpu_to_le32(data);
0035 }
0036
0037 static inline u32 moxart_desc_read(u32 *desc)
0038 {
0039     return le32_to_cpu(*desc);
0040 }
0041
0042 static inline void moxart_emac_write(struct net_device *ndev,
0043                      unsigned int reg, unsigned long value)
0044 {
0045     struct moxart_mac_priv_t *priv = netdev_priv(ndev);
0046
0047     writel(value, priv->base + reg);
0048 }
0049
0050 static void moxart_update_mac_address(struct net_device *ndev)
0051 {
0052     moxart_emac_write(ndev, REG_MAC_MS_ADDRESS,
0053               ((ndev->dev_addr[0] << 8) | (ndev->dev_addr[1])));
0054     moxart_emac_write(ndev, REG_MAC_MS_ADDRESS + 4,
0055               ((ndev->dev_addr[2] << 24) |
0056                (ndev->dev_addr[3] << 16) |
0057                (ndev->dev_addr[4] << 8) |
0058                (ndev->dev_addr[5])));
0059 }
0060
0061 static int moxart_set_mac_address(struct net_device *ndev, void *addr)
0062 {
0063     struct sockaddr *address = addr;
0064
0065     eth_hw_addr_set(ndev, address->sa_data);
0066     moxart_update_mac_address(ndev);
0067
0068     return 0;
0069 }
0070
0071 static void moxart_mac_free_memory(struct net_device *ndev)
0072 {
0073     struct moxart_mac_priv_t *priv = netdev_priv(ndev);
0074
0075     if (priv->tx_desc_base)
0076         dma_free_coherent(&priv->pdev->dev,
0077                   TX_REG_DESC_SIZE * TX_DESC_NUM,
0078                   priv->tx_desc_base, priv->tx_base);
0079
0080     if (priv->rx_desc_base)
0081         dma_free_coherent(&priv->pdev->dev,
0082                   RX_REG_DESC_SIZE * RX_DESC_NUM,
0083                   priv->rx_desc_base, priv->rx_base);
0084
0085     kfree(priv->tx_buf_base);
0086     kfree(priv->rx_buf_base);
0087 }
0088
0089 static void moxart_mac_reset(struct net_device *ndev)
0090 {
0091     struct moxart_mac_priv_t *priv = netdev_priv(ndev);
0092
0093     writel(SW_RST, priv->base + REG_MAC_CTRL);
0094     while (readl(priv->base + REG_MAC_CTRL) & SW_RST)
0095         mdelay(10);
0096
0097     writel(0, priv->base + REG_INTERRUPT_MASK);
0098
0099     priv->reg_maccr = RX_BROADPKT | FULLDUP | CRC_APD | RX_FTL;
0100 }
0101
0102 static void moxart_mac_enable(struct net_device *ndev)
0103 {
0104     struct moxart_mac_priv_t *priv = netdev_priv(ndev);
0105
0106     writel(0x00001010, priv->base + REG_INT_TIMER_CTRL);
0107     writel(0x00000001, priv->base + REG_APOLL_TIMER_CTRL);
0108     writel(0x00000390, priv->base + REG_DMA_BLEN_CTRL);
0109
0110     priv->reg_imr |= (RPKT_FINISH_M | XPKT_FINISH_M);
0111     writel(priv->reg_imr, priv->base + REG_INTERRUPT_MASK);
0112
0113     priv->reg_maccr |= (RCV_EN | XMT_EN | RDMA_EN | XDMA_EN);
0114     writel(priv->reg_maccr, priv->base + REG_MAC_CTRL);
0115 }
0116
0117 static void moxart_mac_setup_desc_ring(struct net_device *ndev)
0118 {
0119     struct moxart_mac_priv_t *priv = netdev_priv(ndev);
0120     void *desc;
0121     int i;
0122
0123     for (i = 0; i < TX_DESC_NUM; i++) {
0124         desc = priv->tx_desc_base + i * TX_REG_DESC_SIZE;
0125         memset(desc, 0, TX_REG_DESC_SIZE);
0126
0127         priv->tx_buf[i] = priv->tx_buf_base + priv->tx_buf_size * i;
0128     }
0129     moxart_desc_write(TX_DESC1_END, desc + TX_REG_OFFSET_DESC1);
0130
0131     priv->tx_head = 0;
0132     priv->tx_tail = 0;
0133
0134     for (i = 0; i < RX_DESC_NUM; i++) {
0135         desc = priv->rx_desc_base + i * RX_REG_DESC_SIZE;
0136         memset(desc, 0, RX_REG_DESC_SIZE);
0137         moxart_desc_write(RX_DESC0_DMA_OWN, desc + RX_REG_OFFSET_DESC0);
0138         moxart_desc_write(RX_BUF_SIZE & RX_DESC1_BUF_SIZE_MASK,
0139                desc + RX_REG_OFFSET_DESC1);
0140
0141         priv->rx_buf[i] = priv->rx_buf_base + priv->rx_buf_size * i;
0142         priv->rx_mapping[i] = dma_map_single(&priv->pdev->dev,
0143                              priv->rx_buf[i],
0144                              priv->rx_buf_size,
0145                              DMA_FROM_DEVICE);
0146         if (dma_mapping_error(&priv->pdev->dev, priv->rx_mapping[i]))
0147             netdev_err(ndev, "DMA mapping error\n");
0148
0149         moxart_desc_write(priv->rx_mapping[i],
0150                desc + RX_REG_OFFSET_DESC2 + RX_DESC2_ADDRESS_PHYS);
0151         moxart_desc_write((uintptr_t)priv->rx_buf[i],
0152                desc + RX_REG_OFFSET_DESC2 + RX_DESC2_ADDRESS_VIRT);
0153     }
0154     moxart_desc_write(RX_DESC1_END, desc + RX_REG_OFFSET_DESC1);
0155
0156     priv->rx_head = 0;
0157
0158     /* reset the MAC controller TX/RX descriptor base address */
0159     writel(priv->tx_base, priv->base + REG_TXR_BASE_ADDRESS);
0160     writel(priv->rx_base, priv->base + REG_RXR_BASE_ADDRESS);
0161 }
0162
0163 static int moxart_mac_open(struct net_device *ndev)
0164 {
0165     struct moxart_mac_priv_t *priv = netdev_priv(ndev);
0166
0167     napi_enable(&priv->napi);
0168
0169     moxart_mac_reset(ndev);
0170     moxart_update_mac_address(ndev);
0171     moxart_mac_setup_desc_ring(ndev);
0172     moxart_mac_enable(ndev);
0173     netif_start_queue(ndev);
0174
0175     netdev_dbg(ndev, "%s: IMR=0x%x, MACCR=0x%x\n",
0176            __func__, readl(priv->base + REG_INTERRUPT_MASK),
0177            readl(priv->base + REG_MAC_CTRL));
0178
0179     return 0;
0180 }
0181
0182 static int moxart_mac_stop(struct net_device *ndev)
0183 {
0184     struct moxart_mac_priv_t *priv = netdev_priv(ndev);
0185     int i;
0186
0187     napi_disable(&priv->napi);
0188
0189     netif_stop_queue(ndev);
0190
0191     /* disable all interrupts */
0192     writel(0, priv->base + REG_INTERRUPT_MASK);
0193
0194     /* disable all functions */
0195     writel(0, priv->base + REG_MAC_CTRL);
0196
0197     /* unmap areas mapped in moxart_mac_setup_desc_ring() */
0198     for (i = 0; i < RX_DESC_NUM; i++)
0199         dma_unmap_single(&priv->pdev->dev, priv->rx_mapping[i],
0200                  priv->rx_buf_size, DMA_FROM_DEVICE);
0201
0202     return 0;
0203 }
0204
0205 static int moxart_rx_poll(struct napi_struct *napi, int budget)
0206 {
0207     struct moxart_mac_priv_t *priv = container_of(napi,
0208                               struct moxart_mac_priv_t,
0209                               napi);
0210     struct net_device *ndev = priv->ndev;
0211     struct sk_buff *skb;
0212     void *desc;
0213     unsigned int desc0, len;
0214     int rx_head = priv->rx_head;
0215     int rx = 0;
0216
0217     while (rx < budget) {
0218         desc = priv->rx_desc_base + (RX_REG_DESC_SIZE * rx_head);
0219         desc0 = moxart_desc_read(desc + RX_REG_OFFSET_DESC0);
0220         rmb(); /* ensure desc0 is up to date */
0221
0222         if (desc0 & RX_DESC0_DMA_OWN)
0223             break;
0224
0225         if (desc0 & (RX_DESC0_ERR | RX_DESC0_CRC_ERR | RX_DESC0_FTL |
0226                  RX_DESC0_RUNT | RX_DESC0_ODD_NB)) {
0227             net_dbg_ratelimited("packet error\n");
0228             ndev->stats.rx_dropped++;
0229             ndev->stats.rx_errors++;
0230             goto rx_next;
0231         }
0232
0233         len = desc0 & RX_DESC0_FRAME_LEN_MASK;
0234
0235         if (len > RX_BUF_SIZE)
0236             len = RX_BUF_SIZE;
0237
0238         dma_sync_single_for_cpu(&priv->pdev->dev,
0239                     priv->rx_mapping[rx_head],
0240                     priv->rx_buf_size, DMA_FROM_DEVICE);
0241         skb = netdev_alloc_skb_ip_align(ndev, len);
0242
0243         if (unlikely(!skb)) {
0244             net_dbg_ratelimited("netdev_alloc_skb_ip_align failed\n");
0245             ndev->stats.rx_dropped++;
0246             ndev->stats.rx_errors++;
0247             goto rx_next;
0248         }
0249
0250         memcpy(skb->data, priv->rx_buf[rx_head], len);
0251         skb_put(skb, len);
0252         skb->protocol = eth_type_trans(skb, ndev);
0253         napi_gro_receive(&priv->napi, skb);
0254         rx++;
0255
0256         ndev->stats.rx_packets++;
0257         ndev->stats.rx_bytes += len;
0258         if (desc0 & RX_DESC0_MULTICAST)
0259             ndev->stats.multicast++;
0260
0261 rx_next:
0262         wmb(); /* prevent setting ownership back too early */
0263         moxart_desc_write(RX_DESC0_DMA_OWN, desc + RX_REG_OFFSET_DESC0);
0264
0265         rx_head = RX_NEXT(rx_head);
0266         priv->rx_head = rx_head;
0267     }
0268
0269     if (rx < budget)
0270         napi_complete_done(napi, rx);
0271
0272     priv->reg_imr |= RPKT_FINISH_M;
0273     writel(priv->reg_imr, priv->base + REG_INTERRUPT_MASK);
0274
0275     return rx;
0276 }
0277
0278 static int moxart_tx_queue_space(struct net_device *ndev)
0279 {
0280     struct moxart_mac_priv_t *priv = netdev_priv(ndev);
0281
0282     return CIRC_SPACE(priv->tx_head, priv->tx_tail, TX_DESC_NUM);
0283 }
0284
0285 static void moxart_tx_finished(struct net_device *ndev)
0286 {
0287     struct moxart_mac_priv_t *priv = netdev_priv(ndev);
0288     unsigned int tx_head = priv->tx_head;
0289     unsigned int tx_tail = priv->tx_tail;
0290
0291     while (tx_tail != tx_head) {
0292         dma_unmap_single(&priv->pdev->dev, priv->tx_mapping[tx_tail],
0293                  priv->tx_len[tx_tail], DMA_TO_DEVICE);
0294
0295         ndev->stats.tx_packets++;
0296         ndev->stats.tx_bytes += priv->tx_skb[tx_tail]->len;
0297
0298         dev_consume_skb_irq(priv->tx_skb[tx_tail]);
0299         priv->tx_skb[tx_tail] = NULL;
0300
0301         tx_tail = TX_NEXT(tx_tail);
0302     }
0303     priv->tx_tail = tx_tail;
0304     if (netif_queue_stopped(ndev) &&
0305         moxart_tx_queue_space(ndev) >= TX_WAKE_THRESHOLD)
0306         netif_wake_queue(ndev);
0307 }
0308
0309 static irqreturn_t moxart_mac_interrupt(int irq, void *dev_id)
0310 {
0311     struct net_device *ndev = (struct net_device *)dev_id;
0312     struct moxart_mac_priv_t *priv = netdev_priv(ndev);
0313     unsigned int ists = readl(priv->base + REG_INTERRUPT_STATUS);
0314
0315     if (ists & XPKT_OK_INT_STS)
0316         moxart_tx_finished(ndev);
0317
0318     if (ists & RPKT_FINISH) {
0319         if (napi_schedule_prep(&priv->napi)) {
0320             priv->reg_imr &= ~RPKT_FINISH_M;
0321             writel(priv->reg_imr, priv->base + REG_INTERRUPT_MASK);
0322             __napi_schedule(&priv->napi);
0323         }
0324     }
0325
0326     return IRQ_HANDLED;
0327 }
0328
0329 static netdev_tx_t moxart_mac_start_xmit(struct sk_buff *skb,
0330                      struct net_device *ndev)
0331 {
0332     struct moxart_mac_priv_t *priv = netdev_priv(ndev);
0333     void *desc;
0334     unsigned int len;
0335     unsigned int tx_head;
0336     u32 txdes1;
0337     netdev_tx_t ret = NETDEV_TX_BUSY;
0338
0339     spin_lock_irq(&priv->txlock);
0340
0341     tx_head = priv->tx_head;
0342     desc = priv->tx_desc_base + (TX_REG_DESC_SIZE * tx_head);
0343
0344     if (moxart_tx_queue_space(ndev) == 1)
0345         netif_stop_queue(ndev);
0346
0347     if (moxart_desc_read(desc + TX_REG_OFFSET_DESC0) & TX_DESC0_DMA_OWN) {
0348         net_dbg_ratelimited("no TX space for packet\n");
0349         ndev->stats.tx_dropped++;
0350         goto out_unlock;
0351     }
0352     rmb(); /* ensure data is only read that had TX_DESC0_DMA_OWN cleared */
0353
0354     len = skb->len > TX_BUF_SIZE ? TX_BUF_SIZE : skb->len;
0355
0356     priv->tx_mapping[tx_head] = dma_map_single(&priv->pdev->dev, skb->data,
0357                            len, DMA_TO_DEVICE);
0358     if (dma_mapping_error(&priv->pdev->dev, priv->tx_mapping[tx_head])) {
0359         netdev_err(ndev, "DMA mapping error\n");
0360         goto out_unlock;
0361     }
0362
0363     priv->tx_len[tx_head] = len;
0364     priv->tx_skb[tx_head] = skb;
0365
0366     moxart_desc_write(priv->tx_mapping[tx_head],
0367            desc + TX_REG_OFFSET_DESC2 + TX_DESC2_ADDRESS_PHYS);
0368     moxart_desc_write((uintptr_t)skb->data,
0369            desc + TX_REG_OFFSET_DESC2 + TX_DESC2_ADDRESS_VIRT);
0370
0371     if (skb->len < ETH_ZLEN) {
0372         memset(&skb->data[skb->len],
0373                0, ETH_ZLEN - skb->len);
0374         len = ETH_ZLEN;
0375     }
0376
0377     dma_sync_single_for_device(&priv->pdev->dev, priv->tx_mapping[tx_head],
0378                    priv->tx_buf_size, DMA_TO_DEVICE);
0379
0380     txdes1 = TX_DESC1_LTS | TX_DESC1_FTS | (len & TX_DESC1_BUF_SIZE_MASK);
0381     if (tx_head == TX_DESC_NUM_MASK)
0382         txdes1 |= TX_DESC1_END;
0383     moxart_desc_write(txdes1, desc + TX_REG_OFFSET_DESC1);
0384     wmb(); /* flush descriptor before transferring ownership */
0385     moxart_desc_write(TX_DESC0_DMA_OWN, desc + TX_REG_OFFSET_DESC0);
0386
0387     /* start to send packet */
0388     writel(0xffffffff, priv->base + REG_TX_POLL_DEMAND);
0389
0390     priv->tx_head = TX_NEXT(tx_head);
0391
0392     netif_trans_update(ndev);
0393     ret = NETDEV_TX_OK;
0394 out_unlock:
0395     spin_unlock_irq(&priv->txlock);
0396
0397     return ret;
0398 }
0399
0400 static void moxart_mac_setmulticast(struct net_device *ndev)
0401 {
0402     struct moxart_mac_priv_t *priv = netdev_priv(ndev);
0403     struct netdev_hw_addr *ha;
0404     int crc_val;
0405
0406     netdev_for_each_mc_addr(ha, ndev) {
0407         crc_val = crc32_le(~0, ha->addr, ETH_ALEN);
0408         crc_val = (crc_val >> 26) & 0x3f;
0409         if (crc_val >= 32) {
0410             writel(readl(priv->base + REG_MCAST_HASH_TABLE1) |
0411                    (1UL << (crc_val - 32)),
0412                    priv->base + REG_MCAST_HASH_TABLE1);
0413         } else {
0414             writel(readl(priv->base + REG_MCAST_HASH_TABLE0) |
0415                    (1UL << crc_val),
0416                    priv->base + REG_MCAST_HASH_TABLE0);
0417         }
0418     }
0419 }
0420
0421 static void moxart_mac_set_rx_mode(struct net_device *ndev)
0422 {
0423     struct moxart_mac_priv_t *priv = netdev_priv(ndev);
0424
0425     spin_lock_irq(&priv->txlock);
0426
0427     (ndev->flags & IFF_PROMISC) ? (priv->reg_maccr |= RCV_ALL) :
0428                       (priv->reg_maccr &= ~RCV_ALL);
0429
0430     (ndev->flags & IFF_ALLMULTI) ? (priv->reg_maccr |= RX_MULTIPKT) :
0431                        (priv->reg_maccr &= ~RX_MULTIPKT);
0432
0433     if ((ndev->flags & IFF_MULTICAST) && netdev_mc_count(ndev)) {
0434         priv->reg_maccr |= HT_MULTI_EN;
0435         moxart_mac_setmulticast(ndev);
0436     } else {
0437         priv->reg_maccr &= ~HT_MULTI_EN;
0438     }
0439
0440     writel(priv->reg_maccr, priv->base + REG_MAC_CTRL);
0441
0442     spin_unlock_irq(&priv->txlock);
0443 }
0444
0445 static const struct net_device_ops moxart_netdev_ops = {
0446     .ndo_open       = moxart_mac_open,
0447     .ndo_stop       = moxart_mac_stop,
0448     .ndo_start_xmit     = moxart_mac_start_xmit,
0449     .ndo_set_rx_mode    = moxart_mac_set_rx_mode,
0450     .ndo_set_mac_address    = moxart_set_mac_address,
0451     .ndo_validate_addr  = eth_validate_addr,
0452 };
0453
0454 static int moxart_mac_probe(struct platform_device *pdev)
0455 {
0456     struct device *p_dev = &pdev->dev;
0457     struct device_node *node = p_dev->of_node;
0458     struct net_device *ndev;
0459     struct moxart_mac_priv_t *priv;
0460     struct resource *res;
0461     unsigned int irq;
0462     int ret;
0463
0464     ndev = alloc_etherdev(sizeof(struct moxart_mac_priv_t));
0465     if (!ndev)
0466         return -ENOMEM;
0467
0468     irq = irq_of_parse_and_map(node, 0);
0469     if (irq <= 0) {
0470         netdev_err(ndev, "irq_of_parse_and_map failed\n");
0471         ret = -EINVAL;
0472         goto irq_map_fail;
0473     }
0474
0475     priv = netdev_priv(ndev);
0476     priv->ndev = ndev;
0477     priv->pdev = pdev;
0478
0479     priv->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
0480     if (IS_ERR(priv->base)) {
0481         ret = PTR_ERR(priv->base);
0482         goto init_fail;
0483     }
0484     ndev->base_addr = res->start;
0485
0486     ret = platform_get_ethdev_address(p_dev, ndev);
0487     if (ret == -EPROBE_DEFER)
0488         goto init_fail;
0489     if (ret)
0490         eth_hw_addr_random(ndev);
0491     moxart_update_mac_address(ndev);
0492
0493     spin_lock_init(&priv->txlock);
0494
0495     priv->tx_buf_size = TX_BUF_SIZE;
0496     priv->rx_buf_size = RX_BUF_SIZE;
0497
0498     priv->tx_desc_base = dma_alloc_coherent(p_dev, TX_REG_DESC_SIZE *
0499                         TX_DESC_NUM, &priv->tx_base,
0500                         GFP_DMA | GFP_KERNEL);
0501     if (!priv->tx_desc_base) {
0502         ret = -ENOMEM;
0503         goto init_fail;
0504     }
0505
0506     priv->rx_desc_base = dma_alloc_coherent(p_dev, RX_REG_DESC_SIZE *
0507                         RX_DESC_NUM, &priv->rx_base,
0508                         GFP_DMA | GFP_KERNEL);
0509     if (!priv->rx_desc_base) {
0510         ret = -ENOMEM;
0511         goto init_fail;
0512     }
0513
0514     priv->tx_buf_base = kmalloc_array(priv->tx_buf_size, TX_DESC_NUM,
0515                       GFP_KERNEL);
0516     if (!priv->tx_buf_base) {
0517         ret = -ENOMEM;
0518         goto init_fail;
0519     }
0520
0521     priv->rx_buf_base = kmalloc_array(priv->rx_buf_size, RX_DESC_NUM,
0522                       GFP_KERNEL);
0523     if (!priv->rx_buf_base) {
0524         ret = -ENOMEM;
0525         goto init_fail;
0526     }
0527
0528     platform_set_drvdata(pdev, ndev);
0529
0530     ret = devm_request_irq(p_dev, irq, moxart_mac_interrupt, 0,
0531                    pdev->name, ndev);
0532     if (ret) {
0533         netdev_err(ndev, "devm_request_irq failed\n");
0534         goto init_fail;
0535     }
0536
0537     ndev->netdev_ops = &moxart_netdev_ops;
0538     netif_napi_add_weight(ndev, &priv->napi, moxart_rx_poll, RX_DESC_NUM);
0539     ndev->priv_flags |= IFF_UNICAST_FLT;
0540     ndev->irq = irq;
0541
0542     SET_NETDEV_DEV(ndev, &pdev->dev);
0543
0544     ret = register_netdev(ndev);
0545     if (ret)
0546         goto init_fail;
0547
0548     netdev_dbg(ndev, "%s: IRQ=%d address=%pM\n",
0549            __func__, ndev->irq, ndev->dev_addr);
0550
0551     return 0;
0552
0553 init_fail:
0554     netdev_err(ndev, "init failed\n");
0555     moxart_mac_free_memory(ndev);
0556 irq_map_fail:
0557     free_netdev(ndev);
0558     return ret;
0559 }
0560
0561 static int moxart_remove(struct platform_device *pdev)
0562 {
0563     struct net_device *ndev = platform_get_drvdata(pdev);
0564
0565     unregister_netdev(ndev);
0566     devm_free_irq(&pdev->dev, ndev->irq, ndev);
0567     moxart_mac_free_memory(ndev);
0568     free_netdev(ndev);
0569
0570     return 0;
0571 }
0572
0573 static const struct of_device_id moxart_mac_match[] = {
0574     { .compatible = "moxa,moxart-mac" },
0575     { }
0576 };
0577 MODULE_DEVICE_TABLE(of, moxart_mac_match);
0578
0579 static struct platform_driver moxart_mac_driver = {
0580     .probe  = moxart_mac_probe,
0581     .remove = moxart_remove,
0582     .driver = {
0583         .name       = "moxart-ethernet",
0584         .of_match_table = moxart_mac_match,
0585     },
0586 };
0587 module_platform_driver(moxart_mac_driver);
0588
0589 MODULE_DESCRIPTION("MOXART RTL8201CP Ethernet driver");
0590 MODULE_LICENSE("GPL v2");
0591 MODULE_AUTHOR("Jonas Jensen <jonas.jensen@gmail.com>");