microsoft/mana/hw_channel.h

0001 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
0002 /* Copyright (c) 2021, Microsoft Corporation. */
0003
0004 #ifndef _HW_CHANNEL_H
0005 #define _HW_CHANNEL_H
0006
0007 #define DEFAULT_LOG2_THROTTLING_FOR_ERROR_EQ  4
0008
0009 #define HW_CHANNEL_MAX_REQUEST_SIZE  0x1000
0010 #define HW_CHANNEL_MAX_RESPONSE_SIZE 0x1000
0011
0012 #define HW_CHANNEL_VF_BOOTSTRAP_QUEUE_DEPTH 1
0013
0014 #define HWC_INIT_DATA_CQID      1
0015 #define HWC_INIT_DATA_RQID      2
0016 #define HWC_INIT_DATA_SQID      3
0017 #define HWC_INIT_DATA_QUEUE_DEPTH   4
0018 #define HWC_INIT_DATA_MAX_REQUEST   5
0019 #define HWC_INIT_DATA_MAX_RESPONSE  6
0020 #define HWC_INIT_DATA_MAX_NUM_CQS   7
0021 #define HWC_INIT_DATA_PDID      8
0022 #define HWC_INIT_DATA_GPA_MKEY      9
0023 #define HWC_INIT_DATA_PF_DEST_RQ_ID 10
0024 #define HWC_INIT_DATA_PF_DEST_CQ_ID 11
0025
0026 /* Structures labeled with "HW DATA" are exchanged with the hardware. All of
0027  * them are naturally aligned and hence don't need __packed.
0028  */
0029
0030 union hwc_init_eq_id_db {
0031     u32 as_uint32;
0032
0033     struct {
0034         u32 eq_id   : 16;
0035         u32 doorbell    : 16;
0036     };
0037 }; /* HW DATA */
0038
0039 union hwc_init_type_data {
0040     u32 as_uint32;
0041
0042     struct {
0043         u32 value   : 24;
0044         u32 type    :  8;
0045     };
0046 }; /* HW DATA */
0047
0048 struct hwc_rx_oob {
0049     u32 type    : 6;
0050     u32 eom     : 1;
0051     u32 som     : 1;
0052     u32 vendor_err  : 8;
0053     u32 reserved1   : 16;
0054
0055     u32 src_virt_wq : 24;
0056     u32 src_vfid    : 8;
0057
0058     u32 reserved2;
0059
0060     union {
0061         u32 wqe_addr_low;
0062         u32 wqe_offset;
0063     };
0064
0065     u32 wqe_addr_high;
0066
0067     u32 client_data_unit    : 14;
0068     u32 reserved3       : 18;
0069
0070     u32 tx_oob_data_size;
0071
0072     u32 chunk_offset    : 21;
0073     u32 reserved4       : 11;
0074 }; /* HW DATA */
0075
0076 struct hwc_tx_oob {
0077     u32 reserved1;
0078
0079     u32 reserved2;
0080
0081     u32 vrq_id  : 24;
0082     u32 dest_vfid   : 8;
0083
0084     u32 vrcq_id : 24;
0085     u32 reserved3   : 8;
0086
0087     u32 vscq_id : 24;
0088     u32 loopback    : 1;
0089     u32 lso_override: 1;
0090     u32 dest_pf : 1;
0091     u32 reserved4   : 5;
0092
0093     u32 vsq_id  : 24;
0094     u32 reserved5   : 8;
0095 }; /* HW DATA */
0096
0097 struct hwc_work_request {
0098     void *buf_va;
0099     void *buf_sge_addr;
0100     u32 buf_len;
0101     u32 msg_size;
0102
0103     struct gdma_wqe_request wqe_req;
0104     struct hwc_tx_oob tx_oob;
0105
0106     struct gdma_sge sge;
0107 };
0108
0109 /* hwc_dma_buf represents the array of in-flight WQEs.
0110  * mem_info as know as the GDMA mapped memory is partitioned and used by
0111  * in-flight WQEs.
0112  * The number of WQEs is determined by the number of in-flight messages.
0113  */
0114 struct hwc_dma_buf {
0115     struct gdma_mem_info mem_info;
0116
0117     u32 gpa_mkey;
0118
0119     u32 num_reqs;
0120     struct hwc_work_request reqs[];
0121 };
0122
0123 typedef void hwc_rx_event_handler_t(void *ctx, u32 gdma_rxq_id,
0124                     const struct hwc_rx_oob *rx_oob);
0125
0126 typedef void hwc_tx_event_handler_t(void *ctx, u32 gdma_txq_id,
0127                     const struct hwc_rx_oob *rx_oob);
0128
0129 struct hwc_cq {
0130     struct hw_channel_context *hwc;
0131
0132     struct gdma_queue *gdma_cq;
0133     struct gdma_queue *gdma_eq;
0134     struct gdma_comp *comp_buf;
0135     u16 queue_depth;
0136
0137     hwc_rx_event_handler_t *rx_event_handler;
0138     void *rx_event_ctx;
0139
0140     hwc_tx_event_handler_t *tx_event_handler;
0141     void *tx_event_ctx;
0142 };
0143
0144 struct hwc_wq {
0145     struct hw_channel_context *hwc;
0146
0147     struct gdma_queue *gdma_wq;
0148     struct hwc_dma_buf *msg_buf;
0149     u16 queue_depth;
0150
0151     struct hwc_cq *hwc_cq;
0152 };
0153
0154 struct hwc_caller_ctx {
0155     struct completion comp_event;
0156     void *output_buf;
0157     u32 output_buflen;
0158
0159     u32 error; /* Linux error code */
0160     u32 status_code;
0161 };
0162
0163 struct hw_channel_context {
0164     struct gdma_dev *gdma_dev;
0165     struct device *dev;
0166
0167     u16 num_inflight_msg;
0168     u32 max_req_msg_size;
0169
0170     u16 hwc_init_q_depth_max;
0171     u32 hwc_init_max_req_msg_size;
0172     u32 hwc_init_max_resp_msg_size;
0173
0174     struct completion hwc_init_eqe_comp;
0175
0176     struct hwc_wq *rxq;
0177     struct hwc_wq *txq;
0178     struct hwc_cq *cq;
0179
0180     struct semaphore sema;
0181     struct gdma_resource inflight_msg_res;
0182
0183     u32 pf_dest_vrq_id;
0184     u32 pf_dest_vrcq_id;
0185
0186     struct hwc_caller_ctx *caller_ctx;
0187 };
0188
0189 int mana_hwc_create_channel(struct gdma_context *gc);
0190 void mana_hwc_destroy_channel(struct gdma_context *gc);
0191
0192 int mana_hwc_send_request(struct hw_channel_context *hwc, u32 req_len,
0193               const void *req, u32 resp_len, void *resp);
0194
0195 #endif /* _HW_CHANNEL_H */