microchip/sparx5/sparx5_port.h

0001 /* SPDX-License-Identifier: GPL-2.0+ */
0002 /* Microchip Sparx5 Switch driver
0003  *
0004  * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
0005  */
0006
0007 #ifndef __SPARX5_PORT_H__
0008 #define __SPARX5_PORT_H__
0009
0010 #include "sparx5_main.h"
0011
0012 static inline bool sparx5_port_is_2g5(int portno)
0013 {
0014     return portno >= 16 && portno <= 47;
0015 }
0016
0017 static inline bool sparx5_port_is_5g(int portno)
0018 {
0019     return portno <= 11 || portno == 64;
0020 }
0021
0022 static inline bool sparx5_port_is_10g(int portno)
0023 {
0024     return (portno >= 12 && portno <= 15) || (portno >= 48 && portno <= 55);
0025 }
0026
0027 static inline bool sparx5_port_is_25g(int portno)
0028 {
0029     return portno >= 56 && portno <= 63;
0030 }
0031
0032 static inline u32 sparx5_to_high_dev(int port)
0033 {
0034     if (sparx5_port_is_5g(port))
0035         return TARGET_DEV5G;
0036     if (sparx5_port_is_10g(port))
0037         return TARGET_DEV10G;
0038     return TARGET_DEV25G;
0039 }
0040
0041 static inline u32 sparx5_to_pcs_dev(int port)
0042 {
0043     if (sparx5_port_is_5g(port))
0044         return TARGET_PCS5G_BR;
0045     if (sparx5_port_is_10g(port))
0046         return TARGET_PCS10G_BR;
0047     return TARGET_PCS25G_BR;
0048 }
0049
0050 static inline int sparx5_port_dev_index(int port)
0051 {
0052     if (sparx5_port_is_2g5(port))
0053         return port;
0054     if (sparx5_port_is_5g(port))
0055         return (port <= 11 ? port : 12);
0056     if (sparx5_port_is_10g(port))
0057         return (port >= 12 && port <= 15) ?
0058             port - 12 : port - 44;
0059     return (port - 56);
0060 }
0061
0062 int sparx5_port_init(struct sparx5 *sparx5,
0063              struct sparx5_port *spx5_port,
0064              struct sparx5_port_config *conf);
0065
0066 int sparx5_port_config(struct sparx5 *sparx5,
0067                struct sparx5_port *spx5_port,
0068                struct sparx5_port_config *conf);
0069
0070 int sparx5_port_pcs_set(struct sparx5 *sparx5,
0071             struct sparx5_port *port,
0072             struct sparx5_port_config *conf);
0073
0074 int sparx5_serdes_set(struct sparx5 *sparx5,
0075               struct sparx5_port *spx5_port,
0076               struct sparx5_port_config *conf);
0077
0078 struct sparx5_port_status {
0079     bool link;
0080     bool link_down;
0081     int  speed;
0082     bool an_complete;
0083     int  duplex;
0084     int  pause;
0085 };
0086
0087 int sparx5_get_port_status(struct sparx5 *sparx5,
0088                struct sparx5_port *port,
0089                struct sparx5_port_status *status);
0090
0091 void sparx5_port_enable(struct sparx5_port *port, bool enable);
0092 int sparx5_port_fwd_urg(struct sparx5 *sparx5, u32 speed);
0093
0094 #endif  /* __SPARX5_PORT_H__ */