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0001 /* SPDX-License-Identifier: GPL-2.0+ */
0002 /* Microchip Sparx5 Switch driver
0003  *
0004  * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
0005  */
0006 
0007 #ifndef __SPARX5_MAIN_H__
0008 #define __SPARX5_MAIN_H__
0009 
0010 #include <linux/types.h>
0011 #include <linux/phy/phy.h>
0012 #include <linux/netdevice.h>
0013 #include <linux/phy.h>
0014 #include <linux/if_vlan.h>
0015 #include <linux/bitmap.h>
0016 #include <linux/phylink.h>
0017 #include <linux/net_tstamp.h>
0018 #include <linux/ptp_clock_kernel.h>
0019 #include <linux/hrtimer.h>
0020 
0021 #include "sparx5_main_regs.h"
0022 
0023 /* Target chip type */
0024 enum spx5_target_chiptype {
0025     SPX5_TARGET_CT_7546    = 0x7546,  /* SparX-5-64  Enterprise */
0026     SPX5_TARGET_CT_7549    = 0x7549,  /* SparX-5-90  Enterprise */
0027     SPX5_TARGET_CT_7552    = 0x7552,  /* SparX-5-128 Enterprise */
0028     SPX5_TARGET_CT_7556    = 0x7556,  /* SparX-5-160 Enterprise */
0029     SPX5_TARGET_CT_7558    = 0x7558,  /* SparX-5-200 Enterprise */
0030     SPX5_TARGET_CT_7546TSN = 0x47546, /* SparX-5-64i Industrial */
0031     SPX5_TARGET_CT_7549TSN = 0x47549, /* SparX-5-90i Industrial */
0032     SPX5_TARGET_CT_7552TSN = 0x47552, /* SparX-5-128i Industrial */
0033     SPX5_TARGET_CT_7556TSN = 0x47556, /* SparX-5-160i Industrial */
0034     SPX5_TARGET_CT_7558TSN = 0x47558, /* SparX-5-200i Industrial */
0035 };
0036 
0037 enum sparx5_port_max_tags {
0038     SPX5_PORT_MAX_TAGS_NONE,  /* No extra tags allowed */
0039     SPX5_PORT_MAX_TAGS_ONE,   /* Single tag allowed */
0040     SPX5_PORT_MAX_TAGS_TWO    /* Single and double tag allowed */
0041 };
0042 
0043 enum sparx5_vlan_port_type {
0044     SPX5_VLAN_PORT_TYPE_UNAWARE, /* VLAN unaware port */
0045     SPX5_VLAN_PORT_TYPE_C,       /* C-port */
0046     SPX5_VLAN_PORT_TYPE_S,       /* S-port */
0047     SPX5_VLAN_PORT_TYPE_S_CUSTOM /* S-port using custom type */
0048 };
0049 
0050 #define SPX5_PORTS             65
0051 #define SPX5_PORT_CPU          (SPX5_PORTS)  /* Next port is CPU port */
0052 #define SPX5_PORT_CPU_0        (SPX5_PORT_CPU + 0) /* CPU Port 65 */
0053 #define SPX5_PORT_CPU_1        (SPX5_PORT_CPU + 1) /* CPU Port 66 */
0054 #define SPX5_PORT_VD0          (SPX5_PORT_CPU + 2) /* VD0/Port 67 used for IPMC */
0055 #define SPX5_PORT_VD1          (SPX5_PORT_CPU + 3) /* VD1/Port 68 used for AFI/OAM */
0056 #define SPX5_PORT_VD2          (SPX5_PORT_CPU + 4) /* VD2/Port 69 used for IPinIP*/
0057 #define SPX5_PORTS_ALL         (SPX5_PORT_CPU + 5) /* Total number of ports */
0058 
0059 #define PGID_BASE              SPX5_PORTS /* Starts after port PGIDs */
0060 #define PGID_UC_FLOOD          (PGID_BASE + 0)
0061 #define PGID_MC_FLOOD          (PGID_BASE + 1)
0062 #define PGID_IPV4_MC_DATA      (PGID_BASE + 2)
0063 #define PGID_IPV4_MC_CTRL      (PGID_BASE + 3)
0064 #define PGID_IPV6_MC_DATA      (PGID_BASE + 4)
0065 #define PGID_IPV6_MC_CTRL      (PGID_BASE + 5)
0066 #define PGID_BCAST         (PGID_BASE + 6)
0067 #define PGID_CPU           (PGID_BASE + 7)
0068 #define PGID_MCAST_START       (PGID_BASE + 8)
0069 
0070 #define PGID_TABLE_SIZE        3290
0071 
0072 #define IFH_LEN                9 /* 36 bytes */
0073 #define NULL_VID               0
0074 #define SPX5_MACT_PULL_DELAY   (2 * HZ)
0075 #define SPX5_STATS_CHECK_DELAY (1 * HZ)
0076 #define SPX5_PRIOS             8     /* Number of priority queues */
0077 #define SPX5_BUFFER_CELL_SZ    184   /* Cell size  */
0078 #define SPX5_BUFFER_MEMORY     4194280 /* 22795 words * 184 bytes */
0079 
0080 #define XTR_QUEUE     0
0081 #define INJ_QUEUE     0
0082 
0083 #define FDMA_DCB_MAX            64
0084 #define FDMA_RX_DCB_MAX_DBS     15
0085 #define FDMA_TX_DCB_MAX_DBS     1
0086 
0087 #define SPARX5_PHC_COUNT        3
0088 #define SPARX5_PHC_PORT         0
0089 
0090 #define IFH_REW_OP_NOOP         0x0
0091 #define IFH_REW_OP_ONE_STEP_PTP     0x3
0092 #define IFH_REW_OP_TWO_STEP_PTP     0x4
0093 
0094 #define IFH_PDU_TYPE_NONE       0x0
0095 #define IFH_PDU_TYPE_PTP        0x5
0096 #define IFH_PDU_TYPE_IPV4_UDP_PTP   0x6
0097 #define IFH_PDU_TYPE_IPV6_UDP_PTP   0x7
0098 
0099 struct sparx5;
0100 
0101 struct sparx5_db_hw {
0102     u64 dataptr;
0103     u64 status;
0104 };
0105 
0106 struct sparx5_rx_dcb_hw {
0107     u64 nextptr;
0108     u64 info;
0109     struct sparx5_db_hw db[FDMA_RX_DCB_MAX_DBS];
0110 };
0111 
0112 struct sparx5_tx_dcb_hw {
0113     u64 nextptr;
0114     u64 info;
0115     struct sparx5_db_hw db[FDMA_TX_DCB_MAX_DBS];
0116 };
0117 
0118 /* Frame DMA receive state:
0119  * For each DB, there is a SKB, and the skb data pointer is mapped in
0120  * the DB. Once a frame is received the skb is given to the upper layers
0121  * and a new skb is added to the dcb.
0122  * When the db_index reached FDMA_RX_DCB_MAX_DBS the DB is reused.
0123  */
0124 struct sparx5_rx {
0125     struct sparx5_rx_dcb_hw *dcb_entries;
0126     struct sparx5_rx_dcb_hw *last_entry;
0127     struct sk_buff *skb[FDMA_DCB_MAX][FDMA_RX_DCB_MAX_DBS];
0128     int db_index;
0129     int dcb_index;
0130     dma_addr_t dma;
0131     struct napi_struct napi;
0132     u32 channel_id;
0133     struct net_device *ndev;
0134     u64 packets;
0135 };
0136 
0137 /* Frame DMA transmit state:
0138  * DCBs are chained using the DCBs nextptr field.
0139  */
0140 struct sparx5_tx {
0141     struct sparx5_tx_dcb_hw *curr_entry;
0142     struct sparx5_tx_dcb_hw *first_entry;
0143     struct list_head db_list;
0144     dma_addr_t dma;
0145     u32 channel_id;
0146     u64 packets;
0147     u64 dropped;
0148 };
0149 
0150 struct sparx5_port_config {
0151     phy_interface_t portmode;
0152     u32 bandwidth;
0153     int speed;
0154     int duplex;
0155     enum phy_media media;
0156     bool inband;
0157     bool power_down;
0158     bool autoneg;
0159     bool serdes_reset;
0160     u32 pause;
0161     u32 pause_adv;
0162     phy_interface_t phy_mode;
0163     u32 sd_sgpio;
0164 };
0165 
0166 struct sparx5_port {
0167     struct net_device *ndev;
0168     struct sparx5 *sparx5;
0169     struct device_node *of_node;
0170     struct phy *serdes;
0171     struct sparx5_port_config conf;
0172     struct phylink_config phylink_config;
0173     struct phylink *phylink;
0174     struct phylink_pcs phylink_pcs;
0175     u16 portno;
0176     /* Ingress default VLAN (pvid) */
0177     u16 pvid;
0178     /* Egress default VLAN (vid) */
0179     u16 vid;
0180     bool signd_internal;
0181     bool signd_active_high;
0182     bool signd_enable;
0183     bool flow_control;
0184     enum sparx5_port_max_tags max_vlan_tags;
0185     enum sparx5_vlan_port_type vlan_type;
0186     u32 custom_etype;
0187     bool vlan_aware;
0188     struct hrtimer inj_timer;
0189     /* ptp */
0190     u8 ptp_cmd;
0191     u16 ts_id;
0192     struct sk_buff_head tx_skbs;
0193 };
0194 
0195 enum sparx5_core_clockfreq {
0196     SPX5_CORE_CLOCK_DEFAULT,  /* Defaults to the highest supported frequency */
0197     SPX5_CORE_CLOCK_250MHZ,   /* 250MHZ core clock frequency */
0198     SPX5_CORE_CLOCK_500MHZ,   /* 500MHZ core clock frequency */
0199     SPX5_CORE_CLOCK_625MHZ,   /* 625MHZ core clock frequency */
0200 };
0201 
0202 struct sparx5_phc {
0203     struct ptp_clock *clock;
0204     struct ptp_clock_info info;
0205     struct hwtstamp_config hwtstamp_config;
0206     struct sparx5 *sparx5;
0207     u8 index;
0208 };
0209 
0210 struct sparx5_skb_cb {
0211     u8 rew_op;
0212     u8 pdu_type;
0213     u8 pdu_w16_offset;
0214     u16 ts_id;
0215     unsigned long jiffies;
0216 };
0217 
0218 #define SPARX5_PTP_TIMEOUT      msecs_to_jiffies(10)
0219 #define SPARX5_SKB_CB(skb) \
0220     ((struct sparx5_skb_cb *)((skb)->cb))
0221 
0222 struct sparx5 {
0223     struct platform_device *pdev;
0224     struct device *dev;
0225     u32 chip_id;
0226     enum spx5_target_chiptype target_ct;
0227     void __iomem *regs[NUM_TARGETS];
0228     int port_count;
0229     struct mutex lock; /* MAC reg lock */
0230     /* port structures are in net device */
0231     struct sparx5_port *ports[SPX5_PORTS];
0232     enum sparx5_core_clockfreq coreclock;
0233     /* Statistics */
0234     u32 num_stats;
0235     u32 num_ethtool_stats;
0236     const char * const *stats_layout;
0237     u64 *stats;
0238     /* Workqueue for reading stats */
0239     struct mutex queue_stats_lock;
0240     struct delayed_work stats_work;
0241     struct workqueue_struct *stats_queue;
0242     /* Notifiers */
0243     struct notifier_block netdevice_nb;
0244     struct notifier_block switchdev_nb;
0245     struct notifier_block switchdev_blocking_nb;
0246     /* Switch state */
0247     u8 base_mac[ETH_ALEN];
0248     /* Associated bridge device (when bridged) */
0249     struct net_device *hw_bridge_dev;
0250     /* Bridged interfaces */
0251     DECLARE_BITMAP(bridge_mask, SPX5_PORTS);
0252     DECLARE_BITMAP(bridge_fwd_mask, SPX5_PORTS);
0253     DECLARE_BITMAP(bridge_lrn_mask, SPX5_PORTS);
0254     DECLARE_BITMAP(vlan_mask[VLAN_N_VID], SPX5_PORTS);
0255     /* SW MAC table */
0256     struct list_head mact_entries;
0257     /* mac table list (mact_entries) mutex */
0258     struct mutex mact_lock;
0259     struct delayed_work mact_work;
0260     struct workqueue_struct *mact_queue;
0261     /* Board specifics */
0262     bool sd_sgpio_remapping;
0263     /* Register based inj/xtr */
0264     int xtr_irq;
0265     /* Frame DMA */
0266     int fdma_irq;
0267     struct sparx5_rx rx;
0268     struct sparx5_tx tx;
0269     /* PTP */
0270     bool ptp;
0271     struct sparx5_phc phc[SPARX5_PHC_COUNT];
0272     spinlock_t ptp_clock_lock; /* lock for phc */
0273     spinlock_t ptp_ts_id_lock; /* lock for ts_id */
0274     struct mutex ptp_lock; /* lock for ptp interface state */
0275     u16 ptp_skbs;
0276     int ptp_irq;
0277     /* PGID allocation map */
0278     u8 pgid_map[PGID_TABLE_SIZE];
0279 };
0280 
0281 /* sparx5_switchdev.c */
0282 int sparx5_register_notifier_blocks(struct sparx5 *sparx5);
0283 void sparx5_unregister_notifier_blocks(struct sparx5 *sparx5);
0284 
0285 /* sparx5_packet.c */
0286 struct frame_info {
0287     int src_port;
0288     u32 timestamp;
0289 };
0290 
0291 void sparx5_xtr_flush(struct sparx5 *sparx5, u8 grp);
0292 void sparx5_ifh_parse(u32 *ifh, struct frame_info *info);
0293 irqreturn_t sparx5_xtr_handler(int irq, void *_priv);
0294 int sparx5_port_xmit_impl(struct sk_buff *skb, struct net_device *dev);
0295 int sparx5_manual_injection_mode(struct sparx5 *sparx5);
0296 void sparx5_port_inj_timer_setup(struct sparx5_port *port);
0297 
0298 /* sparx5_fdma.c */
0299 int sparx5_fdma_start(struct sparx5 *sparx5);
0300 int sparx5_fdma_stop(struct sparx5 *sparx5);
0301 int sparx5_fdma_xmit(struct sparx5 *sparx5, u32 *ifh, struct sk_buff *skb);
0302 irqreturn_t sparx5_fdma_handler(int irq, void *args);
0303 
0304 /* sparx5_mactable.c */
0305 void sparx5_mact_pull_work(struct work_struct *work);
0306 int sparx5_mact_learn(struct sparx5 *sparx5, int port,
0307               const unsigned char mac[ETH_ALEN], u16 vid);
0308 bool sparx5_mact_getnext(struct sparx5 *sparx5,
0309              unsigned char mac[ETH_ALEN], u16 *vid, u32 *pcfg2);
0310 bool sparx5_mact_find(struct sparx5 *sparx5,
0311               const unsigned char mac[ETH_ALEN], u16 vid, u32 *pcfg2);
0312 int sparx5_mact_forget(struct sparx5 *sparx5,
0313                const unsigned char mac[ETH_ALEN], u16 vid);
0314 int sparx5_add_mact_entry(struct sparx5 *sparx5,
0315               struct net_device *dev,
0316               u16 portno,
0317               const unsigned char *addr, u16 vid);
0318 int sparx5_del_mact_entry(struct sparx5 *sparx5,
0319               const unsigned char *addr,
0320               u16 vid);
0321 int sparx5_mc_sync(struct net_device *dev, const unsigned char *addr);
0322 int sparx5_mc_unsync(struct net_device *dev, const unsigned char *addr);
0323 void sparx5_set_ageing(struct sparx5 *sparx5, int msecs);
0324 void sparx5_mact_init(struct sparx5 *sparx5);
0325 
0326 /* sparx5_vlan.c */
0327 void sparx5_pgid_update_mask(struct sparx5_port *port, int pgid, bool enable);
0328 void sparx5_pgid_read_mask(struct sparx5 *sparx5, int pgid, u32 portmask[3]);
0329 void sparx5_update_fwd(struct sparx5 *sparx5);
0330 void sparx5_vlan_init(struct sparx5 *sparx5);
0331 void sparx5_vlan_port_setup(struct sparx5 *sparx5, int portno);
0332 int sparx5_vlan_vid_add(struct sparx5_port *port, u16 vid, bool pvid,
0333             bool untagged);
0334 int sparx5_vlan_vid_del(struct sparx5_port *port, u16 vid);
0335 void sparx5_vlan_port_apply(struct sparx5 *sparx5, struct sparx5_port *port);
0336 
0337 /* sparx5_calendar.c */
0338 int sparx5_config_auto_calendar(struct sparx5 *sparx5);
0339 int sparx5_config_dsm_calendar(struct sparx5 *sparx5);
0340 
0341 /* sparx5_ethtool.c */
0342 void sparx5_get_stats64(struct net_device *ndev, struct rtnl_link_stats64 *stats);
0343 int sparx_stats_init(struct sparx5 *sparx5);
0344 
0345 /* sparx5_netdev.c */
0346 void sparx5_set_port_ifh_timestamp(void *ifh_hdr, u64 timestamp);
0347 void sparx5_set_port_ifh_rew_op(void *ifh_hdr, u32 rew_op);
0348 void sparx5_set_port_ifh_pdu_type(void *ifh_hdr, u32 pdu_type);
0349 void sparx5_set_port_ifh_pdu_w16_offset(void *ifh_hdr, u32 pdu_w16_offset);
0350 void sparx5_set_port_ifh(void *ifh_hdr, u16 portno);
0351 bool sparx5_netdevice_check(const struct net_device *dev);
0352 struct net_device *sparx5_create_netdev(struct sparx5 *sparx5, u32 portno);
0353 int sparx5_register_netdevs(struct sparx5 *sparx5);
0354 void sparx5_destroy_netdevs(struct sparx5 *sparx5);
0355 void sparx5_unregister_netdevs(struct sparx5 *sparx5);
0356 
0357 /* sparx5_ptp.c */
0358 int sparx5_ptp_init(struct sparx5 *sparx5);
0359 void sparx5_ptp_deinit(struct sparx5 *sparx5);
0360 int sparx5_ptp_hwtstamp_set(struct sparx5_port *port, struct ifreq *ifr);
0361 int sparx5_ptp_hwtstamp_get(struct sparx5_port *port, struct ifreq *ifr);
0362 void sparx5_ptp_rxtstamp(struct sparx5 *sparx5, struct sk_buff *skb,
0363              u64 timestamp);
0364 int sparx5_ptp_txtstamp_request(struct sparx5_port *port,
0365                 struct sk_buff *skb);
0366 void sparx5_ptp_txtstamp_release(struct sparx5_port *port,
0367                  struct sk_buff *skb);
0368 irqreturn_t sparx5_ptp_irq_handler(int irq, void *args);
0369 
0370 /* sparx5_pgid.c */
0371 enum sparx5_pgid_type {
0372     SPX5_PGID_FREE,
0373     SPX5_PGID_RESERVED,
0374     SPX5_PGID_MULTICAST,
0375 };
0376 
0377 void sparx5_pgid_init(struct sparx5 *spx5);
0378 int sparx5_pgid_alloc_glag(struct sparx5 *spx5, u16 *idx);
0379 int sparx5_pgid_alloc_mcast(struct sparx5 *spx5, u16 *idx);
0380 int sparx5_pgid_free(struct sparx5 *spx5, u16 idx);
0381 
0382 /* Clock period in picoseconds */
0383 static inline u32 sparx5_clk_period(enum sparx5_core_clockfreq cclock)
0384 {
0385     switch (cclock) {
0386     case SPX5_CORE_CLOCK_250MHZ:
0387         return 4000;
0388     case SPX5_CORE_CLOCK_500MHZ:
0389         return 2000;
0390     case SPX5_CORE_CLOCK_625MHZ:
0391     default:
0392         return 1600;
0393     }
0394 }
0395 
0396 static inline bool sparx5_is_baser(phy_interface_t interface)
0397 {
0398     return interface == PHY_INTERFACE_MODE_5GBASER ||
0399            interface == PHY_INTERFACE_MODE_10GBASER ||
0400            interface == PHY_INTERFACE_MODE_25GBASER;
0401 }
0402 
0403 extern const struct phylink_mac_ops sparx5_phylink_mac_ops;
0404 extern const struct phylink_pcs_ops sparx5_phylink_pcs_ops;
0405 extern const struct ethtool_ops sparx5_ethtool_ops;
0406 
0407 /* Calculate raw offset */
0408 static inline __pure int spx5_offset(int id, int tinst, int tcnt,
0409                      int gbase, int ginst,
0410                      int gcnt, int gwidth,
0411                      int raddr, int rinst,
0412                      int rcnt, int rwidth)
0413 {
0414     WARN_ON((tinst) >= tcnt);
0415     WARN_ON((ginst) >= gcnt);
0416     WARN_ON((rinst) >= rcnt);
0417     return gbase + ((ginst) * gwidth) +
0418         raddr + ((rinst) * rwidth);
0419 }
0420 
0421 /* Read, Write and modify registers content.
0422  * The register definition macros start at the id
0423  */
0424 static inline void __iomem *spx5_addr(void __iomem *base[],
0425                       int id, int tinst, int tcnt,
0426                       int gbase, int ginst,
0427                       int gcnt, int gwidth,
0428                       int raddr, int rinst,
0429                       int rcnt, int rwidth)
0430 {
0431     WARN_ON((tinst) >= tcnt);
0432     WARN_ON((ginst) >= gcnt);
0433     WARN_ON((rinst) >= rcnt);
0434     return base[id + (tinst)] +
0435         gbase + ((ginst) * gwidth) +
0436         raddr + ((rinst) * rwidth);
0437 }
0438 
0439 static inline void __iomem *spx5_inst_addr(void __iomem *base,
0440                        int gbase, int ginst,
0441                        int gcnt, int gwidth,
0442                        int raddr, int rinst,
0443                        int rcnt, int rwidth)
0444 {
0445     WARN_ON((ginst) >= gcnt);
0446     WARN_ON((rinst) >= rcnt);
0447     return base +
0448         gbase + ((ginst) * gwidth) +
0449         raddr + ((rinst) * rwidth);
0450 }
0451 
0452 static inline u32 spx5_rd(struct sparx5 *sparx5, int id, int tinst, int tcnt,
0453               int gbase, int ginst, int gcnt, int gwidth,
0454               int raddr, int rinst, int rcnt, int rwidth)
0455 {
0456     return readl(spx5_addr(sparx5->regs, id, tinst, tcnt, gbase, ginst,
0457                    gcnt, gwidth, raddr, rinst, rcnt, rwidth));
0458 }
0459 
0460 static inline u32 spx5_inst_rd(void __iomem *iomem, int id, int tinst, int tcnt,
0461                    int gbase, int ginst, int gcnt, int gwidth,
0462                    int raddr, int rinst, int rcnt, int rwidth)
0463 {
0464     return readl(spx5_inst_addr(iomem, gbase, ginst,
0465                      gcnt, gwidth, raddr, rinst, rcnt, rwidth));
0466 }
0467 
0468 static inline void spx5_wr(u32 val, struct sparx5 *sparx5,
0469                int id, int tinst, int tcnt,
0470                int gbase, int ginst, int gcnt, int gwidth,
0471                int raddr, int rinst, int rcnt, int rwidth)
0472 {
0473     writel(val, spx5_addr(sparx5->regs, id, tinst, tcnt,
0474                   gbase, ginst, gcnt, gwidth,
0475                   raddr, rinst, rcnt, rwidth));
0476 }
0477 
0478 static inline void spx5_inst_wr(u32 val, void __iomem *iomem,
0479                 int id, int tinst, int tcnt,
0480                 int gbase, int ginst, int gcnt, int gwidth,
0481                 int raddr, int rinst, int rcnt, int rwidth)
0482 {
0483     writel(val, spx5_inst_addr(iomem,
0484                    gbase, ginst, gcnt, gwidth,
0485                    raddr, rinst, rcnt, rwidth));
0486 }
0487 
0488 static inline void spx5_rmw(u32 val, u32 mask, struct sparx5 *sparx5,
0489                 int id, int tinst, int tcnt,
0490                 int gbase, int ginst, int gcnt, int gwidth,
0491                 int raddr, int rinst, int rcnt, int rwidth)
0492 {
0493     u32 nval;
0494 
0495     nval = readl(spx5_addr(sparx5->regs, id, tinst, tcnt, gbase, ginst,
0496                    gcnt, gwidth, raddr, rinst, rcnt, rwidth));
0497     nval = (nval & ~mask) | (val & mask);
0498     writel(nval, spx5_addr(sparx5->regs, id, tinst, tcnt, gbase, ginst,
0499                    gcnt, gwidth, raddr, rinst, rcnt, rwidth));
0500 }
0501 
0502 static inline void spx5_inst_rmw(u32 val, u32 mask, void __iomem *iomem,
0503                  int id, int tinst, int tcnt,
0504                  int gbase, int ginst, int gcnt, int gwidth,
0505                  int raddr, int rinst, int rcnt, int rwidth)
0506 {
0507     u32 nval;
0508 
0509     nval = readl(spx5_inst_addr(iomem, gbase, ginst, gcnt, gwidth, raddr,
0510                     rinst, rcnt, rwidth));
0511     nval = (nval & ~mask) | (val & mask);
0512     writel(nval, spx5_inst_addr(iomem, gbase, ginst, gcnt, gwidth, raddr,
0513                     rinst, rcnt, rwidth));
0514 }
0515 
0516 static inline void __iomem *spx5_inst_get(struct sparx5 *sparx5, int id, int tinst)
0517 {
0518     return sparx5->regs[id + tinst];
0519 }
0520 
0521 static inline void __iomem *spx5_reg_get(struct sparx5 *sparx5,
0522                      int id, int tinst, int tcnt,
0523                      int gbase, int ginst, int gcnt, int gwidth,
0524                      int raddr, int rinst, int rcnt, int rwidth)
0525 {
0526     return spx5_addr(sparx5->regs, id, tinst, tcnt,
0527              gbase, ginst, gcnt, gwidth,
0528              raddr, rinst, rcnt, rwidth);
0529 }
0530 
0531 #endif  /* __SPARX5_MAIN_H__ */
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