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0007 #ifndef _LAN966X_REGS_H_
0008 #define _LAN966X_REGS_H_
0009
0010 #include <linux/bitfield.h>
0011 #include <linux/types.h>
0012 #include <linux/bug.h>
0013
0014 enum lan966x_target {
0015 TARGET_AFI = 2,
0016 TARGET_ANA = 3,
0017 TARGET_CHIP_TOP = 5,
0018 TARGET_CPU = 6,
0019 TARGET_DEV = 13,
0020 TARGET_FDMA = 21,
0021 TARGET_GCB = 27,
0022 TARGET_ORG = 36,
0023 TARGET_PTP = 41,
0024 TARGET_QS = 42,
0025 TARGET_QSYS = 46,
0026 TARGET_REW = 47,
0027 TARGET_SYS = 52,
0028 NUM_TARGETS = 66
0029 };
0030
0031 #define __REG(...) __VA_ARGS__
0032
0033
0034 #define AFI_PORT_FRM_OUT(g) __REG(TARGET_AFI, 0, 1, 98816, g, 10, 8, 0, 0, 1, 4)
0035
0036 #define AFI_PORT_FRM_OUT_FRM_OUT_CNT GENMASK(26, 16)
0037 #define AFI_PORT_FRM_OUT_FRM_OUT_CNT_SET(x)\
0038 FIELD_PREP(AFI_PORT_FRM_OUT_FRM_OUT_CNT, x)
0039 #define AFI_PORT_FRM_OUT_FRM_OUT_CNT_GET(x)\
0040 FIELD_GET(AFI_PORT_FRM_OUT_FRM_OUT_CNT, x)
0041
0042
0043 #define AFI_PORT_CFG(g) __REG(TARGET_AFI, 0, 1, 98816, g, 10, 8, 4, 0, 1, 4)
0044
0045 #define AFI_PORT_CFG_FC_SKIP_TTI_INJ BIT(16)
0046 #define AFI_PORT_CFG_FC_SKIP_TTI_INJ_SET(x)\
0047 FIELD_PREP(AFI_PORT_CFG_FC_SKIP_TTI_INJ, x)
0048 #define AFI_PORT_CFG_FC_SKIP_TTI_INJ_GET(x)\
0049 FIELD_GET(AFI_PORT_CFG_FC_SKIP_TTI_INJ, x)
0050
0051 #define AFI_PORT_CFG_FRM_OUT_MAX GENMASK(9, 0)
0052 #define AFI_PORT_CFG_FRM_OUT_MAX_SET(x)\
0053 FIELD_PREP(AFI_PORT_CFG_FRM_OUT_MAX, x)
0054 #define AFI_PORT_CFG_FRM_OUT_MAX_GET(x)\
0055 FIELD_GET(AFI_PORT_CFG_FRM_OUT_MAX, x)
0056
0057
0058 #define ANA_ADVLEARN __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 0, 0, 1, 4)
0059
0060 #define ANA_ADVLEARN_VLAN_CHK BIT(0)
0061 #define ANA_ADVLEARN_VLAN_CHK_SET(x)\
0062 FIELD_PREP(ANA_ADVLEARN_VLAN_CHK, x)
0063 #define ANA_ADVLEARN_VLAN_CHK_GET(x)\
0064 FIELD_GET(ANA_ADVLEARN_VLAN_CHK, x)
0065
0066
0067 #define ANA_VLANMASK __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 8, 0, 1, 4)
0068
0069
0070 #define ANA_ANAINTR __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 16, 0, 1, 4)
0071
0072 #define ANA_ANAINTR_INTR BIT(1)
0073 #define ANA_ANAINTR_INTR_SET(x)\
0074 FIELD_PREP(ANA_ANAINTR_INTR, x)
0075 #define ANA_ANAINTR_INTR_GET(x)\
0076 FIELD_GET(ANA_ANAINTR_INTR, x)
0077
0078 #define ANA_ANAINTR_INTR_ENA BIT(0)
0079 #define ANA_ANAINTR_INTR_ENA_SET(x)\
0080 FIELD_PREP(ANA_ANAINTR_INTR_ENA, x)
0081 #define ANA_ANAINTR_INTR_ENA_GET(x)\
0082 FIELD_GET(ANA_ANAINTR_INTR_ENA, x)
0083
0084
0085 #define ANA_AUTOAGE __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 44, 0, 1, 4)
0086
0087 #define ANA_AUTOAGE_AGE_PERIOD GENMASK(20, 1)
0088 #define ANA_AUTOAGE_AGE_PERIOD_SET(x)\
0089 FIELD_PREP(ANA_AUTOAGE_AGE_PERIOD, x)
0090 #define ANA_AUTOAGE_AGE_PERIOD_GET(x)\
0091 FIELD_GET(ANA_AUTOAGE_AGE_PERIOD, x)
0092
0093
0094 #define ANA_FLOODING(r) __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 68, r, 8, 4)
0095
0096 #define ANA_FLOODING_FLD_UNICAST GENMASK(17, 12)
0097 #define ANA_FLOODING_FLD_UNICAST_SET(x)\
0098 FIELD_PREP(ANA_FLOODING_FLD_UNICAST, x)
0099 #define ANA_FLOODING_FLD_UNICAST_GET(x)\
0100 FIELD_GET(ANA_FLOODING_FLD_UNICAST, x)
0101
0102 #define ANA_FLOODING_FLD_BROADCAST GENMASK(11, 6)
0103 #define ANA_FLOODING_FLD_BROADCAST_SET(x)\
0104 FIELD_PREP(ANA_FLOODING_FLD_BROADCAST, x)
0105 #define ANA_FLOODING_FLD_BROADCAST_GET(x)\
0106 FIELD_GET(ANA_FLOODING_FLD_BROADCAST, x)
0107
0108 #define ANA_FLOODING_FLD_MULTICAST GENMASK(5, 0)
0109 #define ANA_FLOODING_FLD_MULTICAST_SET(x)\
0110 FIELD_PREP(ANA_FLOODING_FLD_MULTICAST, x)
0111 #define ANA_FLOODING_FLD_MULTICAST_GET(x)\
0112 FIELD_GET(ANA_FLOODING_FLD_MULTICAST, x)
0113
0114
0115 #define ANA_FLOODING_IPMC __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 100, 0, 1, 4)
0116
0117 #define ANA_FLOODING_IPMC_FLD_MC4_CTRL GENMASK(23, 18)
0118 #define ANA_FLOODING_IPMC_FLD_MC4_CTRL_SET(x)\
0119 FIELD_PREP(ANA_FLOODING_IPMC_FLD_MC4_CTRL, x)
0120 #define ANA_FLOODING_IPMC_FLD_MC4_CTRL_GET(x)\
0121 FIELD_GET(ANA_FLOODING_IPMC_FLD_MC4_CTRL, x)
0122
0123 #define ANA_FLOODING_IPMC_FLD_MC4_DATA GENMASK(17, 12)
0124 #define ANA_FLOODING_IPMC_FLD_MC4_DATA_SET(x)\
0125 FIELD_PREP(ANA_FLOODING_IPMC_FLD_MC4_DATA, x)
0126 #define ANA_FLOODING_IPMC_FLD_MC4_DATA_GET(x)\
0127 FIELD_GET(ANA_FLOODING_IPMC_FLD_MC4_DATA, x)
0128
0129 #define ANA_FLOODING_IPMC_FLD_MC6_CTRL GENMASK(11, 6)
0130 #define ANA_FLOODING_IPMC_FLD_MC6_CTRL_SET(x)\
0131 FIELD_PREP(ANA_FLOODING_IPMC_FLD_MC6_CTRL, x)
0132 #define ANA_FLOODING_IPMC_FLD_MC6_CTRL_GET(x)\
0133 FIELD_GET(ANA_FLOODING_IPMC_FLD_MC6_CTRL, x)
0134
0135 #define ANA_FLOODING_IPMC_FLD_MC6_DATA GENMASK(5, 0)
0136 #define ANA_FLOODING_IPMC_FLD_MC6_DATA_SET(x)\
0137 FIELD_PREP(ANA_FLOODING_IPMC_FLD_MC6_DATA, x)
0138 #define ANA_FLOODING_IPMC_FLD_MC6_DATA_GET(x)\
0139 FIELD_GET(ANA_FLOODING_IPMC_FLD_MC6_DATA, x)
0140
0141
0142 #define ANA_PGID(g) __REG(TARGET_ANA, 0, 1, 27648, g, 89, 8, 0, 0, 1, 4)
0143
0144 #define ANA_PGID_PGID GENMASK(8, 0)
0145 #define ANA_PGID_PGID_SET(x)\
0146 FIELD_PREP(ANA_PGID_PGID, x)
0147 #define ANA_PGID_PGID_GET(x)\
0148 FIELD_GET(ANA_PGID_PGID, x)
0149
0150
0151 #define ANA_PGID_CFG(g) __REG(TARGET_ANA, 0, 1, 27648, g, 89, 8, 4, 0, 1, 4)
0152
0153 #define ANA_PGID_CFG_OBEY_VLAN BIT(0)
0154 #define ANA_PGID_CFG_OBEY_VLAN_SET(x)\
0155 FIELD_PREP(ANA_PGID_CFG_OBEY_VLAN, x)
0156 #define ANA_PGID_CFG_OBEY_VLAN_GET(x)\
0157 FIELD_GET(ANA_PGID_CFG_OBEY_VLAN, x)
0158
0159
0160 #define ANA_MACHDATA __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 40, 0, 1, 4)
0161
0162
0163 #define ANA_MACLDATA __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 44, 0, 1, 4)
0164
0165
0166 #define ANA_MACACCESS __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 48, 0, 1, 4)
0167
0168 #define ANA_MACACCESS_CHANGE2SW BIT(17)
0169 #define ANA_MACACCESS_CHANGE2SW_SET(x)\
0170 FIELD_PREP(ANA_MACACCESS_CHANGE2SW, x)
0171 #define ANA_MACACCESS_CHANGE2SW_GET(x)\
0172 FIELD_GET(ANA_MACACCESS_CHANGE2SW, x)
0173
0174 #define ANA_MACACCESS_MAC_CPU_COPY BIT(16)
0175 #define ANA_MACACCESS_MAC_CPU_COPY_SET(x)\
0176 FIELD_PREP(ANA_MACACCESS_MAC_CPU_COPY, x)
0177 #define ANA_MACACCESS_MAC_CPU_COPY_GET(x)\
0178 FIELD_GET(ANA_MACACCESS_MAC_CPU_COPY, x)
0179
0180 #define ANA_MACACCESS_VALID BIT(12)
0181 #define ANA_MACACCESS_VALID_SET(x)\
0182 FIELD_PREP(ANA_MACACCESS_VALID, x)
0183 #define ANA_MACACCESS_VALID_GET(x)\
0184 FIELD_GET(ANA_MACACCESS_VALID, x)
0185
0186 #define ANA_MACACCESS_ENTRYTYPE GENMASK(11, 10)
0187 #define ANA_MACACCESS_ENTRYTYPE_SET(x)\
0188 FIELD_PREP(ANA_MACACCESS_ENTRYTYPE, x)
0189 #define ANA_MACACCESS_ENTRYTYPE_GET(x)\
0190 FIELD_GET(ANA_MACACCESS_ENTRYTYPE, x)
0191
0192 #define ANA_MACACCESS_DEST_IDX GENMASK(9, 4)
0193 #define ANA_MACACCESS_DEST_IDX_SET(x)\
0194 FIELD_PREP(ANA_MACACCESS_DEST_IDX, x)
0195 #define ANA_MACACCESS_DEST_IDX_GET(x)\
0196 FIELD_GET(ANA_MACACCESS_DEST_IDX, x)
0197
0198 #define ANA_MACACCESS_MAC_TABLE_CMD GENMASK(3, 0)
0199 #define ANA_MACACCESS_MAC_TABLE_CMD_SET(x)\
0200 FIELD_PREP(ANA_MACACCESS_MAC_TABLE_CMD, x)
0201 #define ANA_MACACCESS_MAC_TABLE_CMD_GET(x)\
0202 FIELD_GET(ANA_MACACCESS_MAC_TABLE_CMD, x)
0203
0204
0205 #define ANA_MACTINDX __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 52, 0, 1, 4)
0206
0207 #define ANA_MACTINDX_BUCKET GENMASK(12, 11)
0208 #define ANA_MACTINDX_BUCKET_SET(x)\
0209 FIELD_PREP(ANA_MACTINDX_BUCKET, x)
0210 #define ANA_MACTINDX_BUCKET_GET(x)\
0211 FIELD_GET(ANA_MACTINDX_BUCKET, x)
0212
0213 #define ANA_MACTINDX_M_INDEX GENMASK(10, 0)
0214 #define ANA_MACTINDX_M_INDEX_SET(x)\
0215 FIELD_PREP(ANA_MACTINDX_M_INDEX, x)
0216 #define ANA_MACTINDX_M_INDEX_GET(x)\
0217 FIELD_GET(ANA_MACTINDX_M_INDEX, x)
0218
0219
0220 #define ANA_VLAN_PORT_MASK __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 56, 0, 1, 4)
0221
0222 #define ANA_VLAN_PORT_MASK_VLAN_PORT_MASK GENMASK(8, 0)
0223 #define ANA_VLAN_PORT_MASK_VLAN_PORT_MASK_SET(x)\
0224 FIELD_PREP(ANA_VLAN_PORT_MASK_VLAN_PORT_MASK, x)
0225 #define ANA_VLAN_PORT_MASK_VLAN_PORT_MASK_GET(x)\
0226 FIELD_GET(ANA_VLAN_PORT_MASK_VLAN_PORT_MASK, x)
0227
0228
0229 #define ANA_VLANACCESS __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 60, 0, 1, 4)
0230
0231 #define ANA_VLANACCESS_VLAN_TBL_CMD GENMASK(1, 0)
0232 #define ANA_VLANACCESS_VLAN_TBL_CMD_SET(x)\
0233 FIELD_PREP(ANA_VLANACCESS_VLAN_TBL_CMD, x)
0234 #define ANA_VLANACCESS_VLAN_TBL_CMD_GET(x)\
0235 FIELD_GET(ANA_VLANACCESS_VLAN_TBL_CMD, x)
0236
0237
0238 #define ANA_VLANTIDX __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 64, 0, 1, 4)
0239
0240 #define ANA_VLANTIDX_VLAN_PGID_CPU_DIS BIT(18)
0241 #define ANA_VLANTIDX_VLAN_PGID_CPU_DIS_SET(x)\
0242 FIELD_PREP(ANA_VLANTIDX_VLAN_PGID_CPU_DIS, x)
0243 #define ANA_VLANTIDX_VLAN_PGID_CPU_DIS_GET(x)\
0244 FIELD_GET(ANA_VLANTIDX_VLAN_PGID_CPU_DIS, x)
0245
0246 #define ANA_VLANTIDX_V_INDEX GENMASK(11, 0)
0247 #define ANA_VLANTIDX_V_INDEX_SET(x)\
0248 FIELD_PREP(ANA_VLANTIDX_V_INDEX, x)
0249 #define ANA_VLANTIDX_V_INDEX_GET(x)\
0250 FIELD_GET(ANA_VLANTIDX_V_INDEX, x)
0251
0252
0253 #define ANA_VLAN_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 0, 0, 1, 4)
0254
0255 #define ANA_VLAN_CFG_VLAN_AWARE_ENA BIT(20)
0256 #define ANA_VLAN_CFG_VLAN_AWARE_ENA_SET(x)\
0257 FIELD_PREP(ANA_VLAN_CFG_VLAN_AWARE_ENA, x)
0258 #define ANA_VLAN_CFG_VLAN_AWARE_ENA_GET(x)\
0259 FIELD_GET(ANA_VLAN_CFG_VLAN_AWARE_ENA, x)
0260
0261 #define ANA_VLAN_CFG_VLAN_POP_CNT GENMASK(19, 18)
0262 #define ANA_VLAN_CFG_VLAN_POP_CNT_SET(x)\
0263 FIELD_PREP(ANA_VLAN_CFG_VLAN_POP_CNT, x)
0264 #define ANA_VLAN_CFG_VLAN_POP_CNT_GET(x)\
0265 FIELD_GET(ANA_VLAN_CFG_VLAN_POP_CNT, x)
0266
0267 #define ANA_VLAN_CFG_VLAN_VID GENMASK(11, 0)
0268 #define ANA_VLAN_CFG_VLAN_VID_SET(x)\
0269 FIELD_PREP(ANA_VLAN_CFG_VLAN_VID, x)
0270 #define ANA_VLAN_CFG_VLAN_VID_GET(x)\
0271 FIELD_GET(ANA_VLAN_CFG_VLAN_VID, x)
0272
0273
0274 #define ANA_DROP_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 4, 0, 1, 4)
0275
0276 #define ANA_DROP_CFG_DROP_UNTAGGED_ENA BIT(6)
0277 #define ANA_DROP_CFG_DROP_UNTAGGED_ENA_SET(x)\
0278 FIELD_PREP(ANA_DROP_CFG_DROP_UNTAGGED_ENA, x)
0279 #define ANA_DROP_CFG_DROP_UNTAGGED_ENA_GET(x)\
0280 FIELD_GET(ANA_DROP_CFG_DROP_UNTAGGED_ENA, x)
0281
0282 #define ANA_DROP_CFG_DROP_PRIO_S_TAGGED_ENA BIT(3)
0283 #define ANA_DROP_CFG_DROP_PRIO_S_TAGGED_ENA_SET(x)\
0284 FIELD_PREP(ANA_DROP_CFG_DROP_PRIO_S_TAGGED_ENA, x)
0285 #define ANA_DROP_CFG_DROP_PRIO_S_TAGGED_ENA_GET(x)\
0286 FIELD_GET(ANA_DROP_CFG_DROP_PRIO_S_TAGGED_ENA, x)
0287
0288 #define ANA_DROP_CFG_DROP_PRIO_C_TAGGED_ENA BIT(2)
0289 #define ANA_DROP_CFG_DROP_PRIO_C_TAGGED_ENA_SET(x)\
0290 FIELD_PREP(ANA_DROP_CFG_DROP_PRIO_C_TAGGED_ENA, x)
0291 #define ANA_DROP_CFG_DROP_PRIO_C_TAGGED_ENA_GET(x)\
0292 FIELD_GET(ANA_DROP_CFG_DROP_PRIO_C_TAGGED_ENA, x)
0293
0294 #define ANA_DROP_CFG_DROP_MC_SMAC_ENA BIT(0)
0295 #define ANA_DROP_CFG_DROP_MC_SMAC_ENA_SET(x)\
0296 FIELD_PREP(ANA_DROP_CFG_DROP_MC_SMAC_ENA, x)
0297 #define ANA_DROP_CFG_DROP_MC_SMAC_ENA_GET(x)\
0298 FIELD_GET(ANA_DROP_CFG_DROP_MC_SMAC_ENA, x)
0299
0300
0301 #define ANA_CPU_FWD_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 96, 0, 1, 4)
0302
0303 #define ANA_CPU_FWD_CFG_MLD_REDIR_ENA BIT(6)
0304 #define ANA_CPU_FWD_CFG_MLD_REDIR_ENA_SET(x)\
0305 FIELD_PREP(ANA_CPU_FWD_CFG_MLD_REDIR_ENA, x)
0306 #define ANA_CPU_FWD_CFG_MLD_REDIR_ENA_GET(x)\
0307 FIELD_GET(ANA_CPU_FWD_CFG_MLD_REDIR_ENA, x)
0308
0309 #define ANA_CPU_FWD_CFG_IGMP_REDIR_ENA BIT(5)
0310 #define ANA_CPU_FWD_CFG_IGMP_REDIR_ENA_SET(x)\
0311 FIELD_PREP(ANA_CPU_FWD_CFG_IGMP_REDIR_ENA, x)
0312 #define ANA_CPU_FWD_CFG_IGMP_REDIR_ENA_GET(x)\
0313 FIELD_GET(ANA_CPU_FWD_CFG_IGMP_REDIR_ENA, x)
0314
0315 #define ANA_CPU_FWD_CFG_IPMC_CTRL_COPY_ENA BIT(4)
0316 #define ANA_CPU_FWD_CFG_IPMC_CTRL_COPY_ENA_SET(x)\
0317 FIELD_PREP(ANA_CPU_FWD_CFG_IPMC_CTRL_COPY_ENA, x)
0318 #define ANA_CPU_FWD_CFG_IPMC_CTRL_COPY_ENA_GET(x)\
0319 FIELD_GET(ANA_CPU_FWD_CFG_IPMC_CTRL_COPY_ENA, x)
0320
0321 #define ANA_CPU_FWD_CFG_SRC_COPY_ENA BIT(3)
0322 #define ANA_CPU_FWD_CFG_SRC_COPY_ENA_SET(x)\
0323 FIELD_PREP(ANA_CPU_FWD_CFG_SRC_COPY_ENA, x)
0324 #define ANA_CPU_FWD_CFG_SRC_COPY_ENA_GET(x)\
0325 FIELD_GET(ANA_CPU_FWD_CFG_SRC_COPY_ENA, x)
0326
0327
0328 #define ANA_CPU_FWD_BPDU_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 100, 0, 1, 4)
0329
0330
0331 #define ANA_PORT_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 112, 0, 1, 4)
0332
0333 #define ANA_PORT_CFG_LEARNAUTO BIT(6)
0334 #define ANA_PORT_CFG_LEARNAUTO_SET(x)\
0335 FIELD_PREP(ANA_PORT_CFG_LEARNAUTO, x)
0336 #define ANA_PORT_CFG_LEARNAUTO_GET(x)\
0337 FIELD_GET(ANA_PORT_CFG_LEARNAUTO, x)
0338
0339 #define ANA_PORT_CFG_LEARN_ENA BIT(5)
0340 #define ANA_PORT_CFG_LEARN_ENA_SET(x)\
0341 FIELD_PREP(ANA_PORT_CFG_LEARN_ENA, x)
0342 #define ANA_PORT_CFG_LEARN_ENA_GET(x)\
0343 FIELD_GET(ANA_PORT_CFG_LEARN_ENA, x)
0344
0345 #define ANA_PORT_CFG_RECV_ENA BIT(4)
0346 #define ANA_PORT_CFG_RECV_ENA_SET(x)\
0347 FIELD_PREP(ANA_PORT_CFG_RECV_ENA, x)
0348 #define ANA_PORT_CFG_RECV_ENA_GET(x)\
0349 FIELD_GET(ANA_PORT_CFG_RECV_ENA, x)
0350
0351 #define ANA_PORT_CFG_PORTID_VAL GENMASK(3, 0)
0352 #define ANA_PORT_CFG_PORTID_VAL_SET(x)\
0353 FIELD_PREP(ANA_PORT_CFG_PORTID_VAL, x)
0354 #define ANA_PORT_CFG_PORTID_VAL_GET(x)\
0355 FIELD_GET(ANA_PORT_CFG_PORTID_VAL, x)
0356
0357
0358 #define ANA_PFC_CFG(g) __REG(TARGET_ANA, 0, 1, 30720, g, 8, 64, 0, 0, 1, 4)
0359
0360 #define ANA_PFC_CFG_FC_LINK_SPEED GENMASK(1, 0)
0361 #define ANA_PFC_CFG_FC_LINK_SPEED_SET(x)\
0362 FIELD_PREP(ANA_PFC_CFG_FC_LINK_SPEED, x)
0363 #define ANA_PFC_CFG_FC_LINK_SPEED_GET(x)\
0364 FIELD_GET(ANA_PFC_CFG_FC_LINK_SPEED, x)
0365
0366
0367 #define CHIP_TOP_CUPHY_PORT_CFG(r) __REG(TARGET_CHIP_TOP, 0, 1, 16, 0, 1, 20, 8, r, 2, 4)
0368
0369 #define CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA BIT(0)
0370 #define CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA_SET(x)\
0371 FIELD_PREP(CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA, x)
0372 #define CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA_GET(x)\
0373 FIELD_GET(CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA, x)
0374
0375
0376 #define DEV_CLOCK_CFG(t) __REG(TARGET_DEV, t, 8, 0, 0, 1, 28, 0, 0, 1, 4)
0377
0378 #define DEV_CLOCK_CFG_MAC_TX_RST BIT(7)
0379 #define DEV_CLOCK_CFG_MAC_TX_RST_SET(x)\
0380 FIELD_PREP(DEV_CLOCK_CFG_MAC_TX_RST, x)
0381 #define DEV_CLOCK_CFG_MAC_TX_RST_GET(x)\
0382 FIELD_GET(DEV_CLOCK_CFG_MAC_TX_RST, x)
0383
0384 #define DEV_CLOCK_CFG_MAC_RX_RST BIT(6)
0385 #define DEV_CLOCK_CFG_MAC_RX_RST_SET(x)\
0386 FIELD_PREP(DEV_CLOCK_CFG_MAC_RX_RST, x)
0387 #define DEV_CLOCK_CFG_MAC_RX_RST_GET(x)\
0388 FIELD_GET(DEV_CLOCK_CFG_MAC_RX_RST, x)
0389
0390 #define DEV_CLOCK_CFG_PCS_TX_RST BIT(5)
0391 #define DEV_CLOCK_CFG_PCS_TX_RST_SET(x)\
0392 FIELD_PREP(DEV_CLOCK_CFG_PCS_TX_RST, x)
0393 #define DEV_CLOCK_CFG_PCS_TX_RST_GET(x)\
0394 FIELD_GET(DEV_CLOCK_CFG_PCS_TX_RST, x)
0395
0396 #define DEV_CLOCK_CFG_PCS_RX_RST BIT(4)
0397 #define DEV_CLOCK_CFG_PCS_RX_RST_SET(x)\
0398 FIELD_PREP(DEV_CLOCK_CFG_PCS_RX_RST, x)
0399 #define DEV_CLOCK_CFG_PCS_RX_RST_GET(x)\
0400 FIELD_GET(DEV_CLOCK_CFG_PCS_RX_RST, x)
0401
0402 #define DEV_CLOCK_CFG_PORT_RST BIT(3)
0403 #define DEV_CLOCK_CFG_PORT_RST_SET(x)\
0404 FIELD_PREP(DEV_CLOCK_CFG_PORT_RST, x)
0405 #define DEV_CLOCK_CFG_PORT_RST_GET(x)\
0406 FIELD_GET(DEV_CLOCK_CFG_PORT_RST, x)
0407
0408 #define DEV_CLOCK_CFG_LINK_SPEED GENMASK(1, 0)
0409 #define DEV_CLOCK_CFG_LINK_SPEED_SET(x)\
0410 FIELD_PREP(DEV_CLOCK_CFG_LINK_SPEED, x)
0411 #define DEV_CLOCK_CFG_LINK_SPEED_GET(x)\
0412 FIELD_GET(DEV_CLOCK_CFG_LINK_SPEED, x)
0413
0414
0415 #define DEV_MAC_ENA_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 0, 0, 1, 4)
0416
0417 #define DEV_MAC_ENA_CFG_RX_ENA BIT(4)
0418 #define DEV_MAC_ENA_CFG_RX_ENA_SET(x)\
0419 FIELD_PREP(DEV_MAC_ENA_CFG_RX_ENA, x)
0420 #define DEV_MAC_ENA_CFG_RX_ENA_GET(x)\
0421 FIELD_GET(DEV_MAC_ENA_CFG_RX_ENA, x)
0422
0423 #define DEV_MAC_ENA_CFG_TX_ENA BIT(0)
0424 #define DEV_MAC_ENA_CFG_TX_ENA_SET(x)\
0425 FIELD_PREP(DEV_MAC_ENA_CFG_TX_ENA, x)
0426 #define DEV_MAC_ENA_CFG_TX_ENA_GET(x)\
0427 FIELD_GET(DEV_MAC_ENA_CFG_TX_ENA, x)
0428
0429
0430 #define DEV_MAC_MODE_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 4, 0, 1, 4)
0431
0432 #define DEV_MAC_MODE_CFG_GIGA_MODE_ENA BIT(4)
0433 #define DEV_MAC_MODE_CFG_GIGA_MODE_ENA_SET(x)\
0434 FIELD_PREP(DEV_MAC_MODE_CFG_GIGA_MODE_ENA, x)
0435 #define DEV_MAC_MODE_CFG_GIGA_MODE_ENA_GET(x)\
0436 FIELD_GET(DEV_MAC_MODE_CFG_GIGA_MODE_ENA, x)
0437
0438
0439 #define DEV_MAC_MAXLEN_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 8, 0, 1, 4)
0440
0441 #define DEV_MAC_MAXLEN_CFG_MAX_LEN GENMASK(15, 0)
0442 #define DEV_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\
0443 FIELD_PREP(DEV_MAC_MAXLEN_CFG_MAX_LEN, x)
0444 #define DEV_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\
0445 FIELD_GET(DEV_MAC_MAXLEN_CFG_MAX_LEN, x)
0446
0447
0448 #define DEV_MAC_IFG_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 20, 0, 1, 4)
0449
0450 #define DEV_MAC_IFG_CFG_TX_IFG GENMASK(12, 8)
0451 #define DEV_MAC_IFG_CFG_TX_IFG_SET(x)\
0452 FIELD_PREP(DEV_MAC_IFG_CFG_TX_IFG, x)
0453 #define DEV_MAC_IFG_CFG_TX_IFG_GET(x)\
0454 FIELD_GET(DEV_MAC_IFG_CFG_TX_IFG, x)
0455
0456 #define DEV_MAC_IFG_CFG_RX_IFG2 GENMASK(7, 4)
0457 #define DEV_MAC_IFG_CFG_RX_IFG2_SET(x)\
0458 FIELD_PREP(DEV_MAC_IFG_CFG_RX_IFG2, x)
0459 #define DEV_MAC_IFG_CFG_RX_IFG2_GET(x)\
0460 FIELD_GET(DEV_MAC_IFG_CFG_RX_IFG2, x)
0461
0462 #define DEV_MAC_IFG_CFG_RX_IFG1 GENMASK(3, 0)
0463 #define DEV_MAC_IFG_CFG_RX_IFG1_SET(x)\
0464 FIELD_PREP(DEV_MAC_IFG_CFG_RX_IFG1, x)
0465 #define DEV_MAC_IFG_CFG_RX_IFG1_GET(x)\
0466 FIELD_GET(DEV_MAC_IFG_CFG_RX_IFG1, x)
0467
0468
0469 #define DEV_MAC_HDX_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 24, 0, 1, 4)
0470
0471 #define DEV_MAC_HDX_CFG_SEED GENMASK(23, 16)
0472 #define DEV_MAC_HDX_CFG_SEED_SET(x)\
0473 FIELD_PREP(DEV_MAC_HDX_CFG_SEED, x)
0474 #define DEV_MAC_HDX_CFG_SEED_GET(x)\
0475 FIELD_GET(DEV_MAC_HDX_CFG_SEED, x)
0476
0477 #define DEV_MAC_HDX_CFG_SEED_LOAD BIT(12)
0478 #define DEV_MAC_HDX_CFG_SEED_LOAD_SET(x)\
0479 FIELD_PREP(DEV_MAC_HDX_CFG_SEED_LOAD, x)
0480 #define DEV_MAC_HDX_CFG_SEED_LOAD_GET(x)\
0481 FIELD_GET(DEV_MAC_HDX_CFG_SEED_LOAD, x)
0482
0483
0484 #define DEV_FC_MAC_LOW_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 32, 0, 1, 4)
0485
0486
0487 #define DEV_FC_MAC_HIGH_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 36, 0, 1, 4)
0488
0489
0490 #define DEV_PCS1G_CFG(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 0, 0, 1, 4)
0491
0492 #define DEV_PCS1G_CFG_PCS_ENA BIT(0)
0493 #define DEV_PCS1G_CFG_PCS_ENA_SET(x)\
0494 FIELD_PREP(DEV_PCS1G_CFG_PCS_ENA, x)
0495 #define DEV_PCS1G_CFG_PCS_ENA_GET(x)\
0496 FIELD_GET(DEV_PCS1G_CFG_PCS_ENA, x)
0497
0498
0499 #define DEV_PCS1G_MODE_CFG(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 4, 0, 1, 4)
0500
0501 #define DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA BIT(0)
0502 #define DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA_SET(x)\
0503 FIELD_PREP(DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA, x)
0504 #define DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA_GET(x)\
0505 FIELD_GET(DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA, x)
0506
0507
0508 #define DEV_PCS1G_SD_CFG(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 8, 0, 1, 4)
0509
0510 #define DEV_PCS1G_SD_CFG_SD_ENA BIT(0)
0511 #define DEV_PCS1G_SD_CFG_SD_ENA_SET(x)\
0512 FIELD_PREP(DEV_PCS1G_SD_CFG_SD_ENA, x)
0513 #define DEV_PCS1G_SD_CFG_SD_ENA_GET(x)\
0514 FIELD_GET(DEV_PCS1G_SD_CFG_SD_ENA, x)
0515
0516
0517 #define DEV_PCS1G_ANEG_CFG(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 12, 0, 1, 4)
0518
0519 #define DEV_PCS1G_ANEG_CFG_ADV_ABILITY GENMASK(31, 16)
0520 #define DEV_PCS1G_ANEG_CFG_ADV_ABILITY_SET(x)\
0521 FIELD_PREP(DEV_PCS1G_ANEG_CFG_ADV_ABILITY, x)
0522 #define DEV_PCS1G_ANEG_CFG_ADV_ABILITY_GET(x)\
0523 FIELD_GET(DEV_PCS1G_ANEG_CFG_ADV_ABILITY, x)
0524
0525 #define DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA BIT(8)
0526 #define DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_SET(x)\
0527 FIELD_PREP(DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA, x)
0528 #define DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_GET(x)\
0529 FIELD_GET(DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA, x)
0530
0531 #define DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT BIT(1)
0532 #define DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT_SET(x)\
0533 FIELD_PREP(DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT, x)
0534 #define DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT_GET(x)\
0535 FIELD_GET(DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT, x)
0536
0537 #define DEV_PCS1G_ANEG_CFG_ENA BIT(0)
0538 #define DEV_PCS1G_ANEG_CFG_ENA_SET(x)\
0539 FIELD_PREP(DEV_PCS1G_ANEG_CFG_ENA, x)
0540 #define DEV_PCS1G_ANEG_CFG_ENA_GET(x)\
0541 FIELD_GET(DEV_PCS1G_ANEG_CFG_ENA, x)
0542
0543
0544 #define DEV_PCS1G_ANEG_STATUS(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 32, 0, 1, 4)
0545
0546 #define DEV_PCS1G_ANEG_STATUS_LP_ADV GENMASK(31, 16)
0547 #define DEV_PCS1G_ANEG_STATUS_LP_ADV_SET(x)\
0548 FIELD_PREP(DEV_PCS1G_ANEG_STATUS_LP_ADV, x)
0549 #define DEV_PCS1G_ANEG_STATUS_LP_ADV_GET(x)\
0550 FIELD_GET(DEV_PCS1G_ANEG_STATUS_LP_ADV, x)
0551
0552 #define DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE BIT(0)
0553 #define DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE_SET(x)\
0554 FIELD_PREP(DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE, x)
0555 #define DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE_GET(x)\
0556 FIELD_GET(DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE, x)
0557
0558
0559 #define DEV_PCS1G_LINK_STATUS(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 40, 0, 1, 4)
0560
0561 #define DEV_PCS1G_LINK_STATUS_LINK_STATUS BIT(4)
0562 #define DEV_PCS1G_LINK_STATUS_LINK_STATUS_SET(x)\
0563 FIELD_PREP(DEV_PCS1G_LINK_STATUS_LINK_STATUS, x)
0564 #define DEV_PCS1G_LINK_STATUS_LINK_STATUS_GET(x)\
0565 FIELD_GET(DEV_PCS1G_LINK_STATUS_LINK_STATUS, x)
0566
0567 #define DEV_PCS1G_LINK_STATUS_SYNC_STATUS BIT(0)
0568 #define DEV_PCS1G_LINK_STATUS_SYNC_STATUS_SET(x)\
0569 FIELD_PREP(DEV_PCS1G_LINK_STATUS_SYNC_STATUS, x)
0570 #define DEV_PCS1G_LINK_STATUS_SYNC_STATUS_GET(x)\
0571 FIELD_GET(DEV_PCS1G_LINK_STATUS_SYNC_STATUS, x)
0572
0573
0574 #define DEV_PCS1G_STICKY(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 48, 0, 1, 4)
0575
0576 #define DEV_PCS1G_STICKY_LINK_DOWN_STICKY BIT(4)
0577 #define DEV_PCS1G_STICKY_LINK_DOWN_STICKY_SET(x)\
0578 FIELD_PREP(DEV_PCS1G_STICKY_LINK_DOWN_STICKY, x)
0579 #define DEV_PCS1G_STICKY_LINK_DOWN_STICKY_GET(x)\
0580 FIELD_GET(DEV_PCS1G_STICKY_LINK_DOWN_STICKY, x)
0581
0582
0583 #define FDMA_CH_ACTIVATE __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 0, 0, 1, 4)
0584
0585 #define FDMA_CH_ACTIVATE_CH_ACTIVATE GENMASK(7, 0)
0586 #define FDMA_CH_ACTIVATE_CH_ACTIVATE_SET(x)\
0587 FIELD_PREP(FDMA_CH_ACTIVATE_CH_ACTIVATE, x)
0588 #define FDMA_CH_ACTIVATE_CH_ACTIVATE_GET(x)\
0589 FIELD_GET(FDMA_CH_ACTIVATE_CH_ACTIVATE, x)
0590
0591
0592 #define FDMA_CH_RELOAD __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 4, 0, 1, 4)
0593
0594 #define FDMA_CH_RELOAD_CH_RELOAD GENMASK(7, 0)
0595 #define FDMA_CH_RELOAD_CH_RELOAD_SET(x)\
0596 FIELD_PREP(FDMA_CH_RELOAD_CH_RELOAD, x)
0597 #define FDMA_CH_RELOAD_CH_RELOAD_GET(x)\
0598 FIELD_GET(FDMA_CH_RELOAD_CH_RELOAD, x)
0599
0600
0601 #define FDMA_CH_DISABLE __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 8, 0, 1, 4)
0602
0603 #define FDMA_CH_DISABLE_CH_DISABLE GENMASK(7, 0)
0604 #define FDMA_CH_DISABLE_CH_DISABLE_SET(x)\
0605 FIELD_PREP(FDMA_CH_DISABLE_CH_DISABLE, x)
0606 #define FDMA_CH_DISABLE_CH_DISABLE_GET(x)\
0607 FIELD_GET(FDMA_CH_DISABLE_CH_DISABLE, x)
0608
0609
0610 #define FDMA_CH_DB_DISCARD __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 16, 0, 1, 4)
0611
0612 #define FDMA_CH_DB_DISCARD_DB_DISCARD GENMASK(7, 0)
0613 #define FDMA_CH_DB_DISCARD_DB_DISCARD_SET(x)\
0614 FIELD_PREP(FDMA_CH_DB_DISCARD_DB_DISCARD, x)
0615 #define FDMA_CH_DB_DISCARD_DB_DISCARD_GET(x)\
0616 FIELD_GET(FDMA_CH_DB_DISCARD_DB_DISCARD, x)
0617
0618
0619 #define FDMA_DCB_LLP(r) __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 52, r, 8, 4)
0620
0621
0622 #define FDMA_DCB_LLP1(r) __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 84, r, 8, 4)
0623
0624
0625 #define FDMA_CH_ACTIVE __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 180, 0, 1, 4)
0626
0627
0628 #define FDMA_CH_CFG(r) __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 224, r, 8, 4)
0629
0630 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY BIT(4)
0631 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_SET(x)\
0632 FIELD_PREP(FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY, x)
0633 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_GET(x)\
0634 FIELD_GET(FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY, x)
0635
0636 #define FDMA_CH_CFG_CH_INJ_PORT BIT(3)
0637 #define FDMA_CH_CFG_CH_INJ_PORT_SET(x)\
0638 FIELD_PREP(FDMA_CH_CFG_CH_INJ_PORT, x)
0639 #define FDMA_CH_CFG_CH_INJ_PORT_GET(x)\
0640 FIELD_GET(FDMA_CH_CFG_CH_INJ_PORT, x)
0641
0642 #define FDMA_CH_CFG_CH_DCB_DB_CNT GENMASK(2, 1)
0643 #define FDMA_CH_CFG_CH_DCB_DB_CNT_SET(x)\
0644 FIELD_PREP(FDMA_CH_CFG_CH_DCB_DB_CNT, x)
0645 #define FDMA_CH_CFG_CH_DCB_DB_CNT_GET(x)\
0646 FIELD_GET(FDMA_CH_CFG_CH_DCB_DB_CNT, x)
0647
0648 #define FDMA_CH_CFG_CH_MEM BIT(0)
0649 #define FDMA_CH_CFG_CH_MEM_SET(x)\
0650 FIELD_PREP(FDMA_CH_CFG_CH_MEM, x)
0651 #define FDMA_CH_CFG_CH_MEM_GET(x)\
0652 FIELD_GET(FDMA_CH_CFG_CH_MEM, x)
0653
0654
0655 #define FDMA_PORT_CTRL(r) __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 376, r, 2, 4)
0656
0657 #define FDMA_PORT_CTRL_INJ_STOP BIT(4)
0658 #define FDMA_PORT_CTRL_INJ_STOP_SET(x)\
0659 FIELD_PREP(FDMA_PORT_CTRL_INJ_STOP, x)
0660 #define FDMA_PORT_CTRL_INJ_STOP_GET(x)\
0661 FIELD_GET(FDMA_PORT_CTRL_INJ_STOP, x)
0662
0663 #define FDMA_PORT_CTRL_XTR_STOP BIT(2)
0664 #define FDMA_PORT_CTRL_XTR_STOP_SET(x)\
0665 FIELD_PREP(FDMA_PORT_CTRL_XTR_STOP, x)
0666 #define FDMA_PORT_CTRL_XTR_STOP_GET(x)\
0667 FIELD_GET(FDMA_PORT_CTRL_XTR_STOP, x)
0668
0669
0670 #define FDMA_INTR_DB __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 392, 0, 1, 4)
0671
0672
0673 #define FDMA_INTR_DB_ENA __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 396, 0, 1, 4)
0674
0675 #define FDMA_INTR_DB_ENA_INTR_DB_ENA GENMASK(7, 0)
0676 #define FDMA_INTR_DB_ENA_INTR_DB_ENA_SET(x)\
0677 FIELD_PREP(FDMA_INTR_DB_ENA_INTR_DB_ENA, x)
0678 #define FDMA_INTR_DB_ENA_INTR_DB_ENA_GET(x)\
0679 FIELD_GET(FDMA_INTR_DB_ENA_INTR_DB_ENA, x)
0680
0681
0682 #define FDMA_INTR_ERR __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 400, 0, 1, 4)
0683
0684
0685 #define FDMA_ERRORS __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 412, 0, 1, 4)
0686
0687
0688 #define PTP_PIN_INTR __REG(TARGET_PTP, 0, 1, 512, 0, 1, 16, 0, 0, 1, 4)
0689
0690 #define PTP_PIN_INTR_INTR_PTP GENMASK(7, 0)
0691 #define PTP_PIN_INTR_INTR_PTP_SET(x)\
0692 FIELD_PREP(PTP_PIN_INTR_INTR_PTP, x)
0693 #define PTP_PIN_INTR_INTR_PTP_GET(x)\
0694 FIELD_GET(PTP_PIN_INTR_INTR_PTP, x)
0695
0696
0697 #define PTP_PIN_INTR_ENA __REG(TARGET_PTP, 0, 1, 512, 0, 1, 16, 4, 0, 1, 4)
0698
0699 #define PTP_PIN_INTR_ENA_INTR_ENA GENMASK(7, 0)
0700 #define PTP_PIN_INTR_ENA_INTR_ENA_SET(x)\
0701 FIELD_PREP(PTP_PIN_INTR_ENA_INTR_ENA, x)
0702 #define PTP_PIN_INTR_ENA_INTR_ENA_GET(x)\
0703 FIELD_GET(PTP_PIN_INTR_ENA_INTR_ENA, x)
0704
0705
0706 #define PTP_DOM_CFG __REG(TARGET_PTP, 0, 1, 512, 0, 1, 16, 12, 0, 1, 4)
0707
0708 #define PTP_DOM_CFG_ENA GENMASK(11, 9)
0709 #define PTP_DOM_CFG_ENA_SET(x)\
0710 FIELD_PREP(PTP_DOM_CFG_ENA, x)
0711 #define PTP_DOM_CFG_ENA_GET(x)\
0712 FIELD_GET(PTP_DOM_CFG_ENA, x)
0713
0714 #define PTP_DOM_CFG_CLKCFG_DIS GENMASK(2, 0)
0715 #define PTP_DOM_CFG_CLKCFG_DIS_SET(x)\
0716 FIELD_PREP(PTP_DOM_CFG_CLKCFG_DIS, x)
0717 #define PTP_DOM_CFG_CLKCFG_DIS_GET(x)\
0718 FIELD_GET(PTP_DOM_CFG_CLKCFG_DIS, x)
0719
0720
0721 #define PTP_CLK_PER_CFG(g, r) __REG(TARGET_PTP, 0, 1, 528, g, 3, 28, 0, r, 2, 4)
0722
0723
0724 #define PTP_PIN_CFG(g) __REG(TARGET_PTP, 0, 1, 0, g, 8, 64, 0, 0, 1, 4)
0725
0726 #define PTP_PIN_CFG_PIN_ACTION GENMASK(29, 27)
0727 #define PTP_PIN_CFG_PIN_ACTION_SET(x)\
0728 FIELD_PREP(PTP_PIN_CFG_PIN_ACTION, x)
0729 #define PTP_PIN_CFG_PIN_ACTION_GET(x)\
0730 FIELD_GET(PTP_PIN_CFG_PIN_ACTION, x)
0731
0732 #define PTP_PIN_CFG_PIN_SYNC GENMASK(26, 25)
0733 #define PTP_PIN_CFG_PIN_SYNC_SET(x)\
0734 FIELD_PREP(PTP_PIN_CFG_PIN_SYNC, x)
0735 #define PTP_PIN_CFG_PIN_SYNC_GET(x)\
0736 FIELD_GET(PTP_PIN_CFG_PIN_SYNC, x)
0737
0738 #define PTP_PIN_CFG_PIN_SELECT GENMASK(23, 21)
0739 #define PTP_PIN_CFG_PIN_SELECT_SET(x)\
0740 FIELD_PREP(PTP_PIN_CFG_PIN_SELECT, x)
0741 #define PTP_PIN_CFG_PIN_SELECT_GET(x)\
0742 FIELD_GET(PTP_PIN_CFG_PIN_SELECT, x)
0743
0744 #define PTP_PIN_CFG_PIN_DOM GENMASK(17, 16)
0745 #define PTP_PIN_CFG_PIN_DOM_SET(x)\
0746 FIELD_PREP(PTP_PIN_CFG_PIN_DOM, x)
0747 #define PTP_PIN_CFG_PIN_DOM_GET(x)\
0748 FIELD_GET(PTP_PIN_CFG_PIN_DOM, x)
0749
0750
0751 #define PTP_TOD_SEC_MSB(g) __REG(TARGET_PTP, 0, 1, 0, g, 8, 64, 4, 0, 1, 4)
0752
0753 #define PTP_TOD_SEC_MSB_TOD_SEC_MSB GENMASK(15, 0)
0754 #define PTP_TOD_SEC_MSB_TOD_SEC_MSB_SET(x)\
0755 FIELD_PREP(PTP_TOD_SEC_MSB_TOD_SEC_MSB, x)
0756 #define PTP_TOD_SEC_MSB_TOD_SEC_MSB_GET(x)\
0757 FIELD_GET(PTP_TOD_SEC_MSB_TOD_SEC_MSB, x)
0758
0759
0760 #define PTP_TOD_SEC_LSB(g) __REG(TARGET_PTP, 0, 1, 0, g, 8, 64, 8, 0, 1, 4)
0761
0762
0763 #define PTP_TOD_NSEC(g) __REG(TARGET_PTP, 0, 1, 0, g, 8, 64, 12, 0, 1, 4)
0764
0765 #define PTP_TOD_NSEC_TOD_NSEC GENMASK(29, 0)
0766 #define PTP_TOD_NSEC_TOD_NSEC_SET(x)\
0767 FIELD_PREP(PTP_TOD_NSEC_TOD_NSEC, x)
0768 #define PTP_TOD_NSEC_TOD_NSEC_GET(x)\
0769 FIELD_GET(PTP_TOD_NSEC_TOD_NSEC, x)
0770
0771
0772 #define PTP_WF_HIGH_PERIOD(g) __REG(TARGET_PTP,\
0773 0, 1, 0, g, 8, 64, 24, 0, 1, 4)
0774
0775 #define PTP_WF_HIGH_PERIOD_PIN_WFH(x) ((x) & GENMASK(29, 0))
0776 #define PTP_WF_HIGH_PERIOD_PIN_WFH_M GENMASK(29, 0)
0777 #define PTP_WF_HIGH_PERIOD_PIN_WFH_X(x) ((x) & GENMASK(29, 0))
0778
0779
0780 #define PTP_WF_LOW_PERIOD(g) __REG(TARGET_PTP,\
0781 0, 1, 0, g, 8, 64, 28, 0, 1, 4)
0782
0783 #define PTP_WF_LOW_PERIOD_PIN_WFL(x) ((x) & GENMASK(29, 0))
0784 #define PTP_WF_LOW_PERIOD_PIN_WFL_M GENMASK(29, 0)
0785 #define PTP_WF_LOW_PERIOD_PIN_WFL_X(x) ((x) & GENMASK(29, 0))
0786
0787
0788 #define PTP_TWOSTEP_CTRL __REG(TARGET_PTP, 0, 1, 612, 0, 1, 12, 0, 0, 1, 4)
0789
0790 #define PTP_TWOSTEP_CTRL_NXT BIT(11)
0791 #define PTP_TWOSTEP_CTRL_NXT_SET(x)\
0792 FIELD_PREP(PTP_TWOSTEP_CTRL_NXT, x)
0793 #define PTP_TWOSTEP_CTRL_NXT_GET(x)\
0794 FIELD_GET(PTP_TWOSTEP_CTRL_NXT, x)
0795
0796 #define PTP_TWOSTEP_CTRL_VLD BIT(10)
0797 #define PTP_TWOSTEP_CTRL_VLD_SET(x)\
0798 FIELD_PREP(PTP_TWOSTEP_CTRL_VLD, x)
0799 #define PTP_TWOSTEP_CTRL_VLD_GET(x)\
0800 FIELD_GET(PTP_TWOSTEP_CTRL_VLD, x)
0801
0802 #define PTP_TWOSTEP_CTRL_STAMP_TX BIT(9)
0803 #define PTP_TWOSTEP_CTRL_STAMP_TX_SET(x)\
0804 FIELD_PREP(PTP_TWOSTEP_CTRL_STAMP_TX, x)
0805 #define PTP_TWOSTEP_CTRL_STAMP_TX_GET(x)\
0806 FIELD_GET(PTP_TWOSTEP_CTRL_STAMP_TX, x)
0807
0808 #define PTP_TWOSTEP_CTRL_STAMP_PORT GENMASK(8, 1)
0809 #define PTP_TWOSTEP_CTRL_STAMP_PORT_SET(x)\
0810 FIELD_PREP(PTP_TWOSTEP_CTRL_STAMP_PORT, x)
0811 #define PTP_TWOSTEP_CTRL_STAMP_PORT_GET(x)\
0812 FIELD_GET(PTP_TWOSTEP_CTRL_STAMP_PORT, x)
0813
0814 #define PTP_TWOSTEP_CTRL_OVFL BIT(0)
0815 #define PTP_TWOSTEP_CTRL_OVFL_SET(x)\
0816 FIELD_PREP(PTP_TWOSTEP_CTRL_OVFL, x)
0817 #define PTP_TWOSTEP_CTRL_OVFL_GET(x)\
0818 FIELD_GET(PTP_TWOSTEP_CTRL_OVFL, x)
0819
0820
0821 #define PTP_TWOSTEP_STAMP __REG(TARGET_PTP, 0, 1, 612, 0, 1, 12, 4, 0, 1, 4)
0822
0823 #define PTP_TWOSTEP_STAMP_STAMP_NSEC GENMASK(31, 2)
0824 #define PTP_TWOSTEP_STAMP_STAMP_NSEC_SET(x)\
0825 FIELD_PREP(PTP_TWOSTEP_STAMP_STAMP_NSEC, x)
0826 #define PTP_TWOSTEP_STAMP_STAMP_NSEC_GET(x)\
0827 FIELD_GET(PTP_TWOSTEP_STAMP_STAMP_NSEC, x)
0828
0829
0830 #define QS_XTR_GRP_CFG(r) __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 0, r, 2, 4)
0831
0832 #define QS_XTR_GRP_CFG_MODE GENMASK(3, 2)
0833 #define QS_XTR_GRP_CFG_MODE_SET(x)\
0834 FIELD_PREP(QS_XTR_GRP_CFG_MODE, x)
0835 #define QS_XTR_GRP_CFG_MODE_GET(x)\
0836 FIELD_GET(QS_XTR_GRP_CFG_MODE, x)
0837
0838 #define QS_XTR_GRP_CFG_BYTE_SWAP BIT(0)
0839 #define QS_XTR_GRP_CFG_BYTE_SWAP_SET(x)\
0840 FIELD_PREP(QS_XTR_GRP_CFG_BYTE_SWAP, x)
0841 #define QS_XTR_GRP_CFG_BYTE_SWAP_GET(x)\
0842 FIELD_GET(QS_XTR_GRP_CFG_BYTE_SWAP, x)
0843
0844
0845 #define QS_XTR_RD(r) __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 8, r, 2, 4)
0846
0847
0848 #define QS_XTR_FLUSH __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 24, 0, 1, 4)
0849
0850
0851 #define QS_XTR_DATA_PRESENT __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 28, 0, 1, 4)
0852
0853
0854 #define QS_INJ_GRP_CFG(r) __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 0, r, 2, 4)
0855
0856 #define QS_INJ_GRP_CFG_MODE GENMASK(3, 2)
0857 #define QS_INJ_GRP_CFG_MODE_SET(x)\
0858 FIELD_PREP(QS_INJ_GRP_CFG_MODE, x)
0859 #define QS_INJ_GRP_CFG_MODE_GET(x)\
0860 FIELD_GET(QS_INJ_GRP_CFG_MODE, x)
0861
0862 #define QS_INJ_GRP_CFG_BYTE_SWAP BIT(0)
0863 #define QS_INJ_GRP_CFG_BYTE_SWAP_SET(x)\
0864 FIELD_PREP(QS_INJ_GRP_CFG_BYTE_SWAP, x)
0865 #define QS_INJ_GRP_CFG_BYTE_SWAP_GET(x)\
0866 FIELD_GET(QS_INJ_GRP_CFG_BYTE_SWAP, x)
0867
0868
0869 #define QS_INJ_WR(r) __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 8, r, 2, 4)
0870
0871
0872 #define QS_INJ_CTRL(r) __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 16, r, 2, 4)
0873
0874 #define QS_INJ_CTRL_GAP_SIZE GENMASK(24, 21)
0875 #define QS_INJ_CTRL_GAP_SIZE_SET(x)\
0876 FIELD_PREP(QS_INJ_CTRL_GAP_SIZE, x)
0877 #define QS_INJ_CTRL_GAP_SIZE_GET(x)\
0878 FIELD_GET(QS_INJ_CTRL_GAP_SIZE, x)
0879
0880 #define QS_INJ_CTRL_EOF BIT(19)
0881 #define QS_INJ_CTRL_EOF_SET(x)\
0882 FIELD_PREP(QS_INJ_CTRL_EOF, x)
0883 #define QS_INJ_CTRL_EOF_GET(x)\
0884 FIELD_GET(QS_INJ_CTRL_EOF, x)
0885
0886 #define QS_INJ_CTRL_SOF BIT(18)
0887 #define QS_INJ_CTRL_SOF_SET(x)\
0888 FIELD_PREP(QS_INJ_CTRL_SOF, x)
0889 #define QS_INJ_CTRL_SOF_GET(x)\
0890 FIELD_GET(QS_INJ_CTRL_SOF, x)
0891
0892 #define QS_INJ_CTRL_VLD_BYTES GENMASK(17, 16)
0893 #define QS_INJ_CTRL_VLD_BYTES_SET(x)\
0894 FIELD_PREP(QS_INJ_CTRL_VLD_BYTES, x)
0895 #define QS_INJ_CTRL_VLD_BYTES_GET(x)\
0896 FIELD_GET(QS_INJ_CTRL_VLD_BYTES, x)
0897
0898
0899 #define QS_INJ_STATUS __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 24, 0, 1, 4)
0900
0901 #define QS_INJ_STATUS_WMARK_REACHED GENMASK(5, 4)
0902 #define QS_INJ_STATUS_WMARK_REACHED_SET(x)\
0903 FIELD_PREP(QS_INJ_STATUS_WMARK_REACHED, x)
0904 #define QS_INJ_STATUS_WMARK_REACHED_GET(x)\
0905 FIELD_GET(QS_INJ_STATUS_WMARK_REACHED, x)
0906
0907 #define QS_INJ_STATUS_FIFO_RDY GENMASK(3, 2)
0908 #define QS_INJ_STATUS_FIFO_RDY_SET(x)\
0909 FIELD_PREP(QS_INJ_STATUS_FIFO_RDY, x)
0910 #define QS_INJ_STATUS_FIFO_RDY_GET(x)\
0911 FIELD_GET(QS_INJ_STATUS_FIFO_RDY, x)
0912
0913
0914 #define QSYS_PORT_MODE(r) __REG(TARGET_QSYS, 0, 1, 28008, 0, 1, 216, 0, r, 10, 4)
0915
0916 #define QSYS_PORT_MODE_DEQUEUE_DIS BIT(1)
0917 #define QSYS_PORT_MODE_DEQUEUE_DIS_SET(x)\
0918 FIELD_PREP(QSYS_PORT_MODE_DEQUEUE_DIS, x)
0919 #define QSYS_PORT_MODE_DEQUEUE_DIS_GET(x)\
0920 FIELD_GET(QSYS_PORT_MODE_DEQUEUE_DIS, x)
0921
0922
0923 #define QSYS_SW_PORT_MODE(r) __REG(TARGET_QSYS, 0, 1, 28008, 0, 1, 216, 80, r, 9, 4)
0924
0925 #define QSYS_SW_PORT_MODE_PORT_ENA BIT(18)
0926 #define QSYS_SW_PORT_MODE_PORT_ENA_SET(x)\
0927 FIELD_PREP(QSYS_SW_PORT_MODE_PORT_ENA, x)
0928 #define QSYS_SW_PORT_MODE_PORT_ENA_GET(x)\
0929 FIELD_GET(QSYS_SW_PORT_MODE_PORT_ENA, x)
0930
0931 #define QSYS_SW_PORT_MODE_SCH_NEXT_CFG GENMASK(16, 14)
0932 #define QSYS_SW_PORT_MODE_SCH_NEXT_CFG_SET(x)\
0933 FIELD_PREP(QSYS_SW_PORT_MODE_SCH_NEXT_CFG, x)
0934 #define QSYS_SW_PORT_MODE_SCH_NEXT_CFG_GET(x)\
0935 FIELD_GET(QSYS_SW_PORT_MODE_SCH_NEXT_CFG, x)
0936
0937 #define QSYS_SW_PORT_MODE_INGRESS_DROP_MODE BIT(12)
0938 #define QSYS_SW_PORT_MODE_INGRESS_DROP_MODE_SET(x)\
0939 FIELD_PREP(QSYS_SW_PORT_MODE_INGRESS_DROP_MODE, x)
0940 #define QSYS_SW_PORT_MODE_INGRESS_DROP_MODE_GET(x)\
0941 FIELD_GET(QSYS_SW_PORT_MODE_INGRESS_DROP_MODE, x)
0942
0943 #define QSYS_SW_PORT_MODE_TX_PFC_ENA GENMASK(11, 4)
0944 #define QSYS_SW_PORT_MODE_TX_PFC_ENA_SET(x)\
0945 FIELD_PREP(QSYS_SW_PORT_MODE_TX_PFC_ENA, x)
0946 #define QSYS_SW_PORT_MODE_TX_PFC_ENA_GET(x)\
0947 FIELD_GET(QSYS_SW_PORT_MODE_TX_PFC_ENA, x)
0948
0949 #define QSYS_SW_PORT_MODE_AGING_MODE GENMASK(1, 0)
0950 #define QSYS_SW_PORT_MODE_AGING_MODE_SET(x)\
0951 FIELD_PREP(QSYS_SW_PORT_MODE_AGING_MODE, x)
0952 #define QSYS_SW_PORT_MODE_AGING_MODE_GET(x)\
0953 FIELD_GET(QSYS_SW_PORT_MODE_AGING_MODE, x)
0954
0955
0956 #define QSYS_SW_STATUS(r) __REG(TARGET_QSYS, 0, 1, 28008, 0, 1, 216, 164, r, 9, 4)
0957
0958 #define QSYS_SW_STATUS_EQ_AVAIL GENMASK(7, 0)
0959 #define QSYS_SW_STATUS_EQ_AVAIL_SET(x)\
0960 FIELD_PREP(QSYS_SW_STATUS_EQ_AVAIL, x)
0961 #define QSYS_SW_STATUS_EQ_AVAIL_GET(x)\
0962 FIELD_GET(QSYS_SW_STATUS_EQ_AVAIL, x)
0963
0964
0965 #define QSYS_CPU_GROUP_MAP __REG(TARGET_QSYS, 0, 1, 28008, 0, 1, 216, 204, 0, 1, 4)
0966
0967
0968 #define QSYS_RES_CFG(g) __REG(TARGET_QSYS, 0, 1, 32768, g, 1024, 8, 0, 0, 1, 4)
0969
0970
0971 #define REW_PORT_VLAN_CFG(g) __REG(TARGET_REW, 0, 1, 0, g, 10, 128, 0, 0, 1, 4)
0972
0973 #define REW_PORT_VLAN_CFG_PORT_TPID GENMASK(31, 16)
0974 #define REW_PORT_VLAN_CFG_PORT_TPID_SET(x)\
0975 FIELD_PREP(REW_PORT_VLAN_CFG_PORT_TPID, x)
0976 #define REW_PORT_VLAN_CFG_PORT_TPID_GET(x)\
0977 FIELD_GET(REW_PORT_VLAN_CFG_PORT_TPID, x)
0978
0979 #define REW_PORT_VLAN_CFG_PORT_VID GENMASK(11, 0)
0980 #define REW_PORT_VLAN_CFG_PORT_VID_SET(x)\
0981 FIELD_PREP(REW_PORT_VLAN_CFG_PORT_VID, x)
0982 #define REW_PORT_VLAN_CFG_PORT_VID_GET(x)\
0983 FIELD_GET(REW_PORT_VLAN_CFG_PORT_VID, x)
0984
0985
0986 #define REW_TAG_CFG(g) __REG(TARGET_REW, 0, 1, 0, g, 10, 128, 4, 0, 1, 4)
0987
0988 #define REW_TAG_CFG_TAG_CFG GENMASK(8, 7)
0989 #define REW_TAG_CFG_TAG_CFG_SET(x)\
0990 FIELD_PREP(REW_TAG_CFG_TAG_CFG, x)
0991 #define REW_TAG_CFG_TAG_CFG_GET(x)\
0992 FIELD_GET(REW_TAG_CFG_TAG_CFG, x)
0993
0994 #define REW_TAG_CFG_TAG_TPID_CFG GENMASK(6, 5)
0995 #define REW_TAG_CFG_TAG_TPID_CFG_SET(x)\
0996 FIELD_PREP(REW_TAG_CFG_TAG_TPID_CFG, x)
0997 #define REW_TAG_CFG_TAG_TPID_CFG_GET(x)\
0998 FIELD_GET(REW_TAG_CFG_TAG_TPID_CFG, x)
0999
1000
1001 #define REW_PORT_CFG(g) __REG(TARGET_REW, 0, 1, 0, g, 10, 128, 8, 0, 1, 4)
1002
1003 #define REW_PORT_CFG_NO_REWRITE BIT(0)
1004 #define REW_PORT_CFG_NO_REWRITE_SET(x)\
1005 FIELD_PREP(REW_PORT_CFG_NO_REWRITE, x)
1006 #define REW_PORT_CFG_NO_REWRITE_GET(x)\
1007 FIELD_GET(REW_PORT_CFG_NO_REWRITE, x)
1008
1009
1010 #define SYS_RESET_CFG __REG(TARGET_SYS, 0, 1, 4128, 0, 1, 168, 0, 0, 1, 4)
1011
1012 #define SYS_RESET_CFG_CORE_ENA BIT(0)
1013 #define SYS_RESET_CFG_CORE_ENA_SET(x)\
1014 FIELD_PREP(SYS_RESET_CFG_CORE_ENA, x)
1015 #define SYS_RESET_CFG_CORE_ENA_GET(x)\
1016 FIELD_GET(SYS_RESET_CFG_CORE_ENA, x)
1017
1018
1019 #define SYS_PORT_MODE(r) __REG(TARGET_SYS, 0, 1, 4128, 0, 1, 168, 44, r, 10, 4)
1020
1021 #define SYS_PORT_MODE_INCL_INJ_HDR GENMASK(5, 4)
1022 #define SYS_PORT_MODE_INCL_INJ_HDR_SET(x)\
1023 FIELD_PREP(SYS_PORT_MODE_INCL_INJ_HDR, x)
1024 #define SYS_PORT_MODE_INCL_INJ_HDR_GET(x)\
1025 FIELD_GET(SYS_PORT_MODE_INCL_INJ_HDR, x)
1026
1027 #define SYS_PORT_MODE_INCL_XTR_HDR GENMASK(3, 2)
1028 #define SYS_PORT_MODE_INCL_XTR_HDR_SET(x)\
1029 FIELD_PREP(SYS_PORT_MODE_INCL_XTR_HDR, x)
1030 #define SYS_PORT_MODE_INCL_XTR_HDR_GET(x)\
1031 FIELD_GET(SYS_PORT_MODE_INCL_XTR_HDR, x)
1032
1033
1034 #define SYS_FRONT_PORT_MODE(r) __REG(TARGET_SYS, 0, 1, 4128, 0, 1, 168, 84, r, 8, 4)
1035
1036 #define SYS_FRONT_PORT_MODE_HDX_MODE BIT(1)
1037 #define SYS_FRONT_PORT_MODE_HDX_MODE_SET(x)\
1038 FIELD_PREP(SYS_FRONT_PORT_MODE_HDX_MODE, x)
1039 #define SYS_FRONT_PORT_MODE_HDX_MODE_GET(x)\
1040 FIELD_GET(SYS_FRONT_PORT_MODE_HDX_MODE, x)
1041
1042
1043 #define SYS_FRM_AGING __REG(TARGET_SYS, 0, 1, 4128, 0, 1, 168, 116, 0, 1, 4)
1044
1045 #define SYS_FRM_AGING_AGE_TX_ENA BIT(20)
1046 #define SYS_FRM_AGING_AGE_TX_ENA_SET(x)\
1047 FIELD_PREP(SYS_FRM_AGING_AGE_TX_ENA, x)
1048 #define SYS_FRM_AGING_AGE_TX_ENA_GET(x)\
1049 FIELD_GET(SYS_FRM_AGING_AGE_TX_ENA, x)
1050
1051
1052 #define SYS_STAT_CFG __REG(TARGET_SYS, 0, 1, 4128, 0, 1, 168, 120, 0, 1, 4)
1053
1054 #define SYS_STAT_CFG_STAT_VIEW GENMASK(9, 0)
1055 #define SYS_STAT_CFG_STAT_VIEW_SET(x)\
1056 FIELD_PREP(SYS_STAT_CFG_STAT_VIEW, x)
1057 #define SYS_STAT_CFG_STAT_VIEW_GET(x)\
1058 FIELD_GET(SYS_STAT_CFG_STAT_VIEW, x)
1059
1060
1061 #define SYS_PAUSE_CFG(r) __REG(TARGET_SYS, 0, 1, 4296, 0, 1, 112, 0, r, 9, 4)
1062
1063 #define SYS_PAUSE_CFG_PAUSE_START GENMASK(18, 10)
1064 #define SYS_PAUSE_CFG_PAUSE_START_SET(x)\
1065 FIELD_PREP(SYS_PAUSE_CFG_PAUSE_START, x)
1066 #define SYS_PAUSE_CFG_PAUSE_START_GET(x)\
1067 FIELD_GET(SYS_PAUSE_CFG_PAUSE_START, x)
1068
1069 #define SYS_PAUSE_CFG_PAUSE_STOP GENMASK(9, 1)
1070 #define SYS_PAUSE_CFG_PAUSE_STOP_SET(x)\
1071 FIELD_PREP(SYS_PAUSE_CFG_PAUSE_STOP, x)
1072 #define SYS_PAUSE_CFG_PAUSE_STOP_GET(x)\
1073 FIELD_GET(SYS_PAUSE_CFG_PAUSE_STOP, x)
1074
1075 #define SYS_PAUSE_CFG_PAUSE_ENA BIT(0)
1076 #define SYS_PAUSE_CFG_PAUSE_ENA_SET(x)\
1077 FIELD_PREP(SYS_PAUSE_CFG_PAUSE_ENA, x)
1078 #define SYS_PAUSE_CFG_PAUSE_ENA_GET(x)\
1079 FIELD_GET(SYS_PAUSE_CFG_PAUSE_ENA, x)
1080
1081
1082 #define SYS_ATOP(r) __REG(TARGET_SYS, 0, 1, 4296, 0, 1, 112, 40, r, 9, 4)
1083
1084
1085 #define SYS_ATOP_TOT_CFG __REG(TARGET_SYS, 0, 1, 4296, 0, 1, 112, 76, 0, 1, 4)
1086
1087
1088 #define SYS_MAC_FC_CFG(r) __REG(TARGET_SYS, 0, 1, 4296, 0, 1, 112, 80, r, 8, 4)
1089
1090 #define SYS_MAC_FC_CFG_FC_LINK_SPEED GENMASK(27, 26)
1091 #define SYS_MAC_FC_CFG_FC_LINK_SPEED_SET(x)\
1092 FIELD_PREP(SYS_MAC_FC_CFG_FC_LINK_SPEED, x)
1093 #define SYS_MAC_FC_CFG_FC_LINK_SPEED_GET(x)\
1094 FIELD_GET(SYS_MAC_FC_CFG_FC_LINK_SPEED, x)
1095
1096 #define SYS_MAC_FC_CFG_FC_LATENCY_CFG GENMASK(25, 20)
1097 #define SYS_MAC_FC_CFG_FC_LATENCY_CFG_SET(x)\
1098 FIELD_PREP(SYS_MAC_FC_CFG_FC_LATENCY_CFG, x)
1099 #define SYS_MAC_FC_CFG_FC_LATENCY_CFG_GET(x)\
1100 FIELD_GET(SYS_MAC_FC_CFG_FC_LATENCY_CFG, x)
1101
1102 #define SYS_MAC_FC_CFG_ZERO_PAUSE_ENA BIT(18)
1103 #define SYS_MAC_FC_CFG_ZERO_PAUSE_ENA_SET(x)\
1104 FIELD_PREP(SYS_MAC_FC_CFG_ZERO_PAUSE_ENA, x)
1105 #define SYS_MAC_FC_CFG_ZERO_PAUSE_ENA_GET(x)\
1106 FIELD_GET(SYS_MAC_FC_CFG_ZERO_PAUSE_ENA, x)
1107
1108 #define SYS_MAC_FC_CFG_TX_FC_ENA BIT(17)
1109 #define SYS_MAC_FC_CFG_TX_FC_ENA_SET(x)\
1110 FIELD_PREP(SYS_MAC_FC_CFG_TX_FC_ENA, x)
1111 #define SYS_MAC_FC_CFG_TX_FC_ENA_GET(x)\
1112 FIELD_GET(SYS_MAC_FC_CFG_TX_FC_ENA, x)
1113
1114 #define SYS_MAC_FC_CFG_RX_FC_ENA BIT(16)
1115 #define SYS_MAC_FC_CFG_RX_FC_ENA_SET(x)\
1116 FIELD_PREP(SYS_MAC_FC_CFG_RX_FC_ENA, x)
1117 #define SYS_MAC_FC_CFG_RX_FC_ENA_GET(x)\
1118 FIELD_GET(SYS_MAC_FC_CFG_RX_FC_ENA, x)
1119
1120 #define SYS_MAC_FC_CFG_PAUSE_VAL_CFG GENMASK(15, 0)
1121 #define SYS_MAC_FC_CFG_PAUSE_VAL_CFG_SET(x)\
1122 FIELD_PREP(SYS_MAC_FC_CFG_PAUSE_VAL_CFG, x)
1123 #define SYS_MAC_FC_CFG_PAUSE_VAL_CFG_GET(x)\
1124 FIELD_GET(SYS_MAC_FC_CFG_PAUSE_VAL_CFG, x)
1125
1126
1127 #define SYS_CNT(g) __REG(TARGET_SYS, 0, 1, 0, g, 896, 4, 0, 0, 1, 4)
1128
1129
1130 #define SYS_RAM_INIT __REG(TARGET_SYS, 0, 1, 4432, 0, 1, 4, 0, 0, 1, 4)
1131
1132 #define SYS_RAM_INIT_RAM_INIT BIT(1)
1133 #define SYS_RAM_INIT_RAM_INIT_SET(x)\
1134 FIELD_PREP(SYS_RAM_INIT_RAM_INIT, x)
1135 #define SYS_RAM_INIT_RAM_INIT_GET(x)\
1136 FIELD_GET(SYS_RAM_INIT_RAM_INIT, x)
1137
1138 #endif
