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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Microchip ENCX24J600 ethernet driver
0004  *
0005  * Copyright (C) 2015 Gridpoint
0006  * Author: Jon Ringle <jringle@gridpoint.com>
0007  */
0008 
0009 #include <linux/device.h>
0010 #include <linux/errno.h>
0011 #include <linux/etherdevice.h>
0012 #include <linux/ethtool.h>
0013 #include <linux/interrupt.h>
0014 #include <linux/kernel.h>
0015 #include <linux/module.h>
0016 #include <linux/netdevice.h>
0017 #include <linux/regmap.h>
0018 #include <linux/skbuff.h>
0019 #include <linux/spi/spi.h>
0020 
0021 #include "encx24j600_hw.h"
0022 
0023 #define DRV_NAME    "encx24j600"
0024 #define DRV_VERSION "1.0"
0025 
0026 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
0027 static int debug = -1;
0028 module_param(debug, int, 0000);
0029 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
0030 
0031 /* SRAM memory layout:
0032  *
0033  * 0x0000-0x05ff TX buffers  1.5KB  (1*1536) reside in the GP area in SRAM
0034  * 0x0600-0x5fff RX buffers 22.5KB (15*1536) reside in the RX area in SRAM
0035  */
0036 #define ENC_TX_BUF_START 0x0000U
0037 #define ENC_RX_BUF_START 0x0600U
0038 #define ENC_RX_BUF_END   0x5fffU
0039 #define ENC_SRAM_SIZE    0x6000U
0040 
0041 enum {
0042     RXFILTER_NORMAL,
0043     RXFILTER_MULTI,
0044     RXFILTER_PROMISC
0045 };
0046 
0047 struct encx24j600_priv {
0048     struct net_device        *ndev;
0049     struct mutex              lock; /* device access lock */
0050     struct encx24j600_context ctx;
0051     struct sk_buff           *tx_skb;
0052     struct task_struct       *kworker_task;
0053     struct kthread_worker     kworker;
0054     struct kthread_work       tx_work;
0055     struct kthread_work       setrx_work;
0056     u16                       next_packet;
0057     bool                      hw_enabled;
0058     bool                      full_duplex;
0059     bool                      autoneg;
0060     u16                       speed;
0061     int                       rxfilter;
0062     u32                       msg_enable;
0063 };
0064 
0065 static void dump_packet(const char *msg, int len, const char *data)
0066 {
0067     pr_debug(DRV_NAME ": %s - packet len:%d\n", msg, len);
0068     print_hex_dump_bytes("pk data: ", DUMP_PREFIX_OFFSET, data, len);
0069 }
0070 
0071 static void encx24j600_dump_rsv(struct encx24j600_priv *priv, const char *msg,
0072                 struct rsv *rsv)
0073 {
0074     struct net_device *dev = priv->ndev;
0075 
0076     netdev_info(dev, "RX packet Len:%d\n", rsv->len);
0077     netdev_dbg(dev, "%s - NextPk: 0x%04x\n", msg,
0078            rsv->next_packet);
0079     netdev_dbg(dev, "RxOK: %d, DribbleNibble: %d\n",
0080            RSV_GETBIT(rsv->rxstat, RSV_RXOK),
0081            RSV_GETBIT(rsv->rxstat, RSV_DRIBBLENIBBLE));
0082     netdev_dbg(dev, "CRCErr:%d, LenChkErr: %d, LenOutOfRange: %d\n",
0083            RSV_GETBIT(rsv->rxstat, RSV_CRCERROR),
0084            RSV_GETBIT(rsv->rxstat, RSV_LENCHECKERR),
0085            RSV_GETBIT(rsv->rxstat, RSV_LENOUTOFRANGE));
0086     netdev_dbg(dev, "Multicast: %d, Broadcast: %d, LongDropEvent: %d, CarrierEvent: %d\n",
0087            RSV_GETBIT(rsv->rxstat, RSV_RXMULTICAST),
0088            RSV_GETBIT(rsv->rxstat, RSV_RXBROADCAST),
0089            RSV_GETBIT(rsv->rxstat, RSV_RXLONGEVDROPEV),
0090            RSV_GETBIT(rsv->rxstat, RSV_CARRIEREV));
0091     netdev_dbg(dev, "ControlFrame: %d, PauseFrame: %d, UnknownOp: %d, VLanTagFrame: %d\n",
0092            RSV_GETBIT(rsv->rxstat, RSV_RXCONTROLFRAME),
0093            RSV_GETBIT(rsv->rxstat, RSV_RXPAUSEFRAME),
0094            RSV_GETBIT(rsv->rxstat, RSV_RXUNKNOWNOPCODE),
0095            RSV_GETBIT(rsv->rxstat, RSV_RXTYPEVLAN));
0096 }
0097 
0098 static u16 encx24j600_read_reg(struct encx24j600_priv *priv, u8 reg)
0099 {
0100     struct net_device *dev = priv->ndev;
0101     unsigned int val = 0;
0102     int ret = regmap_read(priv->ctx.regmap, reg, &val);
0103 
0104     if (unlikely(ret))
0105         netif_err(priv, drv, dev, "%s: error %d reading reg %02x\n",
0106               __func__, ret, reg);
0107     return val;
0108 }
0109 
0110 static void encx24j600_write_reg(struct encx24j600_priv *priv, u8 reg, u16 val)
0111 {
0112     struct net_device *dev = priv->ndev;
0113     int ret = regmap_write(priv->ctx.regmap, reg, val);
0114 
0115     if (unlikely(ret))
0116         netif_err(priv, drv, dev, "%s: error %d writing reg %02x=%04x\n",
0117               __func__, ret, reg, val);
0118 }
0119 
0120 static void encx24j600_update_reg(struct encx24j600_priv *priv, u8 reg,
0121                   u16 mask, u16 val)
0122 {
0123     struct net_device *dev = priv->ndev;
0124     int ret = regmap_update_bits(priv->ctx.regmap, reg, mask, val);
0125 
0126     if (unlikely(ret))
0127         netif_err(priv, drv, dev, "%s: error %d updating reg %02x=%04x~%04x\n",
0128               __func__, ret, reg, val, mask);
0129 }
0130 
0131 static u16 encx24j600_read_phy(struct encx24j600_priv *priv, u8 reg)
0132 {
0133     struct net_device *dev = priv->ndev;
0134     unsigned int val = 0;
0135     int ret = regmap_read(priv->ctx.phymap, reg, &val);
0136 
0137     if (unlikely(ret))
0138         netif_err(priv, drv, dev, "%s: error %d reading %02x\n",
0139               __func__, ret, reg);
0140     return val;
0141 }
0142 
0143 static void encx24j600_write_phy(struct encx24j600_priv *priv, u8 reg, u16 val)
0144 {
0145     struct net_device *dev = priv->ndev;
0146     int ret = regmap_write(priv->ctx.phymap, reg, val);
0147 
0148     if (unlikely(ret))
0149         netif_err(priv, drv, dev, "%s: error %d writing reg %02x=%04x\n",
0150               __func__, ret, reg, val);
0151 }
0152 
0153 static void encx24j600_clr_bits(struct encx24j600_priv *priv, u8 reg, u16 mask)
0154 {
0155     encx24j600_update_reg(priv, reg, mask, 0);
0156 }
0157 
0158 static void encx24j600_set_bits(struct encx24j600_priv *priv, u8 reg, u16 mask)
0159 {
0160     encx24j600_update_reg(priv, reg, mask, mask);
0161 }
0162 
0163 static void encx24j600_cmd(struct encx24j600_priv *priv, u8 cmd)
0164 {
0165     struct net_device *dev = priv->ndev;
0166     int ret = regmap_write(priv->ctx.regmap, cmd, 0);
0167 
0168     if (unlikely(ret))
0169         netif_err(priv, drv, dev, "%s: error %d with cmd %02x\n",
0170               __func__, ret, cmd);
0171 }
0172 
0173 static int encx24j600_raw_read(struct encx24j600_priv *priv, u8 reg, u8 *data,
0174                    size_t count)
0175 {
0176     int ret;
0177 
0178     mutex_lock(&priv->ctx.mutex);
0179     ret = regmap_encx24j600_spi_read(&priv->ctx, reg, data, count);
0180     mutex_unlock(&priv->ctx.mutex);
0181 
0182     return ret;
0183 }
0184 
0185 static int encx24j600_raw_write(struct encx24j600_priv *priv, u8 reg,
0186                 const u8 *data, size_t count)
0187 {
0188     int ret;
0189 
0190     mutex_lock(&priv->ctx.mutex);
0191     ret = regmap_encx24j600_spi_write(&priv->ctx, reg, data, count);
0192     mutex_unlock(&priv->ctx.mutex);
0193 
0194     return ret;
0195 }
0196 
0197 static void encx24j600_update_phcon1(struct encx24j600_priv *priv)
0198 {
0199     u16 phcon1 = encx24j600_read_phy(priv, PHCON1);
0200 
0201     if (priv->autoneg == AUTONEG_ENABLE) {
0202         phcon1 |= ANEN | RENEG;
0203     } else {
0204         phcon1 &= ~ANEN;
0205         if (priv->speed == SPEED_100)
0206             phcon1 |= SPD100;
0207         else
0208             phcon1 &= ~SPD100;
0209 
0210         if (priv->full_duplex)
0211             phcon1 |= PFULDPX;
0212         else
0213             phcon1 &= ~PFULDPX;
0214     }
0215     encx24j600_write_phy(priv, PHCON1, phcon1);
0216 }
0217 
0218 /* Waits for autonegotiation to complete. */
0219 static int encx24j600_wait_for_autoneg(struct encx24j600_priv *priv)
0220 {
0221     struct net_device *dev = priv->ndev;
0222     unsigned long timeout = jiffies + msecs_to_jiffies(2000);
0223     u16 phstat1;
0224     u16 estat;
0225 
0226     phstat1 = encx24j600_read_phy(priv, PHSTAT1);
0227     while ((phstat1 & ANDONE) == 0) {
0228         if (time_after(jiffies, timeout)) {
0229             u16 phstat3;
0230 
0231             netif_notice(priv, drv, dev, "timeout waiting for autoneg done\n");
0232 
0233             priv->autoneg = AUTONEG_DISABLE;
0234             phstat3 = encx24j600_read_phy(priv, PHSTAT3);
0235             priv->speed = (phstat3 & PHY3SPD100)
0236                       ? SPEED_100 : SPEED_10;
0237             priv->full_duplex = (phstat3 & PHY3DPX) ? 1 : 0;
0238             encx24j600_update_phcon1(priv);
0239             netif_notice(priv, drv, dev, "Using parallel detection: %s/%s",
0240                      priv->speed == SPEED_100 ? "100" : "10",
0241                      priv->full_duplex ? "Full" : "Half");
0242 
0243             return -ETIMEDOUT;
0244         }
0245         cpu_relax();
0246         phstat1 = encx24j600_read_phy(priv, PHSTAT1);
0247     }
0248 
0249     estat = encx24j600_read_reg(priv, ESTAT);
0250     if (estat & PHYDPX) {
0251         encx24j600_set_bits(priv, MACON2, FULDPX);
0252         encx24j600_write_reg(priv, MABBIPG, 0x15);
0253     } else {
0254         encx24j600_clr_bits(priv, MACON2, FULDPX);
0255         encx24j600_write_reg(priv, MABBIPG, 0x12);
0256         /* Max retransmittions attempt  */
0257         encx24j600_write_reg(priv, MACLCON, 0x370f);
0258     }
0259 
0260     return 0;
0261 }
0262 
0263 /* Access the PHY to determine link status */
0264 static void encx24j600_check_link_status(struct encx24j600_priv *priv)
0265 {
0266     struct net_device *dev = priv->ndev;
0267     u16 estat;
0268 
0269     estat = encx24j600_read_reg(priv, ESTAT);
0270 
0271     if (estat & PHYLNK) {
0272         if (priv->autoneg == AUTONEG_ENABLE)
0273             encx24j600_wait_for_autoneg(priv);
0274 
0275         netif_carrier_on(dev);
0276         netif_info(priv, ifup, dev, "link up\n");
0277     } else {
0278         netif_info(priv, ifdown, dev, "link down\n");
0279 
0280         /* Re-enable autoneg since we won't know what we might be
0281          * connected to when the link is brought back up again.
0282          */
0283         priv->autoneg  = AUTONEG_ENABLE;
0284         priv->full_duplex = true;
0285         priv->speed = SPEED_100;
0286         netif_carrier_off(dev);
0287     }
0288 }
0289 
0290 static void encx24j600_int_link_handler(struct encx24j600_priv *priv)
0291 {
0292     struct net_device *dev = priv->ndev;
0293 
0294     netif_dbg(priv, intr, dev, "%s", __func__);
0295     encx24j600_check_link_status(priv);
0296     encx24j600_clr_bits(priv, EIR, LINKIF);
0297 }
0298 
0299 static void encx24j600_tx_complete(struct encx24j600_priv *priv, bool err)
0300 {
0301     struct net_device *dev = priv->ndev;
0302 
0303     if (!priv->tx_skb) {
0304         BUG();
0305         return;
0306     }
0307 
0308     mutex_lock(&priv->lock);
0309 
0310     if (err)
0311         dev->stats.tx_errors++;
0312     else
0313         dev->stats.tx_packets++;
0314 
0315     dev->stats.tx_bytes += priv->tx_skb->len;
0316 
0317     encx24j600_clr_bits(priv, EIR, TXIF | TXABTIF);
0318 
0319     netif_dbg(priv, tx_done, dev, "TX Done%s\n", err ? ": Err" : "");
0320 
0321     dev_kfree_skb(priv->tx_skb);
0322     priv->tx_skb = NULL;
0323 
0324     netif_wake_queue(dev);
0325 
0326     mutex_unlock(&priv->lock);
0327 }
0328 
0329 static int encx24j600_receive_packet(struct encx24j600_priv *priv,
0330                      struct rsv *rsv)
0331 {
0332     struct net_device *dev = priv->ndev;
0333     struct sk_buff *skb = netdev_alloc_skb(dev, rsv->len + NET_IP_ALIGN);
0334 
0335     if (!skb) {
0336         pr_err_ratelimited("RX: OOM: packet dropped\n");
0337         dev->stats.rx_dropped++;
0338         return -ENOMEM;
0339     }
0340     skb_reserve(skb, NET_IP_ALIGN);
0341     encx24j600_raw_read(priv, RRXDATA, skb_put(skb, rsv->len), rsv->len);
0342 
0343     if (netif_msg_pktdata(priv))
0344         dump_packet("RX", skb->len, skb->data);
0345 
0346     skb->dev = dev;
0347     skb->protocol = eth_type_trans(skb, dev);
0348     skb->ip_summed = CHECKSUM_COMPLETE;
0349 
0350     /* Maintain stats */
0351     dev->stats.rx_packets++;
0352     dev->stats.rx_bytes += rsv->len;
0353 
0354     netif_rx(skb);
0355 
0356     return 0;
0357 }
0358 
0359 static void encx24j600_rx_packets(struct encx24j600_priv *priv, u8 packet_count)
0360 {
0361     struct net_device *dev = priv->ndev;
0362 
0363     while (packet_count--) {
0364         struct rsv rsv;
0365         u16 newrxtail;
0366 
0367         encx24j600_write_reg(priv, ERXRDPT, priv->next_packet);
0368         encx24j600_raw_read(priv, RRXDATA, (u8 *)&rsv, sizeof(rsv));
0369 
0370         if (netif_msg_rx_status(priv))
0371             encx24j600_dump_rsv(priv, __func__, &rsv);
0372 
0373         if (!RSV_GETBIT(rsv.rxstat, RSV_RXOK) ||
0374             (rsv.len > MAX_FRAMELEN)) {
0375             netif_err(priv, rx_err, dev, "RX Error %04x\n",
0376                   rsv.rxstat);
0377             dev->stats.rx_errors++;
0378 
0379             if (RSV_GETBIT(rsv.rxstat, RSV_CRCERROR))
0380                 dev->stats.rx_crc_errors++;
0381             if (RSV_GETBIT(rsv.rxstat, RSV_LENCHECKERR))
0382                 dev->stats.rx_frame_errors++;
0383             if (rsv.len > MAX_FRAMELEN)
0384                 dev->stats.rx_over_errors++;
0385         } else {
0386             encx24j600_receive_packet(priv, &rsv);
0387         }
0388 
0389         priv->next_packet = rsv.next_packet;
0390 
0391         newrxtail = priv->next_packet - 2;
0392         if (newrxtail == ENC_RX_BUF_START)
0393             newrxtail = SRAM_SIZE - 2;
0394 
0395         encx24j600_cmd(priv, SETPKTDEC);
0396         encx24j600_write_reg(priv, ERXTAIL, newrxtail);
0397     }
0398 }
0399 
0400 static irqreturn_t encx24j600_isr(int irq, void *dev_id)
0401 {
0402     struct encx24j600_priv *priv = dev_id;
0403     struct net_device *dev = priv->ndev;
0404     int eir;
0405 
0406     /* Clear interrupts */
0407     encx24j600_cmd(priv, CLREIE);
0408 
0409     eir = encx24j600_read_reg(priv, EIR);
0410 
0411     if (eir & LINKIF)
0412         encx24j600_int_link_handler(priv);
0413 
0414     if (eir & TXIF)
0415         encx24j600_tx_complete(priv, false);
0416 
0417     if (eir & TXABTIF)
0418         encx24j600_tx_complete(priv, true);
0419 
0420     if (eir & RXABTIF) {
0421         if (eir & PCFULIF) {
0422             /* Packet counter is full */
0423             netif_err(priv, rx_err, dev, "Packet counter full\n");
0424         }
0425         dev->stats.rx_dropped++;
0426         encx24j600_clr_bits(priv, EIR, RXABTIF);
0427     }
0428 
0429     if (eir & PKTIF) {
0430         u8 packet_count;
0431 
0432         mutex_lock(&priv->lock);
0433 
0434         packet_count = encx24j600_read_reg(priv, ESTAT) & 0xff;
0435         while (packet_count) {
0436             encx24j600_rx_packets(priv, packet_count);
0437             packet_count = encx24j600_read_reg(priv, ESTAT) & 0xff;
0438         }
0439 
0440         mutex_unlock(&priv->lock);
0441     }
0442 
0443     /* Enable interrupts */
0444     encx24j600_cmd(priv, SETEIE);
0445 
0446     return IRQ_HANDLED;
0447 }
0448 
0449 static int encx24j600_soft_reset(struct encx24j600_priv *priv)
0450 {
0451     int ret = 0;
0452     int timeout;
0453     u16 eudast;
0454 
0455     /* Write and verify a test value to EUDAST */
0456     regcache_cache_bypass(priv->ctx.regmap, true);
0457     timeout = 10;
0458     do {
0459         encx24j600_write_reg(priv, EUDAST, EUDAST_TEST_VAL);
0460         eudast = encx24j600_read_reg(priv, EUDAST);
0461         usleep_range(25, 100);
0462     } while ((eudast != EUDAST_TEST_VAL) && --timeout);
0463     regcache_cache_bypass(priv->ctx.regmap, false);
0464 
0465     if (timeout == 0) {
0466         ret = -ETIMEDOUT;
0467         goto err_out;
0468     }
0469 
0470     /* Wait for CLKRDY to become set */
0471     timeout = 10;
0472     while (!(encx24j600_read_reg(priv, ESTAT) & CLKRDY) && --timeout)
0473         usleep_range(25, 100);
0474 
0475     if (timeout == 0) {
0476         ret = -ETIMEDOUT;
0477         goto err_out;
0478     }
0479 
0480     /* Issue a System Reset command */
0481     encx24j600_cmd(priv, SETETHRST);
0482     usleep_range(25, 100);
0483 
0484     /* Confirm that EUDAST has 0000h after system reset */
0485     if (encx24j600_read_reg(priv, EUDAST) != 0) {
0486         ret = -EINVAL;
0487         goto err_out;
0488     }
0489 
0490     /* Wait for PHY register and status bits to become available */
0491     usleep_range(256, 1000);
0492 
0493 err_out:
0494     return ret;
0495 }
0496 
0497 static int encx24j600_hw_reset(struct encx24j600_priv *priv)
0498 {
0499     int ret;
0500 
0501     mutex_lock(&priv->lock);
0502     ret = encx24j600_soft_reset(priv);
0503     mutex_unlock(&priv->lock);
0504 
0505     return ret;
0506 }
0507 
0508 static void encx24j600_reset_hw_tx(struct encx24j600_priv *priv)
0509 {
0510     encx24j600_set_bits(priv, ECON2, TXRST);
0511     encx24j600_clr_bits(priv, ECON2, TXRST);
0512 }
0513 
0514 static void encx24j600_hw_init_tx(struct encx24j600_priv *priv)
0515 {
0516     /* Reset TX */
0517     encx24j600_reset_hw_tx(priv);
0518 
0519     /* Clear the TXIF flag if were previously set */
0520     encx24j600_clr_bits(priv, EIR, TXIF | TXABTIF);
0521 
0522     /* Write the Tx Buffer pointer */
0523     encx24j600_write_reg(priv, EGPWRPT, ENC_TX_BUF_START);
0524 }
0525 
0526 static void encx24j600_hw_init_rx(struct encx24j600_priv *priv)
0527 {
0528     encx24j600_cmd(priv, DISABLERX);
0529 
0530     /* Set up RX packet start address in the SRAM */
0531     encx24j600_write_reg(priv, ERXST, ENC_RX_BUF_START);
0532 
0533     /* Preload the RX Data pointer to the beginning of the RX area */
0534     encx24j600_write_reg(priv, ERXRDPT, ENC_RX_BUF_START);
0535 
0536     priv->next_packet = ENC_RX_BUF_START;
0537 
0538     /* Set up RX end address in the SRAM */
0539     encx24j600_write_reg(priv, ERXTAIL, ENC_SRAM_SIZE - 2);
0540 
0541     /* Reset the  user data pointers    */
0542     encx24j600_write_reg(priv, EUDAST, ENC_SRAM_SIZE);
0543     encx24j600_write_reg(priv, EUDAND, ENC_SRAM_SIZE + 1);
0544 
0545     /* Set Max Frame length */
0546     encx24j600_write_reg(priv, MAMXFL, MAX_FRAMELEN);
0547 }
0548 
0549 static void encx24j600_dump_config(struct encx24j600_priv *priv,
0550                    const char *msg)
0551 {
0552     pr_info(DRV_NAME ": %s\n", msg);
0553 
0554     /* CHIP configuration */
0555     pr_info(DRV_NAME " ECON1:   %04X\n", encx24j600_read_reg(priv, ECON1));
0556     pr_info(DRV_NAME " ECON2:   %04X\n", encx24j600_read_reg(priv, ECON2));
0557     pr_info(DRV_NAME " ERXFCON: %04X\n", encx24j600_read_reg(priv,
0558                                  ERXFCON));
0559     pr_info(DRV_NAME " ESTAT:   %04X\n", encx24j600_read_reg(priv, ESTAT));
0560     pr_info(DRV_NAME " EIR:     %04X\n", encx24j600_read_reg(priv, EIR));
0561     pr_info(DRV_NAME " EIDLED:  %04X\n", encx24j600_read_reg(priv, EIDLED));
0562 
0563     /* MAC layer configuration */
0564     pr_info(DRV_NAME " MACON1:  %04X\n", encx24j600_read_reg(priv, MACON1));
0565     pr_info(DRV_NAME " MACON2:  %04X\n", encx24j600_read_reg(priv, MACON2));
0566     pr_info(DRV_NAME " MAIPG:   %04X\n", encx24j600_read_reg(priv, MAIPG));
0567     pr_info(DRV_NAME " MACLCON: %04X\n", encx24j600_read_reg(priv,
0568                                  MACLCON));
0569     pr_info(DRV_NAME " MABBIPG: %04X\n", encx24j600_read_reg(priv,
0570                                  MABBIPG));
0571 
0572     /* PHY configuation */
0573     pr_info(DRV_NAME " PHCON1:  %04X\n", encx24j600_read_phy(priv, PHCON1));
0574     pr_info(DRV_NAME " PHCON2:  %04X\n", encx24j600_read_phy(priv, PHCON2));
0575     pr_info(DRV_NAME " PHANA:   %04X\n", encx24j600_read_phy(priv, PHANA));
0576     pr_info(DRV_NAME " PHANLPA: %04X\n", encx24j600_read_phy(priv,
0577                                  PHANLPA));
0578     pr_info(DRV_NAME " PHANE:   %04X\n", encx24j600_read_phy(priv, PHANE));
0579     pr_info(DRV_NAME " PHSTAT1: %04X\n", encx24j600_read_phy(priv,
0580                                  PHSTAT1));
0581     pr_info(DRV_NAME " PHSTAT2: %04X\n", encx24j600_read_phy(priv,
0582                                  PHSTAT2));
0583     pr_info(DRV_NAME " PHSTAT3: %04X\n", encx24j600_read_phy(priv,
0584                                  PHSTAT3));
0585 }
0586 
0587 static void encx24j600_set_rxfilter_mode(struct encx24j600_priv *priv)
0588 {
0589     switch (priv->rxfilter) {
0590     case RXFILTER_PROMISC:
0591         encx24j600_set_bits(priv, MACON1, PASSALL);
0592         encx24j600_write_reg(priv, ERXFCON, UCEN | MCEN | NOTMEEN);
0593         break;
0594     case RXFILTER_MULTI:
0595         encx24j600_clr_bits(priv, MACON1, PASSALL);
0596         encx24j600_write_reg(priv, ERXFCON, UCEN | CRCEN | BCEN | MCEN);
0597         break;
0598     case RXFILTER_NORMAL:
0599     default:
0600         encx24j600_clr_bits(priv, MACON1, PASSALL);
0601         encx24j600_write_reg(priv, ERXFCON, UCEN | CRCEN | BCEN);
0602         break;
0603     }
0604 }
0605 
0606 static void encx24j600_hw_init(struct encx24j600_priv *priv)
0607 {
0608     u16 macon2;
0609 
0610     priv->hw_enabled = false;
0611 
0612     /* PHY Leds: link status,
0613      * LEDA: Link State + collision events
0614      * LEDB: Link State + transmit/receive events
0615      */
0616     encx24j600_update_reg(priv, EIDLED, 0xff00, 0xcb00);
0617 
0618     /* Loopback disabled */
0619     encx24j600_write_reg(priv, MACON1, 0x9);
0620 
0621     /* interpacket gap value */
0622     encx24j600_write_reg(priv, MAIPG, 0x0c12);
0623 
0624     /* Write the auto negotiation pattern */
0625     encx24j600_write_phy(priv, PHANA, PHANA_DEFAULT);
0626 
0627     encx24j600_update_phcon1(priv);
0628     encx24j600_check_link_status(priv);
0629 
0630     macon2 = MACON2_RSV1 | TXCRCEN | PADCFG0 | PADCFG2 | MACON2_DEFER;
0631     if ((priv->autoneg == AUTONEG_DISABLE) && priv->full_duplex)
0632         macon2 |= FULDPX;
0633 
0634     encx24j600_set_bits(priv, MACON2, macon2);
0635 
0636     priv->rxfilter = RXFILTER_NORMAL;
0637     encx24j600_set_rxfilter_mode(priv);
0638 
0639     /* Program the Maximum frame length */
0640     encx24j600_write_reg(priv, MAMXFL, MAX_FRAMELEN);
0641 
0642     /* Init Tx pointers */
0643     encx24j600_hw_init_tx(priv);
0644 
0645     /* Init Rx pointers */
0646     encx24j600_hw_init_rx(priv);
0647 
0648     if (netif_msg_hw(priv))
0649         encx24j600_dump_config(priv, "Hw is initialized");
0650 }
0651 
0652 static void encx24j600_hw_enable(struct encx24j600_priv *priv)
0653 {
0654     /* Clear the interrupt flags in case was set */
0655     encx24j600_clr_bits(priv, EIR, (PCFULIF | RXABTIF | TXABTIF | TXIF |
0656                     PKTIF | LINKIF));
0657 
0658     /* Enable the interrupts */
0659     encx24j600_write_reg(priv, EIE, (PCFULIE | RXABTIE | TXABTIE | TXIE |
0660                      PKTIE | LINKIE | INTIE));
0661 
0662     /* Enable RX */
0663     encx24j600_cmd(priv, ENABLERX);
0664 
0665     priv->hw_enabled = true;
0666 }
0667 
0668 static void encx24j600_hw_disable(struct encx24j600_priv *priv)
0669 {
0670     /* Disable all interrupts */
0671     encx24j600_write_reg(priv, EIE, 0);
0672 
0673     /* Disable RX */
0674     encx24j600_cmd(priv, DISABLERX);
0675 
0676     priv->hw_enabled = false;
0677 }
0678 
0679 static int encx24j600_setlink(struct net_device *dev, u8 autoneg, u16 speed,
0680                   u8 duplex)
0681 {
0682     struct encx24j600_priv *priv = netdev_priv(dev);
0683     int ret = 0;
0684 
0685     if (!priv->hw_enabled) {
0686         /* link is in low power mode now; duplex setting
0687          * will take effect on next encx24j600_hw_init()
0688          */
0689         if (speed == SPEED_10 || speed == SPEED_100) {
0690             priv->autoneg = (autoneg == AUTONEG_ENABLE);
0691             priv->full_duplex = (duplex == DUPLEX_FULL);
0692             priv->speed = (speed == SPEED_100);
0693         } else {
0694             netif_warn(priv, link, dev, "unsupported link speed setting\n");
0695             /*speeds other than SPEED_10 and SPEED_100 */
0696             /*are not supported by chip */
0697             ret = -EOPNOTSUPP;
0698         }
0699     } else {
0700         netif_warn(priv, link, dev, "Warning: hw must be disabled to set link mode\n");
0701         ret = -EBUSY;
0702     }
0703     return ret;
0704 }
0705 
0706 static void encx24j600_hw_get_macaddr(struct encx24j600_priv *priv,
0707                       unsigned char *ethaddr)
0708 {
0709     unsigned short val;
0710 
0711     val = encx24j600_read_reg(priv, MAADR1);
0712 
0713     ethaddr[0] = val & 0x00ff;
0714     ethaddr[1] = (val & 0xff00) >> 8;
0715 
0716     val = encx24j600_read_reg(priv, MAADR2);
0717 
0718     ethaddr[2] = val & 0x00ffU;
0719     ethaddr[3] = (val & 0xff00U) >> 8;
0720 
0721     val = encx24j600_read_reg(priv, MAADR3);
0722 
0723     ethaddr[4] = val & 0x00ffU;
0724     ethaddr[5] = (val & 0xff00U) >> 8;
0725 }
0726 
0727 /* Program the hardware MAC address from dev->dev_addr.*/
0728 static int encx24j600_set_hw_macaddr(struct net_device *dev)
0729 {
0730     struct encx24j600_priv *priv = netdev_priv(dev);
0731 
0732     if (priv->hw_enabled) {
0733         netif_info(priv, drv, dev, "Hardware must be disabled to set Mac address\n");
0734         return -EBUSY;
0735     }
0736 
0737     mutex_lock(&priv->lock);
0738 
0739     netif_info(priv, drv, dev, "%s: Setting MAC address to %pM\n",
0740            dev->name, dev->dev_addr);
0741 
0742     encx24j600_write_reg(priv, MAADR3, (dev->dev_addr[4] |
0743                  dev->dev_addr[5] << 8));
0744     encx24j600_write_reg(priv, MAADR2, (dev->dev_addr[2] |
0745                  dev->dev_addr[3] << 8));
0746     encx24j600_write_reg(priv, MAADR1, (dev->dev_addr[0] |
0747                  dev->dev_addr[1] << 8));
0748 
0749     mutex_unlock(&priv->lock);
0750 
0751     return 0;
0752 }
0753 
0754 /* Store the new hardware address in dev->dev_addr, and update the MAC.*/
0755 static int encx24j600_set_mac_address(struct net_device *dev, void *addr)
0756 {
0757     struct sockaddr *address = addr;
0758 
0759     if (netif_running(dev))
0760         return -EBUSY;
0761     if (!is_valid_ether_addr(address->sa_data))
0762         return -EADDRNOTAVAIL;
0763 
0764     eth_hw_addr_set(dev, address->sa_data);
0765     return encx24j600_set_hw_macaddr(dev);
0766 }
0767 
0768 static int encx24j600_open(struct net_device *dev)
0769 {
0770     struct encx24j600_priv *priv = netdev_priv(dev);
0771 
0772     int ret = request_threaded_irq(priv->ctx.spi->irq, NULL, encx24j600_isr,
0773                        IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
0774                        DRV_NAME, priv);
0775     if (unlikely(ret < 0)) {
0776         netdev_err(dev, "request irq %d failed (ret = %d)\n",
0777                priv->ctx.spi->irq, ret);
0778         return ret;
0779     }
0780 
0781     encx24j600_hw_disable(priv);
0782     encx24j600_hw_init(priv);
0783     encx24j600_hw_enable(priv);
0784     netif_start_queue(dev);
0785 
0786     return 0;
0787 }
0788 
0789 static int encx24j600_stop(struct net_device *dev)
0790 {
0791     struct encx24j600_priv *priv = netdev_priv(dev);
0792 
0793     netif_stop_queue(dev);
0794     free_irq(priv->ctx.spi->irq, priv);
0795     return 0;
0796 }
0797 
0798 static void encx24j600_setrx_proc(struct kthread_work *ws)
0799 {
0800     struct encx24j600_priv *priv =
0801             container_of(ws, struct encx24j600_priv, setrx_work);
0802 
0803     mutex_lock(&priv->lock);
0804     encx24j600_set_rxfilter_mode(priv);
0805     mutex_unlock(&priv->lock);
0806 }
0807 
0808 static void encx24j600_set_multicast_list(struct net_device *dev)
0809 {
0810     struct encx24j600_priv *priv = netdev_priv(dev);
0811     int oldfilter = priv->rxfilter;
0812 
0813     if (dev->flags & IFF_PROMISC) {
0814         netif_dbg(priv, link, dev, "promiscuous mode\n");
0815         priv->rxfilter = RXFILTER_PROMISC;
0816     } else if ((dev->flags & IFF_ALLMULTI) || !netdev_mc_empty(dev)) {
0817         netif_dbg(priv, link, dev, "%smulticast mode\n",
0818               (dev->flags & IFF_ALLMULTI) ? "all-" : "");
0819         priv->rxfilter = RXFILTER_MULTI;
0820     } else {
0821         netif_dbg(priv, link, dev, "normal mode\n");
0822         priv->rxfilter = RXFILTER_NORMAL;
0823     }
0824 
0825     if (oldfilter != priv->rxfilter)
0826         kthread_queue_work(&priv->kworker, &priv->setrx_work);
0827 }
0828 
0829 static void encx24j600_hw_tx(struct encx24j600_priv *priv)
0830 {
0831     struct net_device *dev = priv->ndev;
0832 
0833     netif_info(priv, tx_queued, dev, "TX Packet Len:%d\n",
0834            priv->tx_skb->len);
0835 
0836     if (netif_msg_pktdata(priv))
0837         dump_packet("TX", priv->tx_skb->len, priv->tx_skb->data);
0838 
0839     if (encx24j600_read_reg(priv, EIR) & TXABTIF)
0840         /* Last transmition aborted due to error. Reset TX interface */
0841         encx24j600_reset_hw_tx(priv);
0842 
0843     /* Clear the TXIF flag if were previously set */
0844     encx24j600_clr_bits(priv, EIR, TXIF);
0845 
0846     /* Set the data pointer to the TX buffer address in the SRAM */
0847     encx24j600_write_reg(priv, EGPWRPT, ENC_TX_BUF_START);
0848 
0849     /* Copy the packet into the SRAM */
0850     encx24j600_raw_write(priv, WGPDATA, (u8 *)priv->tx_skb->data,
0851                  priv->tx_skb->len);
0852 
0853     /* Program the Tx buffer start pointer */
0854     encx24j600_write_reg(priv, ETXST, ENC_TX_BUF_START);
0855 
0856     /* Program the packet length */
0857     encx24j600_write_reg(priv, ETXLEN, priv->tx_skb->len);
0858 
0859     /* Start the transmission */
0860     encx24j600_cmd(priv, SETTXRTS);
0861 }
0862 
0863 static void encx24j600_tx_proc(struct kthread_work *ws)
0864 {
0865     struct encx24j600_priv *priv =
0866             container_of(ws, struct encx24j600_priv, tx_work);
0867 
0868     mutex_lock(&priv->lock);
0869     encx24j600_hw_tx(priv);
0870     mutex_unlock(&priv->lock);
0871 }
0872 
0873 static netdev_tx_t encx24j600_tx(struct sk_buff *skb, struct net_device *dev)
0874 {
0875     struct encx24j600_priv *priv = netdev_priv(dev);
0876 
0877     netif_stop_queue(dev);
0878 
0879     /* save the timestamp */
0880     netif_trans_update(dev);
0881 
0882     /* Remember the skb for deferred processing */
0883     priv->tx_skb = skb;
0884 
0885     kthread_queue_work(&priv->kworker, &priv->tx_work);
0886 
0887     return NETDEV_TX_OK;
0888 }
0889 
0890 /* Deal with a transmit timeout */
0891 static void encx24j600_tx_timeout(struct net_device *dev, unsigned int txqueue)
0892 {
0893     struct encx24j600_priv *priv = netdev_priv(dev);
0894 
0895     netif_err(priv, tx_err, dev, "TX timeout at %ld, latency %ld\n",
0896           jiffies, jiffies - dev_trans_start(dev));
0897 
0898     dev->stats.tx_errors++;
0899     netif_wake_queue(dev);
0900 }
0901 
0902 static int encx24j600_get_regs_len(struct net_device *dev)
0903 {
0904     return SFR_REG_COUNT;
0905 }
0906 
0907 static void encx24j600_get_regs(struct net_device *dev,
0908                 struct ethtool_regs *regs, void *p)
0909 {
0910     struct encx24j600_priv *priv = netdev_priv(dev);
0911     u16 *buff = p;
0912     u8 reg;
0913 
0914     regs->version = 1;
0915     mutex_lock(&priv->lock);
0916     for (reg = 0; reg < SFR_REG_COUNT; reg += 2) {
0917         unsigned int val = 0;
0918         /* ignore errors for unreadable registers */
0919         regmap_read(priv->ctx.regmap, reg, &val);
0920         buff[reg] = val & 0xffff;
0921     }
0922     mutex_unlock(&priv->lock);
0923 }
0924 
0925 static void encx24j600_get_drvinfo(struct net_device *dev,
0926                    struct ethtool_drvinfo *info)
0927 {
0928     strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
0929     strlcpy(info->version, DRV_VERSION, sizeof(info->version));
0930     strlcpy(info->bus_info, dev_name(dev->dev.parent),
0931         sizeof(info->bus_info));
0932 }
0933 
0934 static int encx24j600_get_link_ksettings(struct net_device *dev,
0935                      struct ethtool_link_ksettings *cmd)
0936 {
0937     struct encx24j600_priv *priv = netdev_priv(dev);
0938     u32 supported;
0939 
0940     supported = SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
0941              SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
0942              SUPPORTED_Autoneg | SUPPORTED_TP;
0943 
0944     ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
0945                         supported);
0946 
0947     cmd->base.speed = priv->speed;
0948     cmd->base.duplex = priv->full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
0949     cmd->base.port = PORT_TP;
0950     cmd->base.autoneg = priv->autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
0951 
0952     return 0;
0953 }
0954 
0955 static int
0956 encx24j600_set_link_ksettings(struct net_device *dev,
0957                   const struct ethtool_link_ksettings *cmd)
0958 {
0959     return encx24j600_setlink(dev, cmd->base.autoneg,
0960                   cmd->base.speed, cmd->base.duplex);
0961 }
0962 
0963 static u32 encx24j600_get_msglevel(struct net_device *dev)
0964 {
0965     struct encx24j600_priv *priv = netdev_priv(dev);
0966 
0967     return priv->msg_enable;
0968 }
0969 
0970 static void encx24j600_set_msglevel(struct net_device *dev, u32 val)
0971 {
0972     struct encx24j600_priv *priv = netdev_priv(dev);
0973 
0974     priv->msg_enable = val;
0975 }
0976 
0977 static const struct ethtool_ops encx24j600_ethtool_ops = {
0978     .get_drvinfo = encx24j600_get_drvinfo,
0979     .get_msglevel = encx24j600_get_msglevel,
0980     .set_msglevel = encx24j600_set_msglevel,
0981     .get_regs_len = encx24j600_get_regs_len,
0982     .get_regs = encx24j600_get_regs,
0983     .get_link_ksettings = encx24j600_get_link_ksettings,
0984     .set_link_ksettings = encx24j600_set_link_ksettings,
0985 };
0986 
0987 static const struct net_device_ops encx24j600_netdev_ops = {
0988     .ndo_open = encx24j600_open,
0989     .ndo_stop = encx24j600_stop,
0990     .ndo_start_xmit = encx24j600_tx,
0991     .ndo_set_rx_mode = encx24j600_set_multicast_list,
0992     .ndo_set_mac_address = encx24j600_set_mac_address,
0993     .ndo_tx_timeout = encx24j600_tx_timeout,
0994     .ndo_validate_addr = eth_validate_addr,
0995 };
0996 
0997 static int encx24j600_spi_probe(struct spi_device *spi)
0998 {
0999     int ret;
1000 
1001     struct net_device *ndev;
1002     struct encx24j600_priv *priv;
1003     u16 eidled;
1004     u8 addr[ETH_ALEN];
1005 
1006     ndev = alloc_etherdev(sizeof(struct encx24j600_priv));
1007 
1008     if (!ndev) {
1009         ret = -ENOMEM;
1010         goto error_out;
1011     }
1012 
1013     priv = netdev_priv(ndev);
1014     spi_set_drvdata(spi, priv);
1015     dev_set_drvdata(&spi->dev, priv);
1016     SET_NETDEV_DEV(ndev, &spi->dev);
1017 
1018     priv->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
1019     priv->ndev = ndev;
1020 
1021     /* Default configuration PHY configuration */
1022     priv->full_duplex = true;
1023     priv->autoneg = AUTONEG_ENABLE;
1024     priv->speed = SPEED_100;
1025 
1026     priv->ctx.spi = spi;
1027     ndev->irq = spi->irq;
1028     ndev->netdev_ops = &encx24j600_netdev_ops;
1029 
1030     ret = devm_regmap_init_encx24j600(&spi->dev, &priv->ctx);
1031     if (ret)
1032         goto out_free;
1033 
1034     mutex_init(&priv->lock);
1035 
1036     /* Reset device and check if it is connected */
1037     if (encx24j600_hw_reset(priv)) {
1038         netif_err(priv, probe, ndev,
1039               DRV_NAME ": Chip is not detected\n");
1040         ret = -EIO;
1041         goto out_free;
1042     }
1043 
1044     /* Initialize the device HW to the consistent state */
1045     encx24j600_hw_init(priv);
1046 
1047     kthread_init_worker(&priv->kworker);
1048     kthread_init_work(&priv->tx_work, encx24j600_tx_proc);
1049     kthread_init_work(&priv->setrx_work, encx24j600_setrx_proc);
1050 
1051     priv->kworker_task = kthread_run(kthread_worker_fn, &priv->kworker,
1052                      "encx24j600");
1053 
1054     if (IS_ERR(priv->kworker_task)) {
1055         ret = PTR_ERR(priv->kworker_task);
1056         goto out_free;
1057     }
1058 
1059     /* Get the MAC address from the chip */
1060     encx24j600_hw_get_macaddr(priv, addr);
1061     eth_hw_addr_set(ndev, addr);
1062 
1063     ndev->ethtool_ops = &encx24j600_ethtool_ops;
1064 
1065     ret = register_netdev(ndev);
1066     if (unlikely(ret)) {
1067         netif_err(priv, probe, ndev, "Error %d initializing card encx24j600 card\n",
1068               ret);
1069         goto out_stop;
1070     }
1071 
1072     eidled = encx24j600_read_reg(priv, EIDLED);
1073     if (((eidled & DEVID_MASK) >> DEVID_SHIFT) != ENCX24J600_DEV_ID) {
1074         ret = -EINVAL;
1075         goto out_unregister;
1076     }
1077 
1078     netif_info(priv, probe, ndev, "Silicon rev ID: 0x%02x\n",
1079            (eidled & REVID_MASK) >> REVID_SHIFT);
1080 
1081     netif_info(priv, drv, priv->ndev, "MAC address %pM\n", ndev->dev_addr);
1082 
1083     return ret;
1084 
1085 out_unregister:
1086     unregister_netdev(priv->ndev);
1087 out_stop:
1088     kthread_stop(priv->kworker_task);
1089 out_free:
1090     free_netdev(ndev);
1091 
1092 error_out:
1093     return ret;
1094 }
1095 
1096 static void encx24j600_spi_remove(struct spi_device *spi)
1097 {
1098     struct encx24j600_priv *priv = dev_get_drvdata(&spi->dev);
1099 
1100     unregister_netdev(priv->ndev);
1101     kthread_stop(priv->kworker_task);
1102 
1103     free_netdev(priv->ndev);
1104 }
1105 
1106 static const struct spi_device_id encx24j600_spi_id_table[] = {
1107     { .name = "encx24j600" },
1108     { /* sentinel */ }
1109 };
1110 MODULE_DEVICE_TABLE(spi, encx24j600_spi_id_table);
1111 
1112 static struct spi_driver encx24j600_spi_net_driver = {
1113     .driver = {
1114         .name   = DRV_NAME,
1115         .owner  = THIS_MODULE,
1116         .bus    = &spi_bus_type,
1117     },
1118     .probe      = encx24j600_spi_probe,
1119     .remove     = encx24j600_spi_remove,
1120     .id_table   = encx24j600_spi_id_table,
1121 };
1122 
1123 module_spi_driver(encx24j600_spi_net_driver);
1124 
1125 MODULE_DESCRIPTION(DRV_NAME " ethernet driver");
1126 MODULE_AUTHOR("Jon Ringle <jringle@gridpoint.com>");
1127 MODULE_LICENSE("GPL");
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