ethernet/microchip/encx24j600-regmap.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Register map access API - ENCX24J600 support
0004  *
0005  * Copyright 2015 Gridpoint
0006  *
0007  * Author: Jon Ringle <jringle@gridpoint.com>
0008  */
0009
0010 #include <linux/delay.h>
0011 #include <linux/errno.h>
0012 #include <linux/init.h>
0013 #include <linux/module.h>
0014 #include <linux/netdevice.h>
0015 #include <linux/regmap.h>
0016 #include <linux/spi/spi.h>
0017
0018 #include "encx24j600_hw.h"
0019
0020 static int encx24j600_switch_bank(struct encx24j600_context *ctx,
0021                   int bank)
0022 {
0023     int ret = 0;
0024     int bank_opcode = BANK_SELECT(bank);
0025
0026     ret = spi_write(ctx->spi, &bank_opcode, 1);
0027     if (ret == 0)
0028         ctx->bank = bank;
0029
0030     return ret;
0031 }
0032
0033 static int encx24j600_cmdn(struct encx24j600_context *ctx, u8 opcode,
0034                const void *buf, size_t len)
0035 {
0036     struct spi_message m;
0037     struct spi_transfer t[2] = { { .tx_buf = &opcode, .len = 1, },
0038                      { .tx_buf = buf, .len = len }, };
0039     spi_message_init(&m);
0040     spi_message_add_tail(&t[0], &m);
0041     spi_message_add_tail(&t[1], &m);
0042
0043     return spi_sync(ctx->spi, &m);
0044 }
0045
0046 static void regmap_lock_mutex(void *context)
0047 {
0048     struct encx24j600_context *ctx = context;
0049
0050     mutex_lock(&ctx->mutex);
0051 }
0052
0053 static void regmap_unlock_mutex(void *context)
0054 {
0055     struct encx24j600_context *ctx = context;
0056
0057     mutex_unlock(&ctx->mutex);
0058 }
0059
0060 static int regmap_encx24j600_sfr_read(void *context, u8 reg, u8 *val,
0061                       size_t len)
0062 {
0063     struct encx24j600_context *ctx = context;
0064     u8 banked_reg = reg & ADDR_MASK;
0065     u8 bank = ((reg & BANK_MASK) >> BANK_SHIFT);
0066     u8 cmd = RCRU;
0067     int ret = 0;
0068     int i = 0;
0069     u8 tx_buf[2];
0070
0071     if (reg < 0x80) {
0072         cmd = RCRCODE | banked_reg;
0073         if ((banked_reg < 0x16) && (ctx->bank != bank))
0074             ret = encx24j600_switch_bank(ctx, bank);
0075         if (unlikely(ret))
0076             return ret;
0077     } else {
0078         /* Translate registers that are more effecient using
0079          * 3-byte SPI commands
0080          */
0081         switch (reg) {
0082         case EGPRDPT:
0083             cmd = RGPRDPT; break;
0084         case EGPWRPT:
0085             cmd = RGPWRPT; break;
0086         case ERXRDPT:
0087             cmd = RRXRDPT; break;
0088         case ERXWRPT:
0089             cmd = RRXWRPT; break;
0090         case EUDARDPT:
0091             cmd = RUDARDPT; break;
0092         case EUDAWRPT:
0093             cmd = RUDAWRPT; break;
0094         case EGPDATA:
0095         case ERXDATA:
0096         case EUDADATA:
0097         default:
0098             return -EINVAL;
0099         }
0100     }
0101
0102     tx_buf[i++] = cmd;
0103     if (cmd == RCRU)
0104         tx_buf[i++] = reg;
0105
0106     ret = spi_write_then_read(ctx->spi, tx_buf, i, val, len);
0107
0108     return ret;
0109 }
0110
0111 static int regmap_encx24j600_sfr_update(struct encx24j600_context *ctx,
0112                     u8 reg, u8 *val, size_t len,
0113                     u8 unbanked_cmd, u8 banked_code)
0114 {
0115     u8 banked_reg = reg & ADDR_MASK;
0116     u8 bank = ((reg & BANK_MASK) >> BANK_SHIFT);
0117     u8 cmd = unbanked_cmd;
0118     struct spi_message m;
0119     struct spi_transfer t[3] = { { .tx_buf = &cmd, .len = sizeof(cmd), },
0120                      { .tx_buf = &reg, .len = sizeof(reg), },
0121                      { .tx_buf = val, .len = len }, };
0122
0123     if (reg < 0x80) {
0124         int ret = 0;
0125
0126         cmd = banked_code | banked_reg;
0127         if ((banked_reg < 0x16) && (ctx->bank != bank))
0128             ret = encx24j600_switch_bank(ctx, bank);
0129         if (unlikely(ret))
0130             return ret;
0131     } else {
0132         /* Translate registers that are more effecient using
0133          * 3-byte SPI commands
0134          */
0135         switch (reg) {
0136         case EGPRDPT:
0137             cmd = WGPRDPT; break;
0138         case EGPWRPT:
0139             cmd = WGPWRPT; break;
0140         case ERXRDPT:
0141             cmd = WRXRDPT; break;
0142         case ERXWRPT:
0143             cmd = WRXWRPT; break;
0144         case EUDARDPT:
0145             cmd = WUDARDPT; break;
0146         case EUDAWRPT:
0147             cmd = WUDAWRPT; break;
0148         case EGPDATA:
0149         case ERXDATA:
0150         case EUDADATA:
0151         default:
0152             return -EINVAL;
0153         }
0154     }
0155
0156     spi_message_init(&m);
0157     spi_message_add_tail(&t[0], &m);
0158
0159     if (cmd == unbanked_cmd) {
0160         t[1].tx_buf = &reg;
0161         spi_message_add_tail(&t[1], &m);
0162     }
0163
0164     spi_message_add_tail(&t[2], &m);
0165     return spi_sync(ctx->spi, &m);
0166 }
0167
0168 static int regmap_encx24j600_sfr_write(void *context, u8 reg, u8 *val,
0169                        size_t len)
0170 {
0171     struct encx24j600_context *ctx = context;
0172
0173     return regmap_encx24j600_sfr_update(ctx, reg, val, len, WCRU, WCRCODE);
0174 }
0175
0176 static int regmap_encx24j600_sfr_set_bits(struct encx24j600_context *ctx,
0177                       u8 reg, u8 val)
0178 {
0179     return regmap_encx24j600_sfr_update(ctx, reg, &val, 1, BFSU, BFSCODE);
0180 }
0181
0182 static int regmap_encx24j600_sfr_clr_bits(struct encx24j600_context *ctx,
0183                       u8 reg, u8 val)
0184 {
0185     return regmap_encx24j600_sfr_update(ctx, reg, &val, 1, BFCU, BFCCODE);
0186 }
0187
0188 static int regmap_encx24j600_reg_update_bits(void *context, unsigned int reg,
0189                          unsigned int mask,
0190                          unsigned int val)
0191 {
0192     struct encx24j600_context *ctx = context;
0193
0194     int ret = 0;
0195     unsigned int set_mask = mask & val;
0196     unsigned int clr_mask = mask & ~val;
0197
0198     if ((reg >= 0x40 && reg < 0x6c) || reg >= 0x80)
0199         return -EINVAL;
0200
0201     if (set_mask & 0xff)
0202         ret = regmap_encx24j600_sfr_set_bits(ctx, reg, set_mask);
0203
0204     set_mask = (set_mask & 0xff00) >> 8;
0205
0206     if ((set_mask & 0xff) && (ret == 0))
0207         ret = regmap_encx24j600_sfr_set_bits(ctx, reg + 1, set_mask);
0208
0209     if ((clr_mask & 0xff) && (ret == 0))
0210         ret = regmap_encx24j600_sfr_clr_bits(ctx, reg, clr_mask);
0211
0212     clr_mask = (clr_mask & 0xff00) >> 8;
0213
0214     if ((clr_mask & 0xff) && (ret == 0))
0215         ret = regmap_encx24j600_sfr_clr_bits(ctx, reg + 1, clr_mask);
0216
0217     return ret;
0218 }
0219
0220 int regmap_encx24j600_spi_write(void *context, u8 reg, const u8 *data,
0221                 size_t count)
0222 {
0223     struct encx24j600_context *ctx = context;
0224
0225     if (reg < 0xc0)
0226         return encx24j600_cmdn(ctx, reg, data, count);
0227
0228     /* SPI 1-byte command. Ignore data */
0229     return spi_write(ctx->spi, &reg, 1);
0230 }
0231 EXPORT_SYMBOL_GPL(regmap_encx24j600_spi_write);
0232
0233 int regmap_encx24j600_spi_read(void *context, u8 reg, u8 *data, size_t count)
0234 {
0235     struct encx24j600_context *ctx = context;
0236
0237     if (reg == RBSEL && count > 1)
0238         count = 1;
0239
0240     return spi_write_then_read(ctx->spi, &reg, sizeof(reg), data, count);
0241 }
0242 EXPORT_SYMBOL_GPL(regmap_encx24j600_spi_read);
0243
0244 static int regmap_encx24j600_write(void *context, const void *data,
0245                    size_t len)
0246 {
0247     u8 *dout = (u8 *)data;
0248     u8 reg = dout[0];
0249     ++dout;
0250     --len;
0251
0252     if (reg > 0xa0)
0253         return regmap_encx24j600_spi_write(context, reg, dout, len);
0254
0255     if (len > 2)
0256         return -EINVAL;
0257
0258     return regmap_encx24j600_sfr_write(context, reg, dout, len);
0259 }
0260
0261 static int regmap_encx24j600_read(void *context,
0262                   const void *reg_buf, size_t reg_size,
0263                   void *val, size_t val_size)
0264 {
0265     u8 reg = *(const u8 *)reg_buf;
0266
0267     if (reg_size != 1) {
0268         pr_err("%s: reg=%02x reg_size=%zu\n", __func__, reg, reg_size);
0269         return -EINVAL;
0270     }
0271
0272     if (reg > 0xa0)
0273         return regmap_encx24j600_spi_read(context, reg, val, val_size);
0274
0275     if (val_size > 2) {
0276         pr_err("%s: reg=%02x val_size=%zu\n", __func__, reg, val_size);
0277         return -EINVAL;
0278     }
0279
0280     return regmap_encx24j600_sfr_read(context, reg, val, val_size);
0281 }
0282
0283 static bool encx24j600_regmap_readable(struct device *dev, unsigned int reg)
0284 {
0285     if ((reg < 0x36) ||
0286         ((reg >= 0x40) && (reg < 0x4c)) ||
0287         ((reg >= 0x52) && (reg < 0x56)) ||
0288         ((reg >= 0x60) && (reg < 0x66)) ||
0289         ((reg >= 0x68) && (reg < 0x80)) ||
0290         ((reg >= 0x86) && (reg < 0x92)) ||
0291         (reg == 0xc8))
0292         return true;
0293     else
0294         return false;
0295 }
0296
0297 static bool encx24j600_regmap_writeable(struct device *dev, unsigned int reg)
0298 {
0299     if ((reg < 0x12) ||
0300         ((reg >= 0x14) && (reg < 0x1a)) ||
0301         ((reg >= 0x1c) && (reg < 0x36)) ||
0302         ((reg >= 0x40) && (reg < 0x4c)) ||
0303         ((reg >= 0x52) && (reg < 0x56)) ||
0304         ((reg >= 0x60) && (reg < 0x68)) ||
0305         ((reg >= 0x6c) && (reg < 0x80)) ||
0306         ((reg >= 0x86) && (reg < 0x92)) ||
0307         ((reg >= 0xc0) && (reg < 0xc8)) ||
0308         ((reg >= 0xca) && (reg < 0xf0)))
0309         return true;
0310     else
0311         return false;
0312 }
0313
0314 static bool encx24j600_regmap_volatile(struct device *dev, unsigned int reg)
0315 {
0316     switch (reg) {
0317     case ERXHEAD:
0318     case EDMACS:
0319     case ETXSTAT:
0320     case ETXWIRE:
0321     case ECON1: /* Can be modified via single byte cmds */
0322     case ECON2: /* Can be modified via single byte cmds */
0323     case ESTAT:
0324     case EIR:   /* Can be modified via single byte cmds */
0325     case MIRD:
0326     case MISTAT:
0327         return true;
0328     default:
0329         break;
0330     }
0331
0332     return false;
0333 }
0334
0335 static bool encx24j600_regmap_precious(struct device *dev, unsigned int reg)
0336 {
0337     /* single byte cmds are precious */
0338     if (((reg >= 0xc0) && (reg < 0xc8)) ||
0339         ((reg >= 0xca) && (reg < 0xf0)))
0340         return true;
0341     else
0342         return false;
0343 }
0344
0345 static int regmap_encx24j600_phy_reg_read(void *context, unsigned int reg,
0346                       unsigned int *val)
0347 {
0348     struct encx24j600_context *ctx = context;
0349     int ret;
0350     unsigned int mistat;
0351
0352     reg = MIREGADR_VAL | (reg & PHREG_MASK);
0353     ret = regmap_write(ctx->regmap, MIREGADR, reg);
0354     if (unlikely(ret))
0355         goto err_out;
0356
0357     ret = regmap_write(ctx->regmap, MICMD, MIIRD);
0358     if (unlikely(ret))
0359         goto err_out;
0360
0361     usleep_range(26, 100);
0362     while ((ret = regmap_read(ctx->regmap, MISTAT, &mistat) != 0) &&
0363            (mistat & BUSY))
0364         cpu_relax();
0365
0366     if (unlikely(ret))
0367         goto err_out;
0368
0369     ret = regmap_write(ctx->regmap, MICMD, 0);
0370     if (unlikely(ret))
0371         goto err_out;
0372
0373     ret = regmap_read(ctx->regmap, MIRD, val);
0374
0375 err_out:
0376     if (ret)
0377         pr_err("%s: error %d reading reg %02x\n", __func__, ret,
0378                reg & PHREG_MASK);
0379
0380     return ret;
0381 }
0382
0383 static int regmap_encx24j600_phy_reg_write(void *context, unsigned int reg,
0384                        unsigned int val)
0385 {
0386     struct encx24j600_context *ctx = context;
0387     int ret;
0388     unsigned int mistat;
0389
0390     reg = MIREGADR_VAL | (reg & PHREG_MASK);
0391     ret = regmap_write(ctx->regmap, MIREGADR, reg);
0392     if (unlikely(ret))
0393         goto err_out;
0394
0395     ret = regmap_write(ctx->regmap, MIWR, val);
0396     if (unlikely(ret))
0397         goto err_out;
0398
0399     usleep_range(26, 100);
0400     while ((ret = regmap_read(ctx->regmap, MISTAT, &mistat) != 0) &&
0401            (mistat & BUSY))
0402         cpu_relax();
0403
0404 err_out:
0405     if (ret)
0406         pr_err("%s: error %d writing reg %02x=%04x\n", __func__, ret,
0407                reg & PHREG_MASK, val);
0408
0409     return ret;
0410 }
0411
0412 static bool encx24j600_phymap_readable(struct device *dev, unsigned int reg)
0413 {
0414     switch (reg) {
0415     case PHCON1:
0416     case PHSTAT1:
0417     case PHANA:
0418     case PHANLPA:
0419     case PHANE:
0420     case PHCON2:
0421     case PHSTAT2:
0422     case PHSTAT3:
0423         return true;
0424     default:
0425         return false;
0426     }
0427 }
0428
0429 static bool encx24j600_phymap_writeable(struct device *dev, unsigned int reg)
0430 {
0431     switch (reg) {
0432     case PHCON1:
0433     case PHCON2:
0434     case PHANA:
0435         return true;
0436     case PHSTAT1:
0437     case PHSTAT2:
0438     case PHSTAT3:
0439     case PHANLPA:
0440     case PHANE:
0441     default:
0442         return false;
0443     }
0444 }
0445
0446 static bool encx24j600_phymap_volatile(struct device *dev, unsigned int reg)
0447 {
0448     switch (reg) {
0449     case PHSTAT1:
0450     case PHSTAT2:
0451     case PHSTAT3:
0452     case PHANLPA:
0453     case PHANE:
0454     case PHCON2:
0455         return true;
0456     default:
0457         return false;
0458     }
0459 }
0460
0461 static struct regmap_config regcfg = {
0462     .name = "reg",
0463     .reg_bits = 8,
0464     .val_bits = 16,
0465     .max_register = 0xee,
0466     .reg_stride = 2,
0467     .cache_type = REGCACHE_RBTREE,
0468     .val_format_endian = REGMAP_ENDIAN_LITTLE,
0469     .readable_reg = encx24j600_regmap_readable,
0470     .writeable_reg = encx24j600_regmap_writeable,
0471     .volatile_reg = encx24j600_regmap_volatile,
0472     .precious_reg = encx24j600_regmap_precious,
0473     .lock = regmap_lock_mutex,
0474     .unlock = regmap_unlock_mutex,
0475 };
0476
0477 static struct regmap_bus regmap_encx24j600 = {
0478     .write = regmap_encx24j600_write,
0479     .read = regmap_encx24j600_read,
0480     .reg_update_bits = regmap_encx24j600_reg_update_bits,
0481 };
0482
0483 static struct regmap_config phycfg = {
0484     .name = "phy",
0485     .reg_bits = 8,
0486     .val_bits = 16,
0487     .max_register = 0x1f,
0488     .cache_type = REGCACHE_RBTREE,
0489     .val_format_endian = REGMAP_ENDIAN_LITTLE,
0490     .readable_reg = encx24j600_phymap_readable,
0491     .writeable_reg = encx24j600_phymap_writeable,
0492     .volatile_reg = encx24j600_phymap_volatile,
0493 };
0494
0495 static struct regmap_bus phymap_encx24j600 = {
0496     .reg_write = regmap_encx24j600_phy_reg_write,
0497     .reg_read = regmap_encx24j600_phy_reg_read,
0498 };
0499
0500 int devm_regmap_init_encx24j600(struct device *dev,
0501                 struct encx24j600_context *ctx)
0502 {
0503     mutex_init(&ctx->mutex);
0504     regcfg.lock_arg = ctx;
0505     ctx->regmap = devm_regmap_init(dev, &regmap_encx24j600, ctx, &regcfg);
0506     if (IS_ERR(ctx->regmap))
0507         return PTR_ERR(ctx->regmap);
0508     ctx->phymap = devm_regmap_init(dev, &phymap_encx24j600, ctx, &phycfg);
0509     if (IS_ERR(ctx->phymap))
0510         return PTR_ERR(ctx->phymap);
0511
0512     return 0;
0513 }
0514 EXPORT_SYMBOL_GPL(devm_regmap_init_encx24j600);
0515
0516 MODULE_LICENSE("GPL");