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0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * enc28j60_hw.h: EDTP FrameThrower style enc28j60 registers
0004  *
0005  * $Id: enc28j60_hw.h,v 1.9 2007/12/14 11:59:16 claudio Exp $
0006  */
0007 
0008 #ifndef _ENC28J60_HW_H
0009 #define _ENC28J60_HW_H
0010 
0011 /*
0012  * ENC28J60 Control Registers
0013  * Control register definitions are a combination of address,
0014  * bank number, and Ethernet/MAC/PHY indicator bits.
0015  * - Register address   (bits 0-4)
0016  * - Bank number    (bits 5-6)
0017  * - MAC/MII indicator  (bit 7)
0018  */
0019 #define ADDR_MASK   0x1F
0020 #define BANK_MASK   0x60
0021 #define SPRD_MASK   0x80
0022 /* All-bank registers */
0023 #define EIE     0x1B
0024 #define EIR     0x1C
0025 #define ESTAT       0x1D
0026 #define ECON2       0x1E
0027 #define ECON1       0x1F
0028 /* Bank 0 registers */
0029 #define ERDPTL      (0x00|0x00)
0030 #define ERDPTH      (0x01|0x00)
0031 #define EWRPTL      (0x02|0x00)
0032 #define EWRPTH      (0x03|0x00)
0033 #define ETXSTL      (0x04|0x00)
0034 #define ETXSTH      (0x05|0x00)
0035 #define ETXNDL      (0x06|0x00)
0036 #define ETXNDH      (0x07|0x00)
0037 #define ERXSTL      (0x08|0x00)
0038 #define ERXSTH      (0x09|0x00)
0039 #define ERXNDL      (0x0A|0x00)
0040 #define ERXNDH      (0x0B|0x00)
0041 #define ERXRDPTL    (0x0C|0x00)
0042 #define ERXRDPTH    (0x0D|0x00)
0043 #define ERXWRPTL    (0x0E|0x00)
0044 #define ERXWRPTH    (0x0F|0x00)
0045 #define EDMASTL     (0x10|0x00)
0046 #define EDMASTH     (0x11|0x00)
0047 #define EDMANDL     (0x12|0x00)
0048 #define EDMANDH     (0x13|0x00)
0049 #define EDMADSTL    (0x14|0x00)
0050 #define EDMADSTH    (0x15|0x00)
0051 #define EDMACSL     (0x16|0x00)
0052 #define EDMACSH     (0x17|0x00)
0053 /* Bank 1 registers */
0054 #define EHT0        (0x00|0x20)
0055 #define EHT1        (0x01|0x20)
0056 #define EHT2        (0x02|0x20)
0057 #define EHT3        (0x03|0x20)
0058 #define EHT4        (0x04|0x20)
0059 #define EHT5        (0x05|0x20)
0060 #define EHT6        (0x06|0x20)
0061 #define EHT7        (0x07|0x20)
0062 #define EPMM0       (0x08|0x20)
0063 #define EPMM1       (0x09|0x20)
0064 #define EPMM2       (0x0A|0x20)
0065 #define EPMM3       (0x0B|0x20)
0066 #define EPMM4       (0x0C|0x20)
0067 #define EPMM5       (0x0D|0x20)
0068 #define EPMM6       (0x0E|0x20)
0069 #define EPMM7       (0x0F|0x20)
0070 #define EPMCSL      (0x10|0x20)
0071 #define EPMCSH      (0x11|0x20)
0072 #define EPMOL       (0x14|0x20)
0073 #define EPMOH       (0x15|0x20)
0074 #define EWOLIE      (0x16|0x20)
0075 #define EWOLIR      (0x17|0x20)
0076 #define ERXFCON     (0x18|0x20)
0077 #define EPKTCNT     (0x19|0x20)
0078 /* Bank 2 registers */
0079 #define MACON1      (0x00|0x40|SPRD_MASK)
0080 /* #define MACON2   (0x01|0x40|SPRD_MASK) */
0081 #define MACON3      (0x02|0x40|SPRD_MASK)
0082 #define MACON4      (0x03|0x40|SPRD_MASK)
0083 #define MABBIPG     (0x04|0x40|SPRD_MASK)
0084 #define MAIPGL      (0x06|0x40|SPRD_MASK)
0085 #define MAIPGH      (0x07|0x40|SPRD_MASK)
0086 #define MACLCON1    (0x08|0x40|SPRD_MASK)
0087 #define MACLCON2    (0x09|0x40|SPRD_MASK)
0088 #define MAMXFLL     (0x0A|0x40|SPRD_MASK)
0089 #define MAMXFLH     (0x0B|0x40|SPRD_MASK)
0090 #define MAPHSUP     (0x0D|0x40|SPRD_MASK)
0091 #define MICON       (0x11|0x40|SPRD_MASK)
0092 #define MICMD       (0x12|0x40|SPRD_MASK)
0093 #define MIREGADR    (0x14|0x40|SPRD_MASK)
0094 #define MIWRL       (0x16|0x40|SPRD_MASK)
0095 #define MIWRH       (0x17|0x40|SPRD_MASK)
0096 #define MIRDL       (0x18|0x40|SPRD_MASK)
0097 #define MIRDH       (0x19|0x40|SPRD_MASK)
0098 /* Bank 3 registers */
0099 #define MAADR1      (0x00|0x60|SPRD_MASK)
0100 #define MAADR0      (0x01|0x60|SPRD_MASK)
0101 #define MAADR3      (0x02|0x60|SPRD_MASK)
0102 #define MAADR2      (0x03|0x60|SPRD_MASK)
0103 #define MAADR5      (0x04|0x60|SPRD_MASK)
0104 #define MAADR4      (0x05|0x60|SPRD_MASK)
0105 #define EBSTSD      (0x06|0x60)
0106 #define EBSTCON     (0x07|0x60)
0107 #define EBSTCSL     (0x08|0x60)
0108 #define EBSTCSH     (0x09|0x60)
0109 #define MISTAT      (0x0A|0x60|SPRD_MASK)
0110 #define EREVID      (0x12|0x60)
0111 #define ECOCON      (0x15|0x60)
0112 #define EFLOCON     (0x17|0x60)
0113 #define EPAUSL      (0x18|0x60)
0114 #define EPAUSH      (0x19|0x60)
0115 /* PHY registers */
0116 #define PHCON1      0x00
0117 #define PHSTAT1     0x01
0118 #define PHHID1      0x02
0119 #define PHHID2      0x03
0120 #define PHCON2      0x10
0121 #define PHSTAT2     0x11
0122 #define PHIE        0x12
0123 #define PHIR        0x13
0124 #define PHLCON      0x14
0125 
0126 /* ENC28J60 EIE Register Bit Definitions */
0127 #define EIE_INTIE   0x80
0128 #define EIE_PKTIE   0x40
0129 #define EIE_DMAIE   0x20
0130 #define EIE_LINKIE  0x10
0131 #define EIE_TXIE    0x08
0132 /* #define EIE_WOLIE    0x04 (reserved) */
0133 #define EIE_TXERIE  0x02
0134 #define EIE_RXERIE  0x01
0135 /* ENC28J60 EIR Register Bit Definitions */
0136 #define EIR_PKTIF   0x40
0137 #define EIR_DMAIF   0x20
0138 #define EIR_LINKIF  0x10
0139 #define EIR_TXIF    0x08
0140 /* #define EIR_WOLIF    0x04 (reserved) */
0141 #define EIR_TXERIF  0x02
0142 #define EIR_RXERIF  0x01
0143 /* ENC28J60 ESTAT Register Bit Definitions */
0144 #define ESTAT_INT   0x80
0145 #define ESTAT_LATECOL   0x10
0146 #define ESTAT_RXBUSY    0x04
0147 #define ESTAT_TXABRT    0x02
0148 #define ESTAT_CLKRDY    0x01
0149 /* ENC28J60 ECON2 Register Bit Definitions */
0150 #define ECON2_AUTOINC   0x80
0151 #define ECON2_PKTDEC    0x40
0152 #define ECON2_PWRSV 0x20
0153 #define ECON2_VRPS  0x08
0154 /* ENC28J60 ECON1 Register Bit Definitions */
0155 #define ECON1_TXRST 0x80
0156 #define ECON1_RXRST 0x40
0157 #define ECON1_DMAST 0x20
0158 #define ECON1_CSUMEN    0x10
0159 #define ECON1_TXRTS 0x08
0160 #define ECON1_RXEN  0x04
0161 #define ECON1_BSEL1 0x02
0162 #define ECON1_BSEL0 0x01
0163 /* ENC28J60 MACON1 Register Bit Definitions */
0164 #define MACON1_LOOPBK   0x10
0165 #define MACON1_TXPAUS   0x08
0166 #define MACON1_RXPAUS   0x04
0167 #define MACON1_PASSALL  0x02
0168 #define MACON1_MARXEN   0x01
0169 /* ENC28J60 MACON2 Register Bit Definitions */
0170 #define MACON2_MARST    0x80
0171 #define MACON2_RNDRST   0x40
0172 #define MACON2_MARXRST  0x08
0173 #define MACON2_RFUNRST  0x04
0174 #define MACON2_MATXRST  0x02
0175 #define MACON2_TFUNRST  0x01
0176 /* ENC28J60 MACON3 Register Bit Definitions */
0177 #define MACON3_PADCFG2  0x80
0178 #define MACON3_PADCFG1  0x40
0179 #define MACON3_PADCFG0  0x20
0180 #define MACON3_TXCRCEN  0x10
0181 #define MACON3_PHDRLEN  0x08
0182 #define MACON3_HFRMLEN  0x04
0183 #define MACON3_FRMLNEN  0x02
0184 #define MACON3_FULDPX   0x01
0185 /* ENC28J60 MICMD Register Bit Definitions */
0186 #define MICMD_MIISCAN   0x02
0187 #define MICMD_MIIRD 0x01
0188 /* ENC28J60 MISTAT Register Bit Definitions */
0189 #define MISTAT_NVALID   0x04
0190 #define MISTAT_SCAN 0x02
0191 #define MISTAT_BUSY 0x01
0192 /* ENC28J60 ERXFCON Register Bit Definitions */
0193 #define ERXFCON_UCEN    0x80
0194 #define ERXFCON_ANDOR   0x40
0195 #define ERXFCON_CRCEN   0x20
0196 #define ERXFCON_PMEN    0x10
0197 #define ERXFCON_MPEN    0x08
0198 #define ERXFCON_HTEN    0x04
0199 #define ERXFCON_MCEN    0x02
0200 #define ERXFCON_BCEN    0x01
0201 
0202 /* ENC28J60 PHY PHCON1 Register Bit Definitions */
0203 #define PHCON1_PRST 0x8000
0204 #define PHCON1_PLOOPBK  0x4000
0205 #define PHCON1_PPWRSV   0x0800
0206 #define PHCON1_PDPXMD   0x0100
0207 /* ENC28J60 PHY PHSTAT1 Register Bit Definitions */
0208 #define PHSTAT1_PFDPX   0x1000
0209 #define PHSTAT1_PHDPX   0x0800
0210 #define PHSTAT1_LLSTAT  0x0004
0211 #define PHSTAT1_JBSTAT  0x0002
0212 /* ENC28J60 PHY PHSTAT2 Register Bit Definitions */
0213 #define PHSTAT2_TXSTAT  (1 << 13)
0214 #define PHSTAT2_RXSTAT  (1 << 12)
0215 #define PHSTAT2_COLSTAT (1 << 11)
0216 #define PHSTAT2_LSTAT   (1 << 10)
0217 #define PHSTAT2_DPXSTAT (1 << 9)
0218 #define PHSTAT2_PLRITY  (1 << 5)
0219 /* ENC28J60 PHY PHCON2 Register Bit Definitions */
0220 #define PHCON2_FRCLINK  0x4000
0221 #define PHCON2_TXDIS    0x2000
0222 #define PHCON2_JABBER   0x0400
0223 #define PHCON2_HDLDIS   0x0100
0224 /* ENC28J60 PHY PHIE Register Bit Definitions */
0225 #define PHIE_PLNKIE (1 << 4)
0226 #define PHIE_PGEIE  (1 << 1)
0227 /* ENC28J60 PHY PHIR Register Bit Definitions */
0228 #define PHIR_PLNKIF (1 << 4)
0229 #define PHIR_PGEIF  (1 << 1)
0230 
0231 /* ENC28J60 Packet Control Byte Bit Definitions */
0232 #define PKTCTRL_PHUGEEN     0x08
0233 #define PKTCTRL_PPADEN      0x04
0234 #define PKTCTRL_PCRCEN      0x02
0235 #define PKTCTRL_POVERRIDE   0x01
0236 
0237 /* ENC28J60 Transmit Status Vector */
0238 #define TSV_TXBYTECNT       0
0239 #define TSV_TXCOLLISIONCNT  16
0240 #define TSV_TXCRCERROR      20
0241 #define TSV_TXLENCHKERROR   21
0242 #define TSV_TXLENOUTOFRANGE 22
0243 #define TSV_TXDONE      23
0244 #define TSV_TXMULTICAST     24
0245 #define TSV_TXBROADCAST     25
0246 #define TSV_TXPACKETDEFER   26
0247 #define TSV_TXEXDEFER       27
0248 #define TSV_TXEXCOLLISION   28
0249 #define TSV_TXLATECOLLISION 29
0250 #define TSV_TXGIANT     30
0251 #define TSV_TXUNDERRUN      31
0252 #define TSV_TOTBYTETXONWIRE 32
0253 #define TSV_TXCONTROLFRAME  48
0254 #define TSV_TXPAUSEFRAME    49
0255 #define TSV_BACKPRESSUREAPP 50
0256 #define TSV_TXVLANTAGFRAME  51
0257 
0258 #define TSV_SIZE        7
0259 #define TSV_BYTEOF(x)       ((x) / 8)
0260 #define TSV_BITMASK(x)      (1 << ((x) % 8))
0261 #define TSV_GETBIT(x, y)    (((x)[TSV_BYTEOF(y)] & TSV_BITMASK(y)) ? 1 : 0)
0262 
0263 /* ENC28J60 Receive Status Vector */
0264 #define RSV_RXLONGEVDROPEV  16
0265 #define RSV_CARRIEREV       18
0266 #define RSV_CRCERROR        20
0267 #define RSV_LENCHECKERR     21
0268 #define RSV_LENOUTOFRANGE   22
0269 #define RSV_RXOK        23
0270 #define RSV_RXMULTICAST     24
0271 #define RSV_RXBROADCAST     25
0272 #define RSV_DRIBBLENIBBLE   26
0273 #define RSV_RXCONTROLFRAME  27
0274 #define RSV_RXPAUSEFRAME    28
0275 #define RSV_RXUNKNOWNOPCODE 29
0276 #define RSV_RXTYPEVLAN      30
0277 
0278 #define RSV_SIZE        6
0279 #define RSV_BITMASK(x)      (1 << ((x) - 16))
0280 #define RSV_GETBIT(x, y)    (((x) & RSV_BITMASK(y)) ? 1 : 0)
0281 
0282 
0283 /* SPI operation codes */
0284 #define ENC28J60_READ_CTRL_REG  0x00
0285 #define ENC28J60_READ_BUF_MEM   0x3A
0286 #define ENC28J60_WRITE_CTRL_REG 0x40
0287 #define ENC28J60_WRITE_BUF_MEM  0x7A
0288 #define ENC28J60_BIT_FIELD_SET  0x80
0289 #define ENC28J60_BIT_FIELD_CLR  0xA0
0290 #define ENC28J60_SOFT_RESET 0xFF
0291 
0292 
0293 /* buffer boundaries applied to internal 8K ram
0294  * entire available packet buffer space is allocated.
0295  * Give TX buffer space for one full ethernet frame (~1500 bytes)
0296  * receive buffer gets the rest */
0297 #define TXSTART_INIT        0x1A00
0298 #define TXEND_INIT      0x1FFF
0299 
0300 /* Put RX buffer at 0 as suggested by the Errata datasheet */
0301 #define RXSTART_INIT        0x0000
0302 #define RXEND_INIT      0x19FF
0303 
0304 /* maximum ethernet frame length */
0305 #define MAX_FRAMELEN        1518
0306 
0307 /* Preferred half duplex: LEDA: Link status LEDB: Rx/Tx activity */
0308 #define ENC28J60_LAMPS_MODE 0x3476
0309 
0310 #endif
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