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0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * Microchip ENC28J60 ethernet driver (MAC + PHY)
0004  *
0005  * Copyright (C) 2007 Eurek srl
0006  * Author: Claudio Lanconelli <lanconelli.claudio@eptar.com>
0007  * based on enc28j60.c written by David Anders for 2.4 kernel version
0008  *
0009  * $Id: enc28j60.c,v 1.22 2007/12/20 10:47:01 claudio Exp $
0010  */
0011 
0012 #include <linux/module.h>
0013 #include <linux/kernel.h>
0014 #include <linux/types.h>
0015 #include <linux/fcntl.h>
0016 #include <linux/interrupt.h>
0017 #include <linux/property.h>
0018 #include <linux/string.h>
0019 #include <linux/errno.h>
0020 #include <linux/netdevice.h>
0021 #include <linux/etherdevice.h>
0022 #include <linux/ethtool.h>
0023 #include <linux/tcp.h>
0024 #include <linux/skbuff.h>
0025 #include <linux/delay.h>
0026 #include <linux/spi/spi.h>
0027 
0028 #include "enc28j60_hw.h"
0029 
0030 #define DRV_NAME    "enc28j60"
0031 #define DRV_VERSION "1.02"
0032 
0033 #define SPI_OPLEN   1
0034 
0035 #define ENC28J60_MSG_DEFAULT    \
0036     (NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN | NETIF_MSG_LINK)
0037 
0038 /* Buffer size required for the largest SPI transfer (i.e., reading a
0039  * frame).
0040  */
0041 #define SPI_TRANSFER_BUF_LEN    (4 + MAX_FRAMELEN)
0042 
0043 #define TX_TIMEOUT      (4 * HZ)
0044 
0045 /* Max TX retries in case of collision as suggested by errata datasheet */
0046 #define MAX_TX_RETRYCOUNT   16
0047 
0048 enum {
0049     RXFILTER_NORMAL,
0050     RXFILTER_MULTI,
0051     RXFILTER_PROMISC
0052 };
0053 
0054 /* Driver local data */
0055 struct enc28j60_net {
0056     struct net_device *netdev;
0057     struct spi_device *spi;
0058     struct mutex lock;
0059     struct sk_buff *tx_skb;
0060     struct work_struct tx_work;
0061     struct work_struct irq_work;
0062     struct work_struct setrx_work;
0063     struct work_struct restart_work;
0064     u8 bank;        /* current register bank selected */
0065     u16 next_pk_ptr;    /* next packet pointer within FIFO */
0066     u16 max_pk_counter; /* statistics: max packet counter */
0067     u16 tx_retry_count;
0068     bool hw_enable;
0069     bool full_duplex;
0070     int rxfilter;
0071     u32 msg_enable;
0072     u8 spi_transfer_buf[SPI_TRANSFER_BUF_LEN];
0073 };
0074 
0075 /* use ethtool to change the level for any given device */
0076 static struct {
0077     u32 msg_enable;
0078 } debug = { -1 };
0079 
0080 /*
0081  * SPI read buffer
0082  * Wait for the SPI transfer and copy received data to destination.
0083  */
0084 static int
0085 spi_read_buf(struct enc28j60_net *priv, int len, u8 *data)
0086 {
0087     struct device *dev = &priv->spi->dev;
0088     u8 *rx_buf = priv->spi_transfer_buf + 4;
0089     u8 *tx_buf = priv->spi_transfer_buf;
0090     struct spi_transfer tx = {
0091         .tx_buf = tx_buf,
0092         .len = SPI_OPLEN,
0093     };
0094     struct spi_transfer rx = {
0095         .rx_buf = rx_buf,
0096         .len = len,
0097     };
0098     struct spi_message msg;
0099     int ret;
0100 
0101     tx_buf[0] = ENC28J60_READ_BUF_MEM;
0102 
0103     spi_message_init(&msg);
0104     spi_message_add_tail(&tx, &msg);
0105     spi_message_add_tail(&rx, &msg);
0106 
0107     ret = spi_sync(priv->spi, &msg);
0108     if (ret == 0) {
0109         memcpy(data, rx_buf, len);
0110         ret = msg.status;
0111     }
0112     if (ret && netif_msg_drv(priv))
0113         dev_printk(KERN_DEBUG, dev, "%s() failed: ret = %d\n",
0114                __func__, ret);
0115 
0116     return ret;
0117 }
0118 
0119 /*
0120  * SPI write buffer
0121  */
0122 static int spi_write_buf(struct enc28j60_net *priv, int len, const u8 *data)
0123 {
0124     struct device *dev = &priv->spi->dev;
0125     int ret;
0126 
0127     if (len > SPI_TRANSFER_BUF_LEN - 1 || len <= 0)
0128         ret = -EINVAL;
0129     else {
0130         priv->spi_transfer_buf[0] = ENC28J60_WRITE_BUF_MEM;
0131         memcpy(&priv->spi_transfer_buf[1], data, len);
0132         ret = spi_write(priv->spi, priv->spi_transfer_buf, len + 1);
0133         if (ret && netif_msg_drv(priv))
0134             dev_printk(KERN_DEBUG, dev, "%s() failed: ret = %d\n",
0135                    __func__, ret);
0136     }
0137     return ret;
0138 }
0139 
0140 /*
0141  * basic SPI read operation
0142  */
0143 static u8 spi_read_op(struct enc28j60_net *priv, u8 op, u8 addr)
0144 {
0145     struct device *dev = &priv->spi->dev;
0146     u8 tx_buf[2];
0147     u8 rx_buf[4];
0148     u8 val = 0;
0149     int ret;
0150     int slen = SPI_OPLEN;
0151 
0152     /* do dummy read if needed */
0153     if (addr & SPRD_MASK)
0154         slen++;
0155 
0156     tx_buf[0] = op | (addr & ADDR_MASK);
0157     ret = spi_write_then_read(priv->spi, tx_buf, 1, rx_buf, slen);
0158     if (ret)
0159         dev_printk(KERN_DEBUG, dev, "%s() failed: ret = %d\n",
0160                __func__, ret);
0161     else
0162         val = rx_buf[slen - 1];
0163 
0164     return val;
0165 }
0166 
0167 /*
0168  * basic SPI write operation
0169  */
0170 static int spi_write_op(struct enc28j60_net *priv, u8 op, u8 addr, u8 val)
0171 {
0172     struct device *dev = &priv->spi->dev;
0173     int ret;
0174 
0175     priv->spi_transfer_buf[0] = op | (addr & ADDR_MASK);
0176     priv->spi_transfer_buf[1] = val;
0177     ret = spi_write(priv->spi, priv->spi_transfer_buf, 2);
0178     if (ret && netif_msg_drv(priv))
0179         dev_printk(KERN_DEBUG, dev, "%s() failed: ret = %d\n",
0180                __func__, ret);
0181     return ret;
0182 }
0183 
0184 static void enc28j60_soft_reset(struct enc28j60_net *priv)
0185 {
0186     spi_write_op(priv, ENC28J60_SOFT_RESET, 0, ENC28J60_SOFT_RESET);
0187     /* Errata workaround #1, CLKRDY check is unreliable,
0188      * delay at least 1 ms instead */
0189     udelay(2000);
0190 }
0191 
0192 /*
0193  * select the current register bank if necessary
0194  */
0195 static void enc28j60_set_bank(struct enc28j60_net *priv, u8 addr)
0196 {
0197     u8 b = (addr & BANK_MASK) >> 5;
0198 
0199     /* These registers (EIE, EIR, ESTAT, ECON2, ECON1)
0200      * are present in all banks, no need to switch bank.
0201      */
0202     if (addr >= EIE && addr <= ECON1)
0203         return;
0204 
0205     /* Clear or set each bank selection bit as needed */
0206     if ((b & ECON1_BSEL0) != (priv->bank & ECON1_BSEL0)) {
0207         if (b & ECON1_BSEL0)
0208             spi_write_op(priv, ENC28J60_BIT_FIELD_SET, ECON1,
0209                     ECON1_BSEL0);
0210         else
0211             spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, ECON1,
0212                     ECON1_BSEL0);
0213     }
0214     if ((b & ECON1_BSEL1) != (priv->bank & ECON1_BSEL1)) {
0215         if (b & ECON1_BSEL1)
0216             spi_write_op(priv, ENC28J60_BIT_FIELD_SET, ECON1,
0217                     ECON1_BSEL1);
0218         else
0219             spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, ECON1,
0220                     ECON1_BSEL1);
0221     }
0222     priv->bank = b;
0223 }
0224 
0225 /*
0226  * Register access routines through the SPI bus.
0227  * Every register access comes in two flavours:
0228  * - nolock_xxx: caller needs to invoke mutex_lock, usually to access
0229  *   atomically more than one register
0230  * - locked_xxx: caller doesn't need to invoke mutex_lock, single access
0231  *
0232  * Some registers can be accessed through the bit field clear and
0233  * bit field set to avoid a read modify write cycle.
0234  */
0235 
0236 /*
0237  * Register bit field Set
0238  */
0239 static void nolock_reg_bfset(struct enc28j60_net *priv, u8 addr, u8 mask)
0240 {
0241     enc28j60_set_bank(priv, addr);
0242     spi_write_op(priv, ENC28J60_BIT_FIELD_SET, addr, mask);
0243 }
0244 
0245 static void locked_reg_bfset(struct enc28j60_net *priv, u8 addr, u8 mask)
0246 {
0247     mutex_lock(&priv->lock);
0248     nolock_reg_bfset(priv, addr, mask);
0249     mutex_unlock(&priv->lock);
0250 }
0251 
0252 /*
0253  * Register bit field Clear
0254  */
0255 static void nolock_reg_bfclr(struct enc28j60_net *priv, u8 addr, u8 mask)
0256 {
0257     enc28j60_set_bank(priv, addr);
0258     spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, addr, mask);
0259 }
0260 
0261 static void locked_reg_bfclr(struct enc28j60_net *priv, u8 addr, u8 mask)
0262 {
0263     mutex_lock(&priv->lock);
0264     nolock_reg_bfclr(priv, addr, mask);
0265     mutex_unlock(&priv->lock);
0266 }
0267 
0268 /*
0269  * Register byte read
0270  */
0271 static int nolock_regb_read(struct enc28j60_net *priv, u8 address)
0272 {
0273     enc28j60_set_bank(priv, address);
0274     return spi_read_op(priv, ENC28J60_READ_CTRL_REG, address);
0275 }
0276 
0277 static int locked_regb_read(struct enc28j60_net *priv, u8 address)
0278 {
0279     int ret;
0280 
0281     mutex_lock(&priv->lock);
0282     ret = nolock_regb_read(priv, address);
0283     mutex_unlock(&priv->lock);
0284 
0285     return ret;
0286 }
0287 
0288 /*
0289  * Register word read
0290  */
0291 static int nolock_regw_read(struct enc28j60_net *priv, u8 address)
0292 {
0293     int rl, rh;
0294 
0295     enc28j60_set_bank(priv, address);
0296     rl = spi_read_op(priv, ENC28J60_READ_CTRL_REG, address);
0297     rh = spi_read_op(priv, ENC28J60_READ_CTRL_REG, address + 1);
0298 
0299     return (rh << 8) | rl;
0300 }
0301 
0302 static int locked_regw_read(struct enc28j60_net *priv, u8 address)
0303 {
0304     int ret;
0305 
0306     mutex_lock(&priv->lock);
0307     ret = nolock_regw_read(priv, address);
0308     mutex_unlock(&priv->lock);
0309 
0310     return ret;
0311 }
0312 
0313 /*
0314  * Register byte write
0315  */
0316 static void nolock_regb_write(struct enc28j60_net *priv, u8 address, u8 data)
0317 {
0318     enc28j60_set_bank(priv, address);
0319     spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, address, data);
0320 }
0321 
0322 static void locked_regb_write(struct enc28j60_net *priv, u8 address, u8 data)
0323 {
0324     mutex_lock(&priv->lock);
0325     nolock_regb_write(priv, address, data);
0326     mutex_unlock(&priv->lock);
0327 }
0328 
0329 /*
0330  * Register word write
0331  */
0332 static void nolock_regw_write(struct enc28j60_net *priv, u8 address, u16 data)
0333 {
0334     enc28j60_set_bank(priv, address);
0335     spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, address, (u8) data);
0336     spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, address + 1,
0337              (u8) (data >> 8));
0338 }
0339 
0340 static void locked_regw_write(struct enc28j60_net *priv, u8 address, u16 data)
0341 {
0342     mutex_lock(&priv->lock);
0343     nolock_regw_write(priv, address, data);
0344     mutex_unlock(&priv->lock);
0345 }
0346 
0347 /*
0348  * Buffer memory read
0349  * Select the starting address and execute a SPI buffer read.
0350  */
0351 static void enc28j60_mem_read(struct enc28j60_net *priv, u16 addr, int len,
0352                   u8 *data)
0353 {
0354     mutex_lock(&priv->lock);
0355     nolock_regw_write(priv, ERDPTL, addr);
0356 #ifdef CONFIG_ENC28J60_WRITEVERIFY
0357     if (netif_msg_drv(priv)) {
0358         struct device *dev = &priv->spi->dev;
0359         u16 reg;
0360 
0361         reg = nolock_regw_read(priv, ERDPTL);
0362         if (reg != addr)
0363             dev_printk(KERN_DEBUG, dev,
0364                    "%s() error writing ERDPT (0x%04x - 0x%04x)\n",
0365                    __func__, reg, addr);
0366     }
0367 #endif
0368     spi_read_buf(priv, len, data);
0369     mutex_unlock(&priv->lock);
0370 }
0371 
0372 /*
0373  * Write packet to enc28j60 TX buffer memory
0374  */
0375 static void
0376 enc28j60_packet_write(struct enc28j60_net *priv, int len, const u8 *data)
0377 {
0378     struct device *dev = &priv->spi->dev;
0379 
0380     mutex_lock(&priv->lock);
0381     /* Set the write pointer to start of transmit buffer area */
0382     nolock_regw_write(priv, EWRPTL, TXSTART_INIT);
0383 #ifdef CONFIG_ENC28J60_WRITEVERIFY
0384     if (netif_msg_drv(priv)) {
0385         u16 reg;
0386         reg = nolock_regw_read(priv, EWRPTL);
0387         if (reg != TXSTART_INIT)
0388             dev_printk(KERN_DEBUG, dev,
0389                    "%s() ERWPT:0x%04x != 0x%04x\n",
0390                    __func__, reg, TXSTART_INIT);
0391     }
0392 #endif
0393     /* Set the TXND pointer to correspond to the packet size given */
0394     nolock_regw_write(priv, ETXNDL, TXSTART_INIT + len);
0395     /* write per-packet control byte */
0396     spi_write_op(priv, ENC28J60_WRITE_BUF_MEM, 0, 0x00);
0397     if (netif_msg_hw(priv))
0398         dev_printk(KERN_DEBUG, dev,
0399                "%s() after control byte ERWPT:0x%04x\n",
0400                __func__, nolock_regw_read(priv, EWRPTL));
0401     /* copy the packet into the transmit buffer */
0402     spi_write_buf(priv, len, data);
0403     if (netif_msg_hw(priv))
0404         dev_printk(KERN_DEBUG, dev,
0405                "%s() after write packet ERWPT:0x%04x, len=%d\n",
0406                __func__, nolock_regw_read(priv, EWRPTL), len);
0407     mutex_unlock(&priv->lock);
0408 }
0409 
0410 static int poll_ready(struct enc28j60_net *priv, u8 reg, u8 mask, u8 val)
0411 {
0412     struct device *dev = &priv->spi->dev;
0413     unsigned long timeout = jiffies + msecs_to_jiffies(20);
0414 
0415     /* 20 msec timeout read */
0416     while ((nolock_regb_read(priv, reg) & mask) != val) {
0417         if (time_after(jiffies, timeout)) {
0418             if (netif_msg_drv(priv))
0419                 dev_dbg(dev, "reg %02x ready timeout!\n", reg);
0420             return -ETIMEDOUT;
0421         }
0422         cpu_relax();
0423     }
0424     return 0;
0425 }
0426 
0427 /*
0428  * Wait until the PHY operation is complete.
0429  */
0430 static int wait_phy_ready(struct enc28j60_net *priv)
0431 {
0432     return poll_ready(priv, MISTAT, MISTAT_BUSY, 0) ? 0 : 1;
0433 }
0434 
0435 /*
0436  * PHY register read
0437  * PHY registers are not accessed directly, but through the MII.
0438  */
0439 static u16 enc28j60_phy_read(struct enc28j60_net *priv, u8 address)
0440 {
0441     u16 ret;
0442 
0443     mutex_lock(&priv->lock);
0444     /* set the PHY register address */
0445     nolock_regb_write(priv, MIREGADR, address);
0446     /* start the register read operation */
0447     nolock_regb_write(priv, MICMD, MICMD_MIIRD);
0448     /* wait until the PHY read completes */
0449     wait_phy_ready(priv);
0450     /* quit reading */
0451     nolock_regb_write(priv, MICMD, 0x00);
0452     /* return the data */
0453     ret = nolock_regw_read(priv, MIRDL);
0454     mutex_unlock(&priv->lock);
0455 
0456     return ret;
0457 }
0458 
0459 static int enc28j60_phy_write(struct enc28j60_net *priv, u8 address, u16 data)
0460 {
0461     int ret;
0462 
0463     mutex_lock(&priv->lock);
0464     /* set the PHY register address */
0465     nolock_regb_write(priv, MIREGADR, address);
0466     /* write the PHY data */
0467     nolock_regw_write(priv, MIWRL, data);
0468     /* wait until the PHY write completes and return */
0469     ret = wait_phy_ready(priv);
0470     mutex_unlock(&priv->lock);
0471 
0472     return ret;
0473 }
0474 
0475 /*
0476  * Program the hardware MAC address from dev->dev_addr.
0477  */
0478 static int enc28j60_set_hw_macaddr(struct net_device *ndev)
0479 {
0480     int ret;
0481     struct enc28j60_net *priv = netdev_priv(ndev);
0482     struct device *dev = &priv->spi->dev;
0483 
0484     mutex_lock(&priv->lock);
0485     if (!priv->hw_enable) {
0486         if (netif_msg_drv(priv))
0487             dev_info(dev, "%s: Setting MAC address to %pM\n",
0488                  ndev->name, ndev->dev_addr);
0489         /* NOTE: MAC address in ENC28J60 is byte-backward */
0490         nolock_regb_write(priv, MAADR5, ndev->dev_addr[0]);
0491         nolock_regb_write(priv, MAADR4, ndev->dev_addr[1]);
0492         nolock_regb_write(priv, MAADR3, ndev->dev_addr[2]);
0493         nolock_regb_write(priv, MAADR2, ndev->dev_addr[3]);
0494         nolock_regb_write(priv, MAADR1, ndev->dev_addr[4]);
0495         nolock_regb_write(priv, MAADR0, ndev->dev_addr[5]);
0496         ret = 0;
0497     } else {
0498         if (netif_msg_drv(priv))
0499             dev_printk(KERN_DEBUG, dev,
0500                    "%s() Hardware must be disabled to set Mac address\n",
0501                    __func__);
0502         ret = -EBUSY;
0503     }
0504     mutex_unlock(&priv->lock);
0505     return ret;
0506 }
0507 
0508 /*
0509  * Store the new hardware address in dev->dev_addr, and update the MAC.
0510  */
0511 static int enc28j60_set_mac_address(struct net_device *dev, void *addr)
0512 {
0513     struct sockaddr *address = addr;
0514 
0515     if (netif_running(dev))
0516         return -EBUSY;
0517     if (!is_valid_ether_addr(address->sa_data))
0518         return -EADDRNOTAVAIL;
0519 
0520     eth_hw_addr_set(dev, address->sa_data);
0521     return enc28j60_set_hw_macaddr(dev);
0522 }
0523 
0524 /*
0525  * Debug routine to dump useful register contents
0526  */
0527 static void enc28j60_dump_regs(struct enc28j60_net *priv, const char *msg)
0528 {
0529     struct device *dev = &priv->spi->dev;
0530 
0531     mutex_lock(&priv->lock);
0532     dev_printk(KERN_DEBUG, dev,
0533            " %s\n"
0534            "HwRevID: 0x%02x\n"
0535            "Cntrl: ECON1 ECON2 ESTAT  EIR  EIE\n"
0536            "       0x%02x  0x%02x  0x%02x  0x%02x  0x%02x\n"
0537            "MAC  : MACON1 MACON3 MACON4\n"
0538            "       0x%02x   0x%02x   0x%02x\n"
0539            "Rx   : ERXST  ERXND  ERXWRPT ERXRDPT ERXFCON EPKTCNT MAMXFL\n"
0540            "       0x%04x 0x%04x 0x%04x  0x%04x  "
0541            "0x%02x    0x%02x    0x%04x\n"
0542            "Tx   : ETXST  ETXND  MACLCON1 MACLCON2 MAPHSUP\n"
0543            "       0x%04x 0x%04x 0x%02x     0x%02x     0x%02x\n",
0544            msg, nolock_regb_read(priv, EREVID),
0545            nolock_regb_read(priv, ECON1), nolock_regb_read(priv, ECON2),
0546            nolock_regb_read(priv, ESTAT), nolock_regb_read(priv, EIR),
0547            nolock_regb_read(priv, EIE), nolock_regb_read(priv, MACON1),
0548            nolock_regb_read(priv, MACON3), nolock_regb_read(priv, MACON4),
0549            nolock_regw_read(priv, ERXSTL), nolock_regw_read(priv, ERXNDL),
0550            nolock_regw_read(priv, ERXWRPTL),
0551            nolock_regw_read(priv, ERXRDPTL),
0552            nolock_regb_read(priv, ERXFCON),
0553            nolock_regb_read(priv, EPKTCNT),
0554            nolock_regw_read(priv, MAMXFLL), nolock_regw_read(priv, ETXSTL),
0555            nolock_regw_read(priv, ETXNDL),
0556            nolock_regb_read(priv, MACLCON1),
0557            nolock_regb_read(priv, MACLCON2),
0558            nolock_regb_read(priv, MAPHSUP));
0559     mutex_unlock(&priv->lock);
0560 }
0561 
0562 /*
0563  * ERXRDPT need to be set always at odd addresses, refer to errata datasheet
0564  */
0565 static u16 erxrdpt_workaround(u16 next_packet_ptr, u16 start, u16 end)
0566 {
0567     u16 erxrdpt;
0568 
0569     if ((next_packet_ptr - 1 < start) || (next_packet_ptr - 1 > end))
0570         erxrdpt = end;
0571     else
0572         erxrdpt = next_packet_ptr - 1;
0573 
0574     return erxrdpt;
0575 }
0576 
0577 /*
0578  * Calculate wrap around when reading beyond the end of the RX buffer
0579  */
0580 static u16 rx_packet_start(u16 ptr)
0581 {
0582     if (ptr + RSV_SIZE > RXEND_INIT)
0583         return (ptr + RSV_SIZE) - (RXEND_INIT - RXSTART_INIT + 1);
0584     else
0585         return ptr + RSV_SIZE;
0586 }
0587 
0588 static void nolock_rxfifo_init(struct enc28j60_net *priv, u16 start, u16 end)
0589 {
0590     struct device *dev = &priv->spi->dev;
0591     u16 erxrdpt;
0592 
0593     if (start > 0x1FFF || end > 0x1FFF || start > end) {
0594         if (netif_msg_drv(priv))
0595             dev_err(dev, "%s(%d, %d) RXFIFO bad parameters!\n",
0596                 __func__, start, end);
0597         return;
0598     }
0599     /* set receive buffer start + end */
0600     priv->next_pk_ptr = start;
0601     nolock_regw_write(priv, ERXSTL, start);
0602     erxrdpt = erxrdpt_workaround(priv->next_pk_ptr, start, end);
0603     nolock_regw_write(priv, ERXRDPTL, erxrdpt);
0604     nolock_regw_write(priv, ERXNDL, end);
0605 }
0606 
0607 static void nolock_txfifo_init(struct enc28j60_net *priv, u16 start, u16 end)
0608 {
0609     struct device *dev = &priv->spi->dev;
0610 
0611     if (start > 0x1FFF || end > 0x1FFF || start > end) {
0612         if (netif_msg_drv(priv))
0613             dev_err(dev, "%s(%d, %d) TXFIFO bad parameters!\n",
0614                 __func__, start, end);
0615         return;
0616     }
0617     /* set transmit buffer start + end */
0618     nolock_regw_write(priv, ETXSTL, start);
0619     nolock_regw_write(priv, ETXNDL, end);
0620 }
0621 
0622 /*
0623  * Low power mode shrinks power consumption about 100x, so we'd like
0624  * the chip to be in that mode whenever it's inactive. (However, we
0625  * can't stay in low power mode during suspend with WOL active.)
0626  */
0627 static void enc28j60_lowpower(struct enc28j60_net *priv, bool is_low)
0628 {
0629     struct device *dev = &priv->spi->dev;
0630 
0631     if (netif_msg_drv(priv))
0632         dev_dbg(dev, "%s power...\n", is_low ? "low" : "high");
0633 
0634     mutex_lock(&priv->lock);
0635     if (is_low) {
0636         nolock_reg_bfclr(priv, ECON1, ECON1_RXEN);
0637         poll_ready(priv, ESTAT, ESTAT_RXBUSY, 0);
0638         poll_ready(priv, ECON1, ECON1_TXRTS, 0);
0639         /* ECON2_VRPS was set during initialization */
0640         nolock_reg_bfset(priv, ECON2, ECON2_PWRSV);
0641     } else {
0642         nolock_reg_bfclr(priv, ECON2, ECON2_PWRSV);
0643         poll_ready(priv, ESTAT, ESTAT_CLKRDY, ESTAT_CLKRDY);
0644         /* caller sets ECON1_RXEN */
0645     }
0646     mutex_unlock(&priv->lock);
0647 }
0648 
0649 static int enc28j60_hw_init(struct enc28j60_net *priv)
0650 {
0651     struct device *dev = &priv->spi->dev;
0652     u8 reg;
0653 
0654     if (netif_msg_drv(priv))
0655         dev_printk(KERN_DEBUG, dev, "%s() - %s\n", __func__,
0656                priv->full_duplex ? "FullDuplex" : "HalfDuplex");
0657 
0658     mutex_lock(&priv->lock);
0659     /* first reset the chip */
0660     enc28j60_soft_reset(priv);
0661     /* Clear ECON1 */
0662     spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, ECON1, 0x00);
0663     priv->bank = 0;
0664     priv->hw_enable = false;
0665     priv->tx_retry_count = 0;
0666     priv->max_pk_counter = 0;
0667     priv->rxfilter = RXFILTER_NORMAL;
0668     /* enable address auto increment and voltage regulator powersave */
0669     nolock_regb_write(priv, ECON2, ECON2_AUTOINC | ECON2_VRPS);
0670 
0671     nolock_rxfifo_init(priv, RXSTART_INIT, RXEND_INIT);
0672     nolock_txfifo_init(priv, TXSTART_INIT, TXEND_INIT);
0673     mutex_unlock(&priv->lock);
0674 
0675     /*
0676      * Check the RevID.
0677      * If it's 0x00 or 0xFF probably the enc28j60 is not mounted or
0678      * damaged.
0679      */
0680     reg = locked_regb_read(priv, EREVID);
0681     if (netif_msg_drv(priv))
0682         dev_info(dev, "chip RevID: 0x%02x\n", reg);
0683     if (reg == 0x00 || reg == 0xff) {
0684         if (netif_msg_drv(priv))
0685             dev_printk(KERN_DEBUG, dev, "%s() Invalid RevId %d\n",
0686                    __func__, reg);
0687         return 0;
0688     }
0689 
0690     /* default filter mode: (unicast OR broadcast) AND crc valid */
0691     locked_regb_write(priv, ERXFCON,
0692                 ERXFCON_UCEN | ERXFCON_CRCEN | ERXFCON_BCEN);
0693 
0694     /* enable MAC receive */
0695     locked_regb_write(priv, MACON1,
0696                 MACON1_MARXEN | MACON1_TXPAUS | MACON1_RXPAUS);
0697     /* enable automatic padding and CRC operations */
0698     if (priv->full_duplex) {
0699         locked_regb_write(priv, MACON3,
0700                     MACON3_PADCFG0 | MACON3_TXCRCEN |
0701                     MACON3_FRMLNEN | MACON3_FULDPX);
0702         /* set inter-frame gap (non-back-to-back) */
0703         locked_regb_write(priv, MAIPGL, 0x12);
0704         /* set inter-frame gap (back-to-back) */
0705         locked_regb_write(priv, MABBIPG, 0x15);
0706     } else {
0707         locked_regb_write(priv, MACON3,
0708                     MACON3_PADCFG0 | MACON3_TXCRCEN |
0709                     MACON3_FRMLNEN);
0710         locked_regb_write(priv, MACON4, 1 << 6);    /* DEFER bit */
0711         /* set inter-frame gap (non-back-to-back) */
0712         locked_regw_write(priv, MAIPGL, 0x0C12);
0713         /* set inter-frame gap (back-to-back) */
0714         locked_regb_write(priv, MABBIPG, 0x12);
0715     }
0716     /*
0717      * MACLCON1 (default)
0718      * MACLCON2 (default)
0719      * Set the maximum packet size which the controller will accept.
0720      */
0721     locked_regw_write(priv, MAMXFLL, MAX_FRAMELEN);
0722 
0723     /* Configure LEDs */
0724     if (!enc28j60_phy_write(priv, PHLCON, ENC28J60_LAMPS_MODE))
0725         return 0;
0726 
0727     if (priv->full_duplex) {
0728         if (!enc28j60_phy_write(priv, PHCON1, PHCON1_PDPXMD))
0729             return 0;
0730         if (!enc28j60_phy_write(priv, PHCON2, 0x00))
0731             return 0;
0732     } else {
0733         if (!enc28j60_phy_write(priv, PHCON1, 0x00))
0734             return 0;
0735         if (!enc28j60_phy_write(priv, PHCON2, PHCON2_HDLDIS))
0736             return 0;
0737     }
0738     if (netif_msg_hw(priv))
0739         enc28j60_dump_regs(priv, "Hw initialized.");
0740 
0741     return 1;
0742 }
0743 
0744 static void enc28j60_hw_enable(struct enc28j60_net *priv)
0745 {
0746     struct device *dev = &priv->spi->dev;
0747 
0748     /* enable interrupts */
0749     if (netif_msg_hw(priv))
0750         dev_printk(KERN_DEBUG, dev, "%s() enabling interrupts.\n",
0751                __func__);
0752 
0753     enc28j60_phy_write(priv, PHIE, PHIE_PGEIE | PHIE_PLNKIE);
0754 
0755     mutex_lock(&priv->lock);
0756     nolock_reg_bfclr(priv, EIR, EIR_DMAIF | EIR_LINKIF |
0757              EIR_TXIF | EIR_TXERIF | EIR_RXERIF | EIR_PKTIF);
0758     nolock_regb_write(priv, EIE, EIE_INTIE | EIE_PKTIE | EIE_LINKIE |
0759               EIE_TXIE | EIE_TXERIE | EIE_RXERIE);
0760 
0761     /* enable receive logic */
0762     nolock_reg_bfset(priv, ECON1, ECON1_RXEN);
0763     priv->hw_enable = true;
0764     mutex_unlock(&priv->lock);
0765 }
0766 
0767 static void enc28j60_hw_disable(struct enc28j60_net *priv)
0768 {
0769     mutex_lock(&priv->lock);
0770     /* disable interrupts and packet reception */
0771     nolock_regb_write(priv, EIE, 0x00);
0772     nolock_reg_bfclr(priv, ECON1, ECON1_RXEN);
0773     priv->hw_enable = false;
0774     mutex_unlock(&priv->lock);
0775 }
0776 
0777 static int
0778 enc28j60_setlink(struct net_device *ndev, u8 autoneg, u16 speed, u8 duplex)
0779 {
0780     struct enc28j60_net *priv = netdev_priv(ndev);
0781     int ret = 0;
0782 
0783     if (!priv->hw_enable) {
0784         /* link is in low power mode now; duplex setting
0785          * will take effect on next enc28j60_hw_init().
0786          */
0787         if (autoneg == AUTONEG_DISABLE && speed == SPEED_10)
0788             priv->full_duplex = (duplex == DUPLEX_FULL);
0789         else {
0790             if (netif_msg_link(priv))
0791                 netdev_warn(ndev, "unsupported link setting\n");
0792             ret = -EOPNOTSUPP;
0793         }
0794     } else {
0795         if (netif_msg_link(priv))
0796             netdev_warn(ndev, "Warning: hw must be disabled to set link mode\n");
0797         ret = -EBUSY;
0798     }
0799     return ret;
0800 }
0801 
0802 /*
0803  * Read the Transmit Status Vector
0804  */
0805 static void enc28j60_read_tsv(struct enc28j60_net *priv, u8 tsv[TSV_SIZE])
0806 {
0807     struct device *dev = &priv->spi->dev;
0808     int endptr;
0809 
0810     endptr = locked_regw_read(priv, ETXNDL);
0811     if (netif_msg_hw(priv))
0812         dev_printk(KERN_DEBUG, dev, "reading TSV at addr:0x%04x\n",
0813                endptr + 1);
0814     enc28j60_mem_read(priv, endptr + 1, TSV_SIZE, tsv);
0815 }
0816 
0817 static void enc28j60_dump_tsv(struct enc28j60_net *priv, const char *msg,
0818                   u8 tsv[TSV_SIZE])
0819 {
0820     struct device *dev = &priv->spi->dev;
0821     u16 tmp1, tmp2;
0822 
0823     dev_printk(KERN_DEBUG, dev, "%s - TSV:\n", msg);
0824     tmp1 = tsv[1];
0825     tmp1 <<= 8;
0826     tmp1 |= tsv[0];
0827 
0828     tmp2 = tsv[5];
0829     tmp2 <<= 8;
0830     tmp2 |= tsv[4];
0831 
0832     dev_printk(KERN_DEBUG, dev,
0833            "ByteCount: %d, CollisionCount: %d, TotByteOnWire: %d\n",
0834            tmp1, tsv[2] & 0x0f, tmp2);
0835     dev_printk(KERN_DEBUG, dev,
0836            "TxDone: %d, CRCErr:%d, LenChkErr: %d, LenOutOfRange: %d\n",
0837            TSV_GETBIT(tsv, TSV_TXDONE),
0838            TSV_GETBIT(tsv, TSV_TXCRCERROR),
0839            TSV_GETBIT(tsv, TSV_TXLENCHKERROR),
0840            TSV_GETBIT(tsv, TSV_TXLENOUTOFRANGE));
0841     dev_printk(KERN_DEBUG, dev,
0842            "Multicast: %d, Broadcast: %d, PacketDefer: %d, ExDefer: %d\n",
0843            TSV_GETBIT(tsv, TSV_TXMULTICAST),
0844            TSV_GETBIT(tsv, TSV_TXBROADCAST),
0845            TSV_GETBIT(tsv, TSV_TXPACKETDEFER),
0846            TSV_GETBIT(tsv, TSV_TXEXDEFER));
0847     dev_printk(KERN_DEBUG, dev,
0848            "ExCollision: %d, LateCollision: %d, Giant: %d, Underrun: %d\n",
0849            TSV_GETBIT(tsv, TSV_TXEXCOLLISION),
0850            TSV_GETBIT(tsv, TSV_TXLATECOLLISION),
0851            TSV_GETBIT(tsv, TSV_TXGIANT), TSV_GETBIT(tsv, TSV_TXUNDERRUN));
0852     dev_printk(KERN_DEBUG, dev,
0853            "ControlFrame: %d, PauseFrame: %d, BackPressApp: %d, VLanTagFrame: %d\n",
0854            TSV_GETBIT(tsv, TSV_TXCONTROLFRAME),
0855            TSV_GETBIT(tsv, TSV_TXPAUSEFRAME),
0856            TSV_GETBIT(tsv, TSV_BACKPRESSUREAPP),
0857            TSV_GETBIT(tsv, TSV_TXVLANTAGFRAME));
0858 }
0859 
0860 /*
0861  * Receive Status vector
0862  */
0863 static void enc28j60_dump_rsv(struct enc28j60_net *priv, const char *msg,
0864                   u16 pk_ptr, int len, u16 sts)
0865 {
0866     struct device *dev = &priv->spi->dev;
0867 
0868     dev_printk(KERN_DEBUG, dev, "%s - NextPk: 0x%04x - RSV:\n", msg, pk_ptr);
0869     dev_printk(KERN_DEBUG, dev, "ByteCount: %d, DribbleNibble: %d\n",
0870            len, RSV_GETBIT(sts, RSV_DRIBBLENIBBLE));
0871     dev_printk(KERN_DEBUG, dev,
0872            "RxOK: %d, CRCErr:%d, LenChkErr: %d, LenOutOfRange: %d\n",
0873            RSV_GETBIT(sts, RSV_RXOK),
0874            RSV_GETBIT(sts, RSV_CRCERROR),
0875            RSV_GETBIT(sts, RSV_LENCHECKERR),
0876            RSV_GETBIT(sts, RSV_LENOUTOFRANGE));
0877     dev_printk(KERN_DEBUG, dev,
0878            "Multicast: %d, Broadcast: %d, LongDropEvent: %d, CarrierEvent: %d\n",
0879            RSV_GETBIT(sts, RSV_RXMULTICAST),
0880            RSV_GETBIT(sts, RSV_RXBROADCAST),
0881            RSV_GETBIT(sts, RSV_RXLONGEVDROPEV),
0882            RSV_GETBIT(sts, RSV_CARRIEREV));
0883     dev_printk(KERN_DEBUG, dev,
0884            "ControlFrame: %d, PauseFrame: %d, UnknownOp: %d, VLanTagFrame: %d\n",
0885            RSV_GETBIT(sts, RSV_RXCONTROLFRAME),
0886            RSV_GETBIT(sts, RSV_RXPAUSEFRAME),
0887            RSV_GETBIT(sts, RSV_RXUNKNOWNOPCODE),
0888            RSV_GETBIT(sts, RSV_RXTYPEVLAN));
0889 }
0890 
0891 static void dump_packet(const char *msg, int len, const char *data)
0892 {
0893     printk(KERN_DEBUG DRV_NAME ": %s - packet len:%d\n", msg, len);
0894     print_hex_dump(KERN_DEBUG, "pk data: ", DUMP_PREFIX_OFFSET, 16, 1,
0895             data, len, true);
0896 }
0897 
0898 /*
0899  * Hardware receive function.
0900  * Read the buffer memory, update the FIFO pointer to free the buffer,
0901  * check the status vector and decrement the packet counter.
0902  */
0903 static void enc28j60_hw_rx(struct net_device *ndev)
0904 {
0905     struct enc28j60_net *priv = netdev_priv(ndev);
0906     struct device *dev = &priv->spi->dev;
0907     struct sk_buff *skb = NULL;
0908     u16 erxrdpt, next_packet, rxstat;
0909     u8 rsv[RSV_SIZE];
0910     int len;
0911 
0912     if (netif_msg_rx_status(priv))
0913         netdev_printk(KERN_DEBUG, ndev, "RX pk_addr:0x%04x\n",
0914                   priv->next_pk_ptr);
0915 
0916     if (unlikely(priv->next_pk_ptr > RXEND_INIT)) {
0917         if (netif_msg_rx_err(priv))
0918             netdev_err(ndev, "%s() Invalid packet address!! 0x%04x\n",
0919                    __func__, priv->next_pk_ptr);
0920         /* packet address corrupted: reset RX logic */
0921         mutex_lock(&priv->lock);
0922         nolock_reg_bfclr(priv, ECON1, ECON1_RXEN);
0923         nolock_reg_bfset(priv, ECON1, ECON1_RXRST);
0924         nolock_reg_bfclr(priv, ECON1, ECON1_RXRST);
0925         nolock_rxfifo_init(priv, RXSTART_INIT, RXEND_INIT);
0926         nolock_reg_bfclr(priv, EIR, EIR_RXERIF);
0927         nolock_reg_bfset(priv, ECON1, ECON1_RXEN);
0928         mutex_unlock(&priv->lock);
0929         ndev->stats.rx_errors++;
0930         return;
0931     }
0932     /* Read next packet pointer and rx status vector */
0933     enc28j60_mem_read(priv, priv->next_pk_ptr, sizeof(rsv), rsv);
0934 
0935     next_packet = rsv[1];
0936     next_packet <<= 8;
0937     next_packet |= rsv[0];
0938 
0939     len = rsv[3];
0940     len <<= 8;
0941     len |= rsv[2];
0942 
0943     rxstat = rsv[5];
0944     rxstat <<= 8;
0945     rxstat |= rsv[4];
0946 
0947     if (netif_msg_rx_status(priv))
0948         enc28j60_dump_rsv(priv, __func__, next_packet, len, rxstat);
0949 
0950     if (!RSV_GETBIT(rxstat, RSV_RXOK) || len > MAX_FRAMELEN) {
0951         if (netif_msg_rx_err(priv))
0952             netdev_err(ndev, "Rx Error (%04x)\n", rxstat);
0953         ndev->stats.rx_errors++;
0954         if (RSV_GETBIT(rxstat, RSV_CRCERROR))
0955             ndev->stats.rx_crc_errors++;
0956         if (RSV_GETBIT(rxstat, RSV_LENCHECKERR))
0957             ndev->stats.rx_frame_errors++;
0958         if (len > MAX_FRAMELEN)
0959             ndev->stats.rx_over_errors++;
0960     } else {
0961         skb = netdev_alloc_skb(ndev, len + NET_IP_ALIGN);
0962         if (!skb) {
0963             if (netif_msg_rx_err(priv))
0964                 netdev_err(ndev, "out of memory for Rx'd frame\n");
0965             ndev->stats.rx_dropped++;
0966         } else {
0967             skb_reserve(skb, NET_IP_ALIGN);
0968             /* copy the packet from the receive buffer */
0969             enc28j60_mem_read(priv,
0970                 rx_packet_start(priv->next_pk_ptr),
0971                 len, skb_put(skb, len));
0972             if (netif_msg_pktdata(priv))
0973                 dump_packet(__func__, skb->len, skb->data);
0974             skb->protocol = eth_type_trans(skb, ndev);
0975             /* update statistics */
0976             ndev->stats.rx_packets++;
0977             ndev->stats.rx_bytes += len;
0978             netif_rx(skb);
0979         }
0980     }
0981     /*
0982      * Move the RX read pointer to the start of the next
0983      * received packet.
0984      * This frees the memory we just read out.
0985      */
0986     erxrdpt = erxrdpt_workaround(next_packet, RXSTART_INIT, RXEND_INIT);
0987     if (netif_msg_hw(priv))
0988         dev_printk(KERN_DEBUG, dev, "%s() ERXRDPT:0x%04x\n",
0989                __func__, erxrdpt);
0990 
0991     mutex_lock(&priv->lock);
0992     nolock_regw_write(priv, ERXRDPTL, erxrdpt);
0993 #ifdef CONFIG_ENC28J60_WRITEVERIFY
0994     if (netif_msg_drv(priv)) {
0995         u16 reg;
0996         reg = nolock_regw_read(priv, ERXRDPTL);
0997         if (reg != erxrdpt)
0998             dev_printk(KERN_DEBUG, dev,
0999                    "%s() ERXRDPT verify error (0x%04x - 0x%04x)\n",
1000                    __func__, reg, erxrdpt);
1001     }
1002 #endif
1003     priv->next_pk_ptr = next_packet;
1004     /* we are done with this packet, decrement the packet counter */
1005     nolock_reg_bfset(priv, ECON2, ECON2_PKTDEC);
1006     mutex_unlock(&priv->lock);
1007 }
1008 
1009 /*
1010  * Calculate free space in RxFIFO
1011  */
1012 static int enc28j60_get_free_rxfifo(struct enc28j60_net *priv)
1013 {
1014     struct net_device *ndev = priv->netdev;
1015     int epkcnt, erxst, erxnd, erxwr, erxrd;
1016     int free_space;
1017 
1018     mutex_lock(&priv->lock);
1019     epkcnt = nolock_regb_read(priv, EPKTCNT);
1020     if (epkcnt >= 255)
1021         free_space = -1;
1022     else {
1023         erxst = nolock_regw_read(priv, ERXSTL);
1024         erxnd = nolock_regw_read(priv, ERXNDL);
1025         erxwr = nolock_regw_read(priv, ERXWRPTL);
1026         erxrd = nolock_regw_read(priv, ERXRDPTL);
1027 
1028         if (erxwr > erxrd)
1029             free_space = (erxnd - erxst) - (erxwr - erxrd);
1030         else if (erxwr == erxrd)
1031             free_space = (erxnd - erxst);
1032         else
1033             free_space = erxrd - erxwr - 1;
1034     }
1035     mutex_unlock(&priv->lock);
1036     if (netif_msg_rx_status(priv))
1037         netdev_printk(KERN_DEBUG, ndev, "%s() free_space = %d\n",
1038                   __func__, free_space);
1039     return free_space;
1040 }
1041 
1042 /*
1043  * Access the PHY to determine link status
1044  */
1045 static void enc28j60_check_link_status(struct net_device *ndev)
1046 {
1047     struct enc28j60_net *priv = netdev_priv(ndev);
1048     struct device *dev = &priv->spi->dev;
1049     u16 reg;
1050     int duplex;
1051 
1052     reg = enc28j60_phy_read(priv, PHSTAT2);
1053     if (netif_msg_hw(priv))
1054         dev_printk(KERN_DEBUG, dev,
1055                "%s() PHSTAT1: %04x, PHSTAT2: %04x\n", __func__,
1056                enc28j60_phy_read(priv, PHSTAT1), reg);
1057     duplex = reg & PHSTAT2_DPXSTAT;
1058 
1059     if (reg & PHSTAT2_LSTAT) {
1060         netif_carrier_on(ndev);
1061         if (netif_msg_ifup(priv))
1062             netdev_info(ndev, "link up - %s\n",
1063                     duplex ? "Full duplex" : "Half duplex");
1064     } else {
1065         if (netif_msg_ifdown(priv))
1066             netdev_info(ndev, "link down\n");
1067         netif_carrier_off(ndev);
1068     }
1069 }
1070 
1071 static void enc28j60_tx_clear(struct net_device *ndev, bool err)
1072 {
1073     struct enc28j60_net *priv = netdev_priv(ndev);
1074 
1075     if (err)
1076         ndev->stats.tx_errors++;
1077     else
1078         ndev->stats.tx_packets++;
1079 
1080     if (priv->tx_skb) {
1081         if (!err)
1082             ndev->stats.tx_bytes += priv->tx_skb->len;
1083         dev_kfree_skb(priv->tx_skb);
1084         priv->tx_skb = NULL;
1085     }
1086     locked_reg_bfclr(priv, ECON1, ECON1_TXRTS);
1087     netif_wake_queue(ndev);
1088 }
1089 
1090 /*
1091  * RX handler
1092  * Ignore PKTIF because is unreliable! (Look at the errata datasheet)
1093  * Check EPKTCNT is the suggested workaround.
1094  * We don't need to clear interrupt flag, automatically done when
1095  * enc28j60_hw_rx() decrements the packet counter.
1096  * Returns how many packet processed.
1097  */
1098 static int enc28j60_rx_interrupt(struct net_device *ndev)
1099 {
1100     struct enc28j60_net *priv = netdev_priv(ndev);
1101     int pk_counter, ret;
1102 
1103     pk_counter = locked_regb_read(priv, EPKTCNT);
1104     if (pk_counter && netif_msg_intr(priv))
1105         netdev_printk(KERN_DEBUG, ndev, "intRX, pk_cnt: %d\n",
1106                   pk_counter);
1107     if (pk_counter > priv->max_pk_counter) {
1108         /* update statistics */
1109         priv->max_pk_counter = pk_counter;
1110         if (netif_msg_rx_status(priv) && priv->max_pk_counter > 1)
1111             netdev_printk(KERN_DEBUG, ndev, "RX max_pk_cnt: %d\n",
1112                       priv->max_pk_counter);
1113     }
1114     ret = pk_counter;
1115     while (pk_counter-- > 0)
1116         enc28j60_hw_rx(ndev);
1117 
1118     return ret;
1119 }
1120 
1121 static void enc28j60_irq_work_handler(struct work_struct *work)
1122 {
1123     struct enc28j60_net *priv =
1124         container_of(work, struct enc28j60_net, irq_work);
1125     struct net_device *ndev = priv->netdev;
1126     int intflags, loop;
1127 
1128     /* disable further interrupts */
1129     locked_reg_bfclr(priv, EIE, EIE_INTIE);
1130 
1131     do {
1132         loop = 0;
1133         intflags = locked_regb_read(priv, EIR);
1134         /* DMA interrupt handler (not currently used) */
1135         if ((intflags & EIR_DMAIF) != 0) {
1136             loop++;
1137             if (netif_msg_intr(priv))
1138                 netdev_printk(KERN_DEBUG, ndev, "intDMA(%d)\n",
1139                           loop);
1140             locked_reg_bfclr(priv, EIR, EIR_DMAIF);
1141         }
1142         /* LINK changed handler */
1143         if ((intflags & EIR_LINKIF) != 0) {
1144             loop++;
1145             if (netif_msg_intr(priv))
1146                 netdev_printk(KERN_DEBUG, ndev, "intLINK(%d)\n",
1147                           loop);
1148             enc28j60_check_link_status(ndev);
1149             /* read PHIR to clear the flag */
1150             enc28j60_phy_read(priv, PHIR);
1151         }
1152         /* TX complete handler */
1153         if (((intflags & EIR_TXIF) != 0) &&
1154             ((intflags & EIR_TXERIF) == 0)) {
1155             bool err = false;
1156             loop++;
1157             if (netif_msg_intr(priv))
1158                 netdev_printk(KERN_DEBUG, ndev, "intTX(%d)\n",
1159                           loop);
1160             priv->tx_retry_count = 0;
1161             if (locked_regb_read(priv, ESTAT) & ESTAT_TXABRT) {
1162                 if (netif_msg_tx_err(priv))
1163                     netdev_err(ndev, "Tx Error (aborted)\n");
1164                 err = true;
1165             }
1166             if (netif_msg_tx_done(priv)) {
1167                 u8 tsv[TSV_SIZE];
1168                 enc28j60_read_tsv(priv, tsv);
1169                 enc28j60_dump_tsv(priv, "Tx Done", tsv);
1170             }
1171             enc28j60_tx_clear(ndev, err);
1172             locked_reg_bfclr(priv, EIR, EIR_TXIF);
1173         }
1174         /* TX Error handler */
1175         if ((intflags & EIR_TXERIF) != 0) {
1176             u8 tsv[TSV_SIZE];
1177 
1178             loop++;
1179             if (netif_msg_intr(priv))
1180                 netdev_printk(KERN_DEBUG, ndev, "intTXErr(%d)\n",
1181                           loop);
1182             locked_reg_bfclr(priv, ECON1, ECON1_TXRTS);
1183             enc28j60_read_tsv(priv, tsv);
1184             if (netif_msg_tx_err(priv))
1185                 enc28j60_dump_tsv(priv, "Tx Error", tsv);
1186             /* Reset TX logic */
1187             mutex_lock(&priv->lock);
1188             nolock_reg_bfset(priv, ECON1, ECON1_TXRST);
1189             nolock_reg_bfclr(priv, ECON1, ECON1_TXRST);
1190             nolock_txfifo_init(priv, TXSTART_INIT, TXEND_INIT);
1191             mutex_unlock(&priv->lock);
1192             /* Transmit Late collision check for retransmit */
1193             if (TSV_GETBIT(tsv, TSV_TXLATECOLLISION)) {
1194                 if (netif_msg_tx_err(priv))
1195                     netdev_printk(KERN_DEBUG, ndev,
1196                               "LateCollision TXErr (%d)\n",
1197                               priv->tx_retry_count);
1198                 if (priv->tx_retry_count++ < MAX_TX_RETRYCOUNT)
1199                     locked_reg_bfset(priv, ECON1,
1200                                ECON1_TXRTS);
1201                 else
1202                     enc28j60_tx_clear(ndev, true);
1203             } else
1204                 enc28j60_tx_clear(ndev, true);
1205             locked_reg_bfclr(priv, EIR, EIR_TXERIF | EIR_TXIF);
1206         }
1207         /* RX Error handler */
1208         if ((intflags & EIR_RXERIF) != 0) {
1209             loop++;
1210             if (netif_msg_intr(priv))
1211                 netdev_printk(KERN_DEBUG, ndev, "intRXErr(%d)\n",
1212                           loop);
1213             /* Check free FIFO space to flag RX overrun */
1214             if (enc28j60_get_free_rxfifo(priv) <= 0) {
1215                 if (netif_msg_rx_err(priv))
1216                     netdev_printk(KERN_DEBUG, ndev, "RX Overrun\n");
1217                 ndev->stats.rx_dropped++;
1218             }
1219             locked_reg_bfclr(priv, EIR, EIR_RXERIF);
1220         }
1221         /* RX handler */
1222         if (enc28j60_rx_interrupt(ndev))
1223             loop++;
1224     } while (loop);
1225 
1226     /* re-enable interrupts */
1227     locked_reg_bfset(priv, EIE, EIE_INTIE);
1228 }
1229 
1230 /*
1231  * Hardware transmit function.
1232  * Fill the buffer memory and send the contents of the transmit buffer
1233  * onto the network
1234  */
1235 static void enc28j60_hw_tx(struct enc28j60_net *priv)
1236 {
1237     struct net_device *ndev = priv->netdev;
1238 
1239     BUG_ON(!priv->tx_skb);
1240 
1241     if (netif_msg_tx_queued(priv))
1242         netdev_printk(KERN_DEBUG, ndev, "Tx Packet Len:%d\n",
1243                   priv->tx_skb->len);
1244 
1245     if (netif_msg_pktdata(priv))
1246         dump_packet(__func__,
1247                 priv->tx_skb->len, priv->tx_skb->data);
1248     enc28j60_packet_write(priv, priv->tx_skb->len, priv->tx_skb->data);
1249 
1250 #ifdef CONFIG_ENC28J60_WRITEVERIFY
1251     /* readback and verify written data */
1252     if (netif_msg_drv(priv)) {
1253         struct device *dev = &priv->spi->dev;
1254         int test_len, k;
1255         u8 test_buf[64]; /* limit the test to the first 64 bytes */
1256         int okflag;
1257 
1258         test_len = priv->tx_skb->len;
1259         if (test_len > sizeof(test_buf))
1260             test_len = sizeof(test_buf);
1261 
1262         /* + 1 to skip control byte */
1263         enc28j60_mem_read(priv, TXSTART_INIT + 1, test_len, test_buf);
1264         okflag = 1;
1265         for (k = 0; k < test_len; k++) {
1266             if (priv->tx_skb->data[k] != test_buf[k]) {
1267                 dev_printk(KERN_DEBUG, dev,
1268                        "Error, %d location differ: 0x%02x-0x%02x\n",
1269                        k, priv->tx_skb->data[k], test_buf[k]);
1270                 okflag = 0;
1271             }
1272         }
1273         if (!okflag)
1274             dev_printk(KERN_DEBUG, dev, "Tx write buffer, verify ERROR!\n");
1275     }
1276 #endif
1277     /* set TX request flag */
1278     locked_reg_bfset(priv, ECON1, ECON1_TXRTS);
1279 }
1280 
1281 static netdev_tx_t enc28j60_send_packet(struct sk_buff *skb,
1282                     struct net_device *dev)
1283 {
1284     struct enc28j60_net *priv = netdev_priv(dev);
1285 
1286     /* If some error occurs while trying to transmit this
1287      * packet, you should return '1' from this function.
1288      * In such a case you _may not_ do anything to the
1289      * SKB, it is still owned by the network queueing
1290      * layer when an error is returned. This means you
1291      * may not modify any SKB fields, you may not free
1292      * the SKB, etc.
1293      */
1294     netif_stop_queue(dev);
1295 
1296     /* Remember the skb for deferred processing */
1297     priv->tx_skb = skb;
1298     schedule_work(&priv->tx_work);
1299 
1300     return NETDEV_TX_OK;
1301 }
1302 
1303 static void enc28j60_tx_work_handler(struct work_struct *work)
1304 {
1305     struct enc28j60_net *priv =
1306         container_of(work, struct enc28j60_net, tx_work);
1307 
1308     /* actual delivery of data */
1309     enc28j60_hw_tx(priv);
1310 }
1311 
1312 static irqreturn_t enc28j60_irq(int irq, void *dev_id)
1313 {
1314     struct enc28j60_net *priv = dev_id;
1315 
1316     /*
1317      * Can't do anything in interrupt context because we need to
1318      * block (spi_sync() is blocking) so fire of the interrupt
1319      * handling workqueue.
1320      * Remember that we access enc28j60 registers through SPI bus
1321      * via spi_sync() call.
1322      */
1323     schedule_work(&priv->irq_work);
1324 
1325     return IRQ_HANDLED;
1326 }
1327 
1328 static void enc28j60_tx_timeout(struct net_device *ndev, unsigned int txqueue)
1329 {
1330     struct enc28j60_net *priv = netdev_priv(ndev);
1331 
1332     if (netif_msg_timer(priv))
1333         netdev_err(ndev, "tx timeout\n");
1334 
1335     ndev->stats.tx_errors++;
1336     /* can't restart safely under softirq */
1337     schedule_work(&priv->restart_work);
1338 }
1339 
1340 /*
1341  * Open/initialize the board. This is called (in the current kernel)
1342  * sometime after booting when the 'ifconfig' program is run.
1343  *
1344  * This routine should set everything up anew at each open, even
1345  * registers that "should" only need to be set once at boot, so that
1346  * there is non-reboot way to recover if something goes wrong.
1347  */
1348 static int enc28j60_net_open(struct net_device *dev)
1349 {
1350     struct enc28j60_net *priv = netdev_priv(dev);
1351 
1352     if (!is_valid_ether_addr(dev->dev_addr)) {
1353         if (netif_msg_ifup(priv))
1354             netdev_err(dev, "invalid MAC address %pM\n", dev->dev_addr);
1355         return -EADDRNOTAVAIL;
1356     }
1357     /* Reset the hardware here (and take it out of low power mode) */
1358     enc28j60_lowpower(priv, false);
1359     enc28j60_hw_disable(priv);
1360     if (!enc28j60_hw_init(priv)) {
1361         if (netif_msg_ifup(priv))
1362             netdev_err(dev, "hw_reset() failed\n");
1363         return -EINVAL;
1364     }
1365     /* Update the MAC address (in case user has changed it) */
1366     enc28j60_set_hw_macaddr(dev);
1367     /* Enable interrupts */
1368     enc28j60_hw_enable(priv);
1369     /* check link status */
1370     enc28j60_check_link_status(dev);
1371     /* We are now ready to accept transmit requests from
1372      * the queueing layer of the networking.
1373      */
1374     netif_start_queue(dev);
1375 
1376     return 0;
1377 }
1378 
1379 /* The inverse routine to net_open(). */
1380 static int enc28j60_net_close(struct net_device *dev)
1381 {
1382     struct enc28j60_net *priv = netdev_priv(dev);
1383 
1384     enc28j60_hw_disable(priv);
1385     enc28j60_lowpower(priv, true);
1386     netif_stop_queue(dev);
1387 
1388     return 0;
1389 }
1390 
1391 /*
1392  * Set or clear the multicast filter for this adapter
1393  * num_addrs == -1  Promiscuous mode, receive all packets
1394  * num_addrs == 0   Normal mode, filter out multicast packets
1395  * num_addrs > 0    Multicast mode, receive normal and MC packets
1396  */
1397 static void enc28j60_set_multicast_list(struct net_device *dev)
1398 {
1399     struct enc28j60_net *priv = netdev_priv(dev);
1400     int oldfilter = priv->rxfilter;
1401 
1402     if (dev->flags & IFF_PROMISC) {
1403         if (netif_msg_link(priv))
1404             netdev_info(dev, "promiscuous mode\n");
1405         priv->rxfilter = RXFILTER_PROMISC;
1406     } else if ((dev->flags & IFF_ALLMULTI) || !netdev_mc_empty(dev)) {
1407         if (netif_msg_link(priv))
1408             netdev_info(dev, "%smulticast mode\n",
1409                     (dev->flags & IFF_ALLMULTI) ? "all-" : "");
1410         priv->rxfilter = RXFILTER_MULTI;
1411     } else {
1412         if (netif_msg_link(priv))
1413             netdev_info(dev, "normal mode\n");
1414         priv->rxfilter = RXFILTER_NORMAL;
1415     }
1416 
1417     if (oldfilter != priv->rxfilter)
1418         schedule_work(&priv->setrx_work);
1419 }
1420 
1421 static void enc28j60_setrx_work_handler(struct work_struct *work)
1422 {
1423     struct enc28j60_net *priv =
1424         container_of(work, struct enc28j60_net, setrx_work);
1425     struct device *dev = &priv->spi->dev;
1426 
1427     if (priv->rxfilter == RXFILTER_PROMISC) {
1428         if (netif_msg_drv(priv))
1429             dev_printk(KERN_DEBUG, dev, "promiscuous mode\n");
1430         locked_regb_write(priv, ERXFCON, 0x00);
1431     } else if (priv->rxfilter == RXFILTER_MULTI) {
1432         if (netif_msg_drv(priv))
1433             dev_printk(KERN_DEBUG, dev, "multicast mode\n");
1434         locked_regb_write(priv, ERXFCON,
1435                     ERXFCON_UCEN | ERXFCON_CRCEN |
1436                     ERXFCON_BCEN | ERXFCON_MCEN);
1437     } else {
1438         if (netif_msg_drv(priv))
1439             dev_printk(KERN_DEBUG, dev, "normal mode\n");
1440         locked_regb_write(priv, ERXFCON,
1441                     ERXFCON_UCEN | ERXFCON_CRCEN |
1442                     ERXFCON_BCEN);
1443     }
1444 }
1445 
1446 static void enc28j60_restart_work_handler(struct work_struct *work)
1447 {
1448     struct enc28j60_net *priv =
1449             container_of(work, struct enc28j60_net, restart_work);
1450     struct net_device *ndev = priv->netdev;
1451     int ret;
1452 
1453     rtnl_lock();
1454     if (netif_running(ndev)) {
1455         enc28j60_net_close(ndev);
1456         ret = enc28j60_net_open(ndev);
1457         if (unlikely(ret)) {
1458             netdev_info(ndev, "could not restart %d\n", ret);
1459             dev_close(ndev);
1460         }
1461     }
1462     rtnl_unlock();
1463 }
1464 
1465 /* ......................... ETHTOOL SUPPORT ........................... */
1466 
1467 static void
1468 enc28j60_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1469 {
1470     strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
1471     strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1472     strlcpy(info->bus_info,
1473         dev_name(dev->dev.parent), sizeof(info->bus_info));
1474 }
1475 
1476 static int
1477 enc28j60_get_link_ksettings(struct net_device *dev,
1478                 struct ethtool_link_ksettings *cmd)
1479 {
1480     struct enc28j60_net *priv = netdev_priv(dev);
1481 
1482     ethtool_link_ksettings_zero_link_mode(cmd, supported);
1483     ethtool_link_ksettings_add_link_mode(cmd, supported, 10baseT_Half);
1484     ethtool_link_ksettings_add_link_mode(cmd, supported, 10baseT_Full);
1485     ethtool_link_ksettings_add_link_mode(cmd, supported, TP);
1486 
1487     cmd->base.speed = SPEED_10;
1488     cmd->base.duplex = priv->full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
1489     cmd->base.port  = PORT_TP;
1490     cmd->base.autoneg = AUTONEG_DISABLE;
1491 
1492     return 0;
1493 }
1494 
1495 static int
1496 enc28j60_set_link_ksettings(struct net_device *dev,
1497                 const struct ethtool_link_ksettings *cmd)
1498 {
1499     return enc28j60_setlink(dev, cmd->base.autoneg,
1500                 cmd->base.speed, cmd->base.duplex);
1501 }
1502 
1503 static u32 enc28j60_get_msglevel(struct net_device *dev)
1504 {
1505     struct enc28j60_net *priv = netdev_priv(dev);
1506     return priv->msg_enable;
1507 }
1508 
1509 static void enc28j60_set_msglevel(struct net_device *dev, u32 val)
1510 {
1511     struct enc28j60_net *priv = netdev_priv(dev);
1512     priv->msg_enable = val;
1513 }
1514 
1515 static const struct ethtool_ops enc28j60_ethtool_ops = {
1516     .get_drvinfo    = enc28j60_get_drvinfo,
1517     .get_msglevel   = enc28j60_get_msglevel,
1518     .set_msglevel   = enc28j60_set_msglevel,
1519     .get_link_ksettings = enc28j60_get_link_ksettings,
1520     .set_link_ksettings = enc28j60_set_link_ksettings,
1521 };
1522 
1523 static int enc28j60_chipset_init(struct net_device *dev)
1524 {
1525     struct enc28j60_net *priv = netdev_priv(dev);
1526 
1527     return enc28j60_hw_init(priv);
1528 }
1529 
1530 static const struct net_device_ops enc28j60_netdev_ops = {
1531     .ndo_open       = enc28j60_net_open,
1532     .ndo_stop       = enc28j60_net_close,
1533     .ndo_start_xmit     = enc28j60_send_packet,
1534     .ndo_set_rx_mode    = enc28j60_set_multicast_list,
1535     .ndo_set_mac_address    = enc28j60_set_mac_address,
1536     .ndo_tx_timeout     = enc28j60_tx_timeout,
1537     .ndo_validate_addr  = eth_validate_addr,
1538 };
1539 
1540 static int enc28j60_probe(struct spi_device *spi)
1541 {
1542     struct net_device *dev;
1543     struct enc28j60_net *priv;
1544     int ret = 0;
1545 
1546     if (netif_msg_drv(&debug))
1547         dev_info(&spi->dev, "Ethernet driver %s loaded\n", DRV_VERSION);
1548 
1549     dev = alloc_etherdev(sizeof(struct enc28j60_net));
1550     if (!dev) {
1551         ret = -ENOMEM;
1552         goto error_alloc;
1553     }
1554     priv = netdev_priv(dev);
1555 
1556     priv->netdev = dev; /* priv to netdev reference */
1557     priv->spi = spi;    /* priv to spi reference */
1558     priv->msg_enable = netif_msg_init(debug.msg_enable, ENC28J60_MSG_DEFAULT);
1559     mutex_init(&priv->lock);
1560     INIT_WORK(&priv->tx_work, enc28j60_tx_work_handler);
1561     INIT_WORK(&priv->setrx_work, enc28j60_setrx_work_handler);
1562     INIT_WORK(&priv->irq_work, enc28j60_irq_work_handler);
1563     INIT_WORK(&priv->restart_work, enc28j60_restart_work_handler);
1564     spi_set_drvdata(spi, priv); /* spi to priv reference */
1565     SET_NETDEV_DEV(dev, &spi->dev);
1566 
1567     if (!enc28j60_chipset_init(dev)) {
1568         if (netif_msg_probe(priv))
1569             dev_info(&spi->dev, "chip not found\n");
1570         ret = -EIO;
1571         goto error_irq;
1572     }
1573 
1574     if (device_get_ethdev_address(&spi->dev, dev))
1575         eth_hw_addr_random(dev);
1576     enc28j60_set_hw_macaddr(dev);
1577 
1578     /* Board setup must set the relevant edge trigger type;
1579      * level triggers won't currently work.
1580      */
1581     ret = request_irq(spi->irq, enc28j60_irq, 0, DRV_NAME, priv);
1582     if (ret < 0) {
1583         if (netif_msg_probe(priv))
1584             dev_err(&spi->dev, "request irq %d failed (ret = %d)\n",
1585                 spi->irq, ret);
1586         goto error_irq;
1587     }
1588 
1589     dev->if_port = IF_PORT_10BASET;
1590     dev->irq = spi->irq;
1591     dev->netdev_ops = &enc28j60_netdev_ops;
1592     dev->watchdog_timeo = TX_TIMEOUT;
1593     dev->ethtool_ops = &enc28j60_ethtool_ops;
1594 
1595     enc28j60_lowpower(priv, true);
1596 
1597     ret = register_netdev(dev);
1598     if (ret) {
1599         if (netif_msg_probe(priv))
1600             dev_err(&spi->dev, "register netdev failed (ret = %d)\n",
1601                 ret);
1602         goto error_register;
1603     }
1604 
1605     return 0;
1606 
1607 error_register:
1608     free_irq(spi->irq, priv);
1609 error_irq:
1610     free_netdev(dev);
1611 error_alloc:
1612     return ret;
1613 }
1614 
1615 static void enc28j60_remove(struct spi_device *spi)
1616 {
1617     struct enc28j60_net *priv = spi_get_drvdata(spi);
1618 
1619     unregister_netdev(priv->netdev);
1620     free_irq(spi->irq, priv);
1621     free_netdev(priv->netdev);
1622 }
1623 
1624 static const struct of_device_id enc28j60_dt_ids[] = {
1625     { .compatible = "microchip,enc28j60" },
1626     { /* sentinel */ }
1627 };
1628 MODULE_DEVICE_TABLE(of, enc28j60_dt_ids);
1629 
1630 static struct spi_driver enc28j60_driver = {
1631     .driver = {
1632         .name = DRV_NAME,
1633         .of_match_table = enc28j60_dt_ids,
1634      },
1635     .probe = enc28j60_probe,
1636     .remove = enc28j60_remove,
1637 };
1638 module_spi_driver(enc28j60_driver);
1639 
1640 MODULE_DESCRIPTION(DRV_NAME " ethernet driver");
1641 MODULE_AUTHOR("Claudio Lanconelli <lanconelli.claudio@eptar.com>");
1642 MODULE_LICENSE("GPL");
1643 module_param_named(debug, debug.msg_enable, int, 0);
1644 MODULE_PARM_DESC(debug, "Debug verbosity level in amount of bits set (0=none, ..., 31=all)");
1645 MODULE_ALIAS("spi:" DRV_NAME);
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