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0001 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
0002 /* Copyright (c) 2016-2018 Mellanox Technologies. All rights reserved */
0003 
0004 #include <linux/netdevice.h>
0005 #include <linux/string.h>
0006 #include <linux/bitops.h>
0007 #include <net/dcbnl.h>
0008 
0009 #include "spectrum.h"
0010 #include "reg.h"
0011 
0012 static u8 mlxsw_sp_dcbnl_getdcbx(struct net_device __always_unused *dev)
0013 {
0014     return DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_IEEE;
0015 }
0016 
0017 static u8 mlxsw_sp_dcbnl_setdcbx(struct net_device __always_unused *dev,
0018                  u8 mode)
0019 {
0020     return (mode != (DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_IEEE)) ? 1 : 0;
0021 }
0022 
0023 static int mlxsw_sp_dcbnl_ieee_getets(struct net_device *dev,
0024                       struct ieee_ets *ets)
0025 {
0026     struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
0027 
0028     memcpy(ets, mlxsw_sp_port->dcb.ets, sizeof(*ets));
0029 
0030     return 0;
0031 }
0032 
0033 static int mlxsw_sp_port_ets_validate(struct mlxsw_sp_port *mlxsw_sp_port,
0034                       struct ieee_ets *ets)
0035 {
0036     struct net_device *dev = mlxsw_sp_port->dev;
0037     bool has_ets_tc = false;
0038     int i, tx_bw_sum = 0;
0039 
0040     for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
0041         switch (ets->tc_tsa[i]) {
0042         case IEEE_8021QAZ_TSA_STRICT:
0043             break;
0044         case IEEE_8021QAZ_TSA_ETS:
0045             has_ets_tc = true;
0046             tx_bw_sum += ets->tc_tx_bw[i];
0047             break;
0048         default:
0049             netdev_err(dev, "Only strict priority and ETS are supported\n");
0050             return -EINVAL;
0051         }
0052 
0053         if (ets->prio_tc[i] >= IEEE_8021QAZ_MAX_TCS) {
0054             netdev_err(dev, "Invalid TC\n");
0055             return -EINVAL;
0056         }
0057     }
0058 
0059     if (has_ets_tc && tx_bw_sum != 100) {
0060         netdev_err(dev, "Total ETS bandwidth should equal 100\n");
0061         return -EINVAL;
0062     }
0063 
0064     return 0;
0065 }
0066 
0067 static int mlxsw_sp_port_headroom_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
0068                       struct ieee_ets *ets)
0069 {
0070     struct net_device *dev = mlxsw_sp_port->dev;
0071     struct mlxsw_sp_hdroom hdroom;
0072     int prio;
0073     int err;
0074 
0075     hdroom = *mlxsw_sp_port->hdroom;
0076     for (prio = 0; prio < IEEE_8021QAZ_MAX_TCS; prio++)
0077         hdroom.prios.prio[prio].ets_buf_idx = ets->prio_tc[prio];
0078     mlxsw_sp_hdroom_prios_reset_buf_idx(&hdroom);
0079     mlxsw_sp_hdroom_bufs_reset_lossiness(&hdroom);
0080     mlxsw_sp_hdroom_bufs_reset_sizes(mlxsw_sp_port, &hdroom);
0081 
0082     err = mlxsw_sp_hdroom_configure(mlxsw_sp_port, &hdroom);
0083     if (err) {
0084         netdev_err(dev, "Failed to configure port's headroom\n");
0085         return err;
0086     }
0087 
0088     return 0;
0089 }
0090 
0091 static int __mlxsw_sp_dcbnl_ieee_setets(struct mlxsw_sp_port *mlxsw_sp_port,
0092                     struct ieee_ets *ets)
0093 {
0094     struct ieee_ets *my_ets = mlxsw_sp_port->dcb.ets;
0095     struct net_device *dev = mlxsw_sp_port->dev;
0096     int i, err;
0097 
0098     /* Egress configuration. */
0099     for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
0100         bool dwrr = ets->tc_tsa[i] == IEEE_8021QAZ_TSA_ETS;
0101         u8 weight = ets->tc_tx_bw[i];
0102 
0103         err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
0104                         MLXSW_REG_QEEC_HR_SUBGROUP, i,
0105                         0, dwrr, weight);
0106         if (err) {
0107             netdev_err(dev, "Failed to link subgroup ETS element %d to group\n",
0108                    i);
0109             goto err_port_ets_set;
0110         }
0111     }
0112 
0113     for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
0114         err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i,
0115                         ets->prio_tc[i]);
0116         if (err) {
0117             netdev_err(dev, "Failed to map prio %d to TC %d\n", i,
0118                    ets->prio_tc[i]);
0119             goto err_port_prio_tc_set;
0120         }
0121     }
0122 
0123     /* Ingress configuration. */
0124     err = mlxsw_sp_port_headroom_ets_set(mlxsw_sp_port, ets);
0125     if (err)
0126         goto err_port_headroom_set;
0127 
0128     return 0;
0129 
0130 err_port_headroom_set:
0131     i = IEEE_8021QAZ_MAX_TCS;
0132 err_port_prio_tc_set:
0133     for (i--; i >= 0; i--)
0134         mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, my_ets->prio_tc[i]);
0135     i = IEEE_8021QAZ_MAX_TCS;
0136 err_port_ets_set:
0137     for (i--; i >= 0; i--) {
0138         bool dwrr = my_ets->tc_tsa[i] == IEEE_8021QAZ_TSA_ETS;
0139         u8 weight = my_ets->tc_tx_bw[i];
0140 
0141         err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
0142                         MLXSW_REG_QEEC_HR_SUBGROUP, i,
0143                         0, dwrr, weight);
0144     }
0145     return err;
0146 }
0147 
0148 static int mlxsw_sp_dcbnl_ieee_setets(struct net_device *dev,
0149                       struct ieee_ets *ets)
0150 {
0151     struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
0152     int err;
0153 
0154     err = mlxsw_sp_port_ets_validate(mlxsw_sp_port, ets);
0155     if (err)
0156         return err;
0157 
0158     err = __mlxsw_sp_dcbnl_ieee_setets(mlxsw_sp_port, ets);
0159     if (err)
0160         return err;
0161 
0162     memcpy(mlxsw_sp_port->dcb.ets, ets, sizeof(*ets));
0163     mlxsw_sp_port->dcb.ets->ets_cap = IEEE_8021QAZ_MAX_TCS;
0164 
0165     return 0;
0166 }
0167 
0168 static int mlxsw_sp_dcbnl_app_validate(struct net_device *dev,
0169                        struct dcb_app *app)
0170 {
0171     if (app->priority >= IEEE_8021QAZ_MAX_TCS) {
0172         netdev_err(dev, "APP entry with priority value %u is invalid\n",
0173                app->priority);
0174         return -EINVAL;
0175     }
0176 
0177     switch (app->selector) {
0178     case IEEE_8021QAZ_APP_SEL_DSCP:
0179         if (app->protocol >= 64) {
0180             netdev_err(dev, "DSCP APP entry with protocol value %u is invalid\n",
0181                    app->protocol);
0182             return -EINVAL;
0183         }
0184         break;
0185 
0186     case IEEE_8021QAZ_APP_SEL_ETHERTYPE:
0187         if (app->protocol) {
0188             netdev_err(dev, "EtherType APP entries with protocol value != 0 not supported\n");
0189             return -EINVAL;
0190         }
0191         break;
0192 
0193     default:
0194         netdev_err(dev, "APP entries with selector %u not supported\n",
0195                app->selector);
0196         return -EINVAL;
0197     }
0198 
0199     return 0;
0200 }
0201 
0202 static u8
0203 mlxsw_sp_port_dcb_app_default_prio(struct mlxsw_sp_port *mlxsw_sp_port)
0204 {
0205     u8 prio_mask;
0206 
0207     prio_mask = dcb_ieee_getapp_default_prio_mask(mlxsw_sp_port->dev);
0208     if (prio_mask)
0209         /* Take the highest configured priority. */
0210         return fls(prio_mask) - 1;
0211 
0212     return 0;
0213 }
0214 
0215 static void
0216 mlxsw_sp_port_dcb_app_dscp_prio_map(struct mlxsw_sp_port *mlxsw_sp_port,
0217                     u8 default_prio,
0218                     struct dcb_ieee_app_dscp_map *map)
0219 {
0220     int i;
0221 
0222     dcb_ieee_getapp_dscp_prio_mask_map(mlxsw_sp_port->dev, map);
0223     for (i = 0; i < ARRAY_SIZE(map->map); ++i) {
0224         if (map->map[i])
0225             map->map[i] = fls(map->map[i]) - 1;
0226         else
0227             map->map[i] = default_prio;
0228     }
0229 }
0230 
0231 static bool
0232 mlxsw_sp_port_dcb_app_prio_dscp_map(struct mlxsw_sp_port *mlxsw_sp_port,
0233                     struct dcb_ieee_app_prio_map *map)
0234 {
0235     bool have_dscp = false;
0236     int i;
0237 
0238     dcb_ieee_getapp_prio_dscp_mask_map(mlxsw_sp_port->dev, map);
0239     for (i = 0; i < ARRAY_SIZE(map->map); ++i) {
0240         if (map->map[i]) {
0241             map->map[i] = fls64(map->map[i]) - 1;
0242             have_dscp = true;
0243         }
0244     }
0245 
0246     return have_dscp;
0247 }
0248 
0249 static int
0250 mlxsw_sp_port_dcb_app_update_qpts(struct mlxsw_sp_port *mlxsw_sp_port,
0251                   enum mlxsw_reg_qpts_trust_state ts)
0252 {
0253     struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
0254     char qpts_pl[MLXSW_REG_QPTS_LEN];
0255 
0256     mlxsw_reg_qpts_pack(qpts_pl, mlxsw_sp_port->local_port, ts);
0257     return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qpts), qpts_pl);
0258 }
0259 
0260 static int
0261 mlxsw_sp_port_dcb_app_update_qrwe(struct mlxsw_sp_port *mlxsw_sp_port,
0262                   bool rewrite_dscp)
0263 {
0264     struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
0265     char qrwe_pl[MLXSW_REG_QRWE_LEN];
0266 
0267     mlxsw_reg_qrwe_pack(qrwe_pl, mlxsw_sp_port->local_port,
0268                 false, rewrite_dscp);
0269     return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qrwe), qrwe_pl);
0270 }
0271 
0272 static int
0273 mlxsw_sp_port_dcb_toggle_trust(struct mlxsw_sp_port *mlxsw_sp_port,
0274                    enum mlxsw_reg_qpts_trust_state ts)
0275 {
0276     bool rewrite_dscp = ts == MLXSW_REG_QPTS_TRUST_STATE_DSCP;
0277     int err;
0278 
0279     if (mlxsw_sp_port->dcb.trust_state == ts)
0280         return 0;
0281 
0282     err = mlxsw_sp_port_dcb_app_update_qpts(mlxsw_sp_port, ts);
0283     if (err)
0284         return err;
0285 
0286     err = mlxsw_sp_port_dcb_app_update_qrwe(mlxsw_sp_port, rewrite_dscp);
0287     if (err)
0288         goto err_update_qrwe;
0289 
0290     mlxsw_sp_port->dcb.trust_state = ts;
0291     return 0;
0292 
0293 err_update_qrwe:
0294     mlxsw_sp_port_dcb_app_update_qpts(mlxsw_sp_port,
0295                       mlxsw_sp_port->dcb.trust_state);
0296     return err;
0297 }
0298 
0299 static int
0300 mlxsw_sp_port_dcb_app_update_qpdp(struct mlxsw_sp_port *mlxsw_sp_port,
0301                   u8 default_prio)
0302 {
0303     struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
0304     char qpdp_pl[MLXSW_REG_QPDP_LEN];
0305 
0306     mlxsw_reg_qpdp_pack(qpdp_pl, mlxsw_sp_port->local_port, default_prio);
0307     return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qpdp), qpdp_pl);
0308 }
0309 
0310 static int
0311 mlxsw_sp_port_dcb_app_update_qpdpm(struct mlxsw_sp_port *mlxsw_sp_port,
0312                    struct dcb_ieee_app_dscp_map *map)
0313 {
0314     struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
0315     char qpdpm_pl[MLXSW_REG_QPDPM_LEN];
0316     short int i;
0317 
0318     mlxsw_reg_qpdpm_pack(qpdpm_pl, mlxsw_sp_port->local_port);
0319     for (i = 0; i < ARRAY_SIZE(map->map); ++i)
0320         mlxsw_reg_qpdpm_dscp_pack(qpdpm_pl, i, map->map[i]);
0321     return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qpdpm), qpdpm_pl);
0322 }
0323 
0324 static int
0325 mlxsw_sp_port_dcb_app_update_qpdsm(struct mlxsw_sp_port *mlxsw_sp_port,
0326                    struct dcb_ieee_app_prio_map *map)
0327 {
0328     struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
0329     char qpdsm_pl[MLXSW_REG_QPDSM_LEN];
0330     short int i;
0331 
0332     mlxsw_reg_qpdsm_pack(qpdsm_pl, mlxsw_sp_port->local_port);
0333     for (i = 0; i < ARRAY_SIZE(map->map); ++i)
0334         mlxsw_reg_qpdsm_prio_pack(qpdsm_pl, i, map->map[i]);
0335     return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qpdsm), qpdsm_pl);
0336 }
0337 
0338 static int mlxsw_sp_port_dcb_app_update(struct mlxsw_sp_port *mlxsw_sp_port)
0339 {
0340     struct dcb_ieee_app_prio_map prio_map;
0341     struct dcb_ieee_app_dscp_map dscp_map;
0342     u8 default_prio;
0343     bool have_dscp;
0344     int err;
0345 
0346     default_prio = mlxsw_sp_port_dcb_app_default_prio(mlxsw_sp_port);
0347     err = mlxsw_sp_port_dcb_app_update_qpdp(mlxsw_sp_port, default_prio);
0348     if (err) {
0349         netdev_err(mlxsw_sp_port->dev, "Couldn't configure port default priority\n");
0350         return err;
0351     }
0352 
0353     have_dscp = mlxsw_sp_port_dcb_app_prio_dscp_map(mlxsw_sp_port,
0354                             &prio_map);
0355 
0356     mlxsw_sp_port_dcb_app_dscp_prio_map(mlxsw_sp_port, default_prio,
0357                         &dscp_map);
0358     err = mlxsw_sp_port_dcb_app_update_qpdpm(mlxsw_sp_port,
0359                          &dscp_map);
0360     if (err) {
0361         netdev_err(mlxsw_sp_port->dev, "Couldn't configure priority map\n");
0362         return err;
0363     }
0364 
0365     err = mlxsw_sp_port_dcb_app_update_qpdsm(mlxsw_sp_port,
0366                          &prio_map);
0367     if (err) {
0368         netdev_err(mlxsw_sp_port->dev, "Couldn't configure DSCP rewrite map\n");
0369         return err;
0370     }
0371 
0372     if (!have_dscp) {
0373         err = mlxsw_sp_port_dcb_toggle_trust(mlxsw_sp_port,
0374                     MLXSW_REG_QPTS_TRUST_STATE_PCP);
0375         if (err)
0376             netdev_err(mlxsw_sp_port->dev, "Couldn't switch to trust L2\n");
0377         return err;
0378     }
0379 
0380     err = mlxsw_sp_port_dcb_toggle_trust(mlxsw_sp_port,
0381                          MLXSW_REG_QPTS_TRUST_STATE_DSCP);
0382     if (err) {
0383         /* A failure to set trust DSCP means that the QPDPM and QPDSM
0384          * maps installed above are not in effect. And since we are here
0385          * attempting to set trust DSCP, we couldn't have attempted to
0386          * switch trust to PCP. Thus no cleanup is necessary.
0387          */
0388         netdev_err(mlxsw_sp_port->dev, "Couldn't switch to trust L3\n");
0389         return err;
0390     }
0391 
0392     return 0;
0393 }
0394 
0395 static int mlxsw_sp_dcbnl_ieee_setapp(struct net_device *dev,
0396                       struct dcb_app *app)
0397 {
0398     struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
0399     int err;
0400 
0401     err = mlxsw_sp_dcbnl_app_validate(dev, app);
0402     if (err)
0403         return err;
0404 
0405     err = dcb_ieee_setapp(dev, app);
0406     if (err)
0407         return err;
0408 
0409     err = mlxsw_sp_port_dcb_app_update(mlxsw_sp_port);
0410     if (err)
0411         goto err_update;
0412 
0413     return 0;
0414 
0415 err_update:
0416     dcb_ieee_delapp(dev, app);
0417     return err;
0418 }
0419 
0420 static int mlxsw_sp_dcbnl_ieee_delapp(struct net_device *dev,
0421                       struct dcb_app *app)
0422 {
0423     struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
0424     int err;
0425 
0426     err = dcb_ieee_delapp(dev, app);
0427     if (err)
0428         return err;
0429 
0430     err = mlxsw_sp_port_dcb_app_update(mlxsw_sp_port);
0431     if (err)
0432         netdev_err(dev, "Failed to update DCB APP configuration\n");
0433     return 0;
0434 }
0435 
0436 static int mlxsw_sp_dcbnl_ieee_getmaxrate(struct net_device *dev,
0437                       struct ieee_maxrate *maxrate)
0438 {
0439     struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
0440 
0441     memcpy(maxrate, mlxsw_sp_port->dcb.maxrate, sizeof(*maxrate));
0442 
0443     return 0;
0444 }
0445 
0446 static int mlxsw_sp_dcbnl_ieee_setmaxrate(struct net_device *dev,
0447                       struct ieee_maxrate *maxrate)
0448 {
0449     struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
0450     struct ieee_maxrate *my_maxrate = mlxsw_sp_port->dcb.maxrate;
0451     int err, i;
0452 
0453     for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
0454         err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
0455                             MLXSW_REG_QEEC_HR_SUBGROUP,
0456                             i, 0,
0457                             maxrate->tc_maxrate[i], 0);
0458         if (err) {
0459             netdev_err(dev, "Failed to set maxrate for TC %d\n", i);
0460             goto err_port_ets_maxrate_set;
0461         }
0462     }
0463 
0464     memcpy(mlxsw_sp_port->dcb.maxrate, maxrate, sizeof(*maxrate));
0465 
0466     return 0;
0467 
0468 err_port_ets_maxrate_set:
0469     for (i--; i >= 0; i--)
0470         mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
0471                           MLXSW_REG_QEEC_HR_SUBGROUP,
0472                           i, 0,
0473                           my_maxrate->tc_maxrate[i], 0);
0474     return err;
0475 }
0476 
0477 static int mlxsw_sp_port_pfc_cnt_get(struct mlxsw_sp_port *mlxsw_sp_port,
0478                      u8 prio)
0479 {
0480     struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
0481     struct ieee_pfc *my_pfc = mlxsw_sp_port->dcb.pfc;
0482     char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
0483     int err;
0484 
0485     mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port,
0486                  MLXSW_REG_PPCNT_PRIO_CNT, prio);
0487     err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
0488     if (err)
0489         return err;
0490 
0491     my_pfc->requests[prio] = mlxsw_reg_ppcnt_tx_pause_get(ppcnt_pl);
0492     my_pfc->indications[prio] = mlxsw_reg_ppcnt_rx_pause_get(ppcnt_pl);
0493 
0494     return 0;
0495 }
0496 
0497 static int mlxsw_sp_dcbnl_ieee_getpfc(struct net_device *dev,
0498                       struct ieee_pfc *pfc)
0499 {
0500     struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
0501     int err, i;
0502 
0503     for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
0504         err = mlxsw_sp_port_pfc_cnt_get(mlxsw_sp_port, i);
0505         if (err) {
0506             netdev_err(dev, "Failed to get PFC count for priority %d\n",
0507                    i);
0508             return err;
0509         }
0510     }
0511 
0512     memcpy(pfc, mlxsw_sp_port->dcb.pfc, sizeof(*pfc));
0513 
0514     return 0;
0515 }
0516 
0517 static int mlxsw_sp_port_pfc_set(struct mlxsw_sp_port *mlxsw_sp_port,
0518                  struct ieee_pfc *pfc)
0519 {
0520     char pfcc_pl[MLXSW_REG_PFCC_LEN];
0521 
0522     mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port);
0523     mlxsw_reg_pfcc_pprx_set(pfcc_pl, mlxsw_sp_port->link.rx_pause);
0524     mlxsw_reg_pfcc_pptx_set(pfcc_pl, mlxsw_sp_port->link.tx_pause);
0525     mlxsw_reg_pfcc_prio_pack(pfcc_pl, pfc->pfc_en);
0526 
0527     return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc),
0528                    pfcc_pl);
0529 }
0530 
0531 static int mlxsw_sp_dcbnl_ieee_setpfc(struct net_device *dev,
0532                       struct ieee_pfc *pfc)
0533 {
0534     struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
0535     bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
0536     struct mlxsw_sp_hdroom orig_hdroom;
0537     struct mlxsw_sp_hdroom hdroom;
0538     int prio;
0539     int err;
0540 
0541     if (pause_en && pfc->pfc_en) {
0542         netdev_err(dev, "PAUSE frames already enabled on port\n");
0543         return -EINVAL;
0544     }
0545 
0546     orig_hdroom = *mlxsw_sp_port->hdroom;
0547 
0548     hdroom = orig_hdroom;
0549     if (pfc->pfc_en)
0550         hdroom.delay_bytes = DIV_ROUND_UP(pfc->delay, BITS_PER_BYTE);
0551     else
0552         hdroom.delay_bytes = 0;
0553 
0554     for (prio = 0; prio < IEEE_8021QAZ_MAX_TCS; prio++)
0555         hdroom.prios.prio[prio].lossy = !(pfc->pfc_en & BIT(prio));
0556 
0557     mlxsw_sp_hdroom_bufs_reset_lossiness(&hdroom);
0558     mlxsw_sp_hdroom_bufs_reset_sizes(mlxsw_sp_port, &hdroom);
0559 
0560     err = mlxsw_sp_hdroom_configure(mlxsw_sp_port, &hdroom);
0561     if (err) {
0562         netdev_err(dev, "Failed to configure port's headroom for PFC\n");
0563         return err;
0564     }
0565 
0566     err = mlxsw_sp_port_pfc_set(mlxsw_sp_port, pfc);
0567     if (err) {
0568         netdev_err(dev, "Failed to configure PFC\n");
0569         goto err_port_pfc_set;
0570     }
0571 
0572     memcpy(mlxsw_sp_port->dcb.pfc, pfc, sizeof(*pfc));
0573     mlxsw_sp_port->dcb.pfc->pfc_cap = IEEE_8021QAZ_MAX_TCS;
0574 
0575     return 0;
0576 
0577 err_port_pfc_set:
0578     mlxsw_sp_hdroom_configure(mlxsw_sp_port, &orig_hdroom);
0579     return err;
0580 }
0581 
0582 static int mlxsw_sp_dcbnl_getbuffer(struct net_device *dev, struct dcbnl_buffer *buf)
0583 {
0584     struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
0585     struct mlxsw_sp_hdroom *hdroom = mlxsw_sp_port->hdroom;
0586     struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
0587     int prio;
0588     int i;
0589 
0590     buf->total_size = 0;
0591 
0592     BUILD_BUG_ON(DCBX_MAX_BUFFERS > MLXSW_SP_PB_COUNT);
0593     for (i = 0; i < MLXSW_SP_PB_COUNT; i++) {
0594         u32 bytes = mlxsw_sp_cells_bytes(mlxsw_sp, hdroom->bufs.buf[i].size_cells);
0595 
0596         if (i < DCBX_MAX_BUFFERS)
0597             buf->buffer_size[i] = bytes;
0598         buf->total_size += bytes;
0599     }
0600 
0601     buf->total_size += mlxsw_sp_cells_bytes(mlxsw_sp, hdroom->int_buf.size_cells);
0602 
0603     for (prio = 0; prio < IEEE_8021Q_MAX_PRIORITIES; prio++)
0604         buf->prio2buffer[prio] = hdroom->prios.prio[prio].buf_idx;
0605 
0606     return 0;
0607 }
0608 
0609 static int mlxsw_sp_dcbnl_setbuffer(struct net_device *dev, struct dcbnl_buffer *buf)
0610 {
0611     struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
0612     struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
0613     struct mlxsw_sp_hdroom hdroom;
0614     int prio;
0615     int i;
0616 
0617     hdroom = *mlxsw_sp_port->hdroom;
0618 
0619     if (hdroom.mode != MLXSW_SP_HDROOM_MODE_TC) {
0620         netdev_err(dev, "The use of dcbnl_setbuffer is only allowed if egress is configured using TC\n");
0621         return -EINVAL;
0622     }
0623 
0624     for (prio = 0; prio < IEEE_8021Q_MAX_PRIORITIES; prio++)
0625         hdroom.prios.prio[prio].set_buf_idx = buf->prio2buffer[prio];
0626 
0627     BUILD_BUG_ON(DCBX_MAX_BUFFERS > MLXSW_SP_PB_COUNT);
0628     for (i = 0; i < DCBX_MAX_BUFFERS; i++)
0629         hdroom.bufs.buf[i].set_size_cells = mlxsw_sp_bytes_cells(mlxsw_sp,
0630                                      buf->buffer_size[i]);
0631 
0632     mlxsw_sp_hdroom_prios_reset_buf_idx(&hdroom);
0633     mlxsw_sp_hdroom_bufs_reset_lossiness(&hdroom);
0634     mlxsw_sp_hdroom_bufs_reset_sizes(mlxsw_sp_port, &hdroom);
0635     return mlxsw_sp_hdroom_configure(mlxsw_sp_port, &hdroom);
0636 }
0637 
0638 static const struct dcbnl_rtnl_ops mlxsw_sp_dcbnl_ops = {
0639     .ieee_getets        = mlxsw_sp_dcbnl_ieee_getets,
0640     .ieee_setets        = mlxsw_sp_dcbnl_ieee_setets,
0641     .ieee_getmaxrate    = mlxsw_sp_dcbnl_ieee_getmaxrate,
0642     .ieee_setmaxrate    = mlxsw_sp_dcbnl_ieee_setmaxrate,
0643     .ieee_getpfc        = mlxsw_sp_dcbnl_ieee_getpfc,
0644     .ieee_setpfc        = mlxsw_sp_dcbnl_ieee_setpfc,
0645     .ieee_setapp        = mlxsw_sp_dcbnl_ieee_setapp,
0646     .ieee_delapp        = mlxsw_sp_dcbnl_ieee_delapp,
0647 
0648     .getdcbx        = mlxsw_sp_dcbnl_getdcbx,
0649     .setdcbx        = mlxsw_sp_dcbnl_setdcbx,
0650 
0651     .dcbnl_getbuffer    = mlxsw_sp_dcbnl_getbuffer,
0652     .dcbnl_setbuffer    = mlxsw_sp_dcbnl_setbuffer,
0653 };
0654 
0655 static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
0656 {
0657     mlxsw_sp_port->dcb.ets = kzalloc(sizeof(*mlxsw_sp_port->dcb.ets),
0658                      GFP_KERNEL);
0659     if (!mlxsw_sp_port->dcb.ets)
0660         return -ENOMEM;
0661 
0662     mlxsw_sp_port->dcb.ets->ets_cap = IEEE_8021QAZ_MAX_TCS;
0663 
0664     return 0;
0665 }
0666 
0667 static void mlxsw_sp_port_ets_fini(struct mlxsw_sp_port *mlxsw_sp_port)
0668 {
0669     kfree(mlxsw_sp_port->dcb.ets);
0670 }
0671 
0672 static int mlxsw_sp_port_maxrate_init(struct mlxsw_sp_port *mlxsw_sp_port)
0673 {
0674     int i;
0675 
0676     mlxsw_sp_port->dcb.maxrate = kmalloc(sizeof(*mlxsw_sp_port->dcb.maxrate),
0677                          GFP_KERNEL);
0678     if (!mlxsw_sp_port->dcb.maxrate)
0679         return -ENOMEM;
0680 
0681     for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
0682         mlxsw_sp_port->dcb.maxrate->tc_maxrate[i] = MLXSW_REG_QEEC_MAS_DIS;
0683 
0684     return 0;
0685 }
0686 
0687 static void mlxsw_sp_port_maxrate_fini(struct mlxsw_sp_port *mlxsw_sp_port)
0688 {
0689     kfree(mlxsw_sp_port->dcb.maxrate);
0690 }
0691 
0692 static int mlxsw_sp_port_pfc_init(struct mlxsw_sp_port *mlxsw_sp_port)
0693 {
0694     mlxsw_sp_port->dcb.pfc = kzalloc(sizeof(*mlxsw_sp_port->dcb.pfc),
0695                      GFP_KERNEL);
0696     if (!mlxsw_sp_port->dcb.pfc)
0697         return -ENOMEM;
0698 
0699     mlxsw_sp_port->dcb.pfc->pfc_cap = IEEE_8021QAZ_MAX_TCS;
0700 
0701     return 0;
0702 }
0703 
0704 static void mlxsw_sp_port_pfc_fini(struct mlxsw_sp_port *mlxsw_sp_port)
0705 {
0706     kfree(mlxsw_sp_port->dcb.pfc);
0707 }
0708 
0709 int mlxsw_sp_port_dcb_init(struct mlxsw_sp_port *mlxsw_sp_port)
0710 {
0711     int err;
0712 
0713     err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
0714     if (err)
0715         return err;
0716     err = mlxsw_sp_port_maxrate_init(mlxsw_sp_port);
0717     if (err)
0718         goto err_port_maxrate_init;
0719     err = mlxsw_sp_port_pfc_init(mlxsw_sp_port);
0720     if (err)
0721         goto err_port_pfc_init;
0722 
0723     mlxsw_sp_port->dcb.trust_state = MLXSW_REG_QPTS_TRUST_STATE_PCP;
0724     mlxsw_sp_port->dev->dcbnl_ops = &mlxsw_sp_dcbnl_ops;
0725 
0726     return 0;
0727 
0728 err_port_pfc_init:
0729     mlxsw_sp_port_maxrate_fini(mlxsw_sp_port);
0730 err_port_maxrate_init:
0731     mlxsw_sp_port_ets_fini(mlxsw_sp_port);
0732     return err;
0733 }
0734 
0735 void mlxsw_sp_port_dcb_fini(struct mlxsw_sp_port *mlxsw_sp_port)
0736 {
0737     mlxsw_sp_port_pfc_fini(mlxsw_sp_port);
0738     mlxsw_sp_port_maxrate_fini(mlxsw_sp_port);
0739     mlxsw_sp_port_ets_fini(mlxsw_sp_port);
0740 }
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