mellanox/mlxsw/spectrum2_acl_tcam.c

0001 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
0002 /* Copyright (c) 2018 Mellanox Technologies. All rights reserved */
0003
0004 #include <linux/kernel.h>
0005
0006 #include "spectrum.h"
0007 #include "spectrum_acl_tcam.h"
0008 #include "core_acl_flex_actions.h"
0009
0010 struct mlxsw_sp2_acl_tcam {
0011     struct mlxsw_sp_acl_atcam atcam;
0012     u32 kvdl_index;
0013     unsigned int kvdl_count;
0014 };
0015
0016 struct mlxsw_sp2_acl_tcam_region {
0017     struct mlxsw_sp_acl_atcam_region aregion;
0018     struct mlxsw_sp_acl_tcam_region *region;
0019 };
0020
0021 struct mlxsw_sp2_acl_tcam_chunk {
0022     struct mlxsw_sp_acl_atcam_chunk achunk;
0023 };
0024
0025 struct mlxsw_sp2_acl_tcam_entry {
0026     struct mlxsw_sp_acl_atcam_entry aentry;
0027     struct mlxsw_afa_block *act_block;
0028 };
0029
0030 static int
0031 mlxsw_sp2_acl_ctcam_region_entry_insert(struct mlxsw_sp_acl_ctcam_region *cregion,
0032                     struct mlxsw_sp_acl_ctcam_entry *centry,
0033                     const char *mask)
0034 {
0035     struct mlxsw_sp_acl_atcam_region *aregion;
0036     struct mlxsw_sp_acl_atcam_entry *aentry;
0037     struct mlxsw_sp_acl_erp_mask *erp_mask;
0038
0039     aregion = mlxsw_sp_acl_tcam_cregion_aregion(cregion);
0040     aentry = mlxsw_sp_acl_tcam_centry_aentry(centry);
0041
0042     erp_mask = mlxsw_sp_acl_erp_mask_get(aregion, mask, true);
0043     if (IS_ERR(erp_mask))
0044         return PTR_ERR(erp_mask);
0045     aentry->erp_mask = erp_mask;
0046
0047     return 0;
0048 }
0049
0050 static void
0051 mlxsw_sp2_acl_ctcam_region_entry_remove(struct mlxsw_sp_acl_ctcam_region *cregion,
0052                     struct mlxsw_sp_acl_ctcam_entry *centry)
0053 {
0054     struct mlxsw_sp_acl_atcam_region *aregion;
0055     struct mlxsw_sp_acl_atcam_entry *aentry;
0056
0057     aregion = mlxsw_sp_acl_tcam_cregion_aregion(cregion);
0058     aentry = mlxsw_sp_acl_tcam_centry_aentry(centry);
0059
0060     mlxsw_sp_acl_erp_mask_put(aregion, aentry->erp_mask);
0061 }
0062
0063 static const struct mlxsw_sp_acl_ctcam_region_ops
0064 mlxsw_sp2_acl_ctcam_region_ops = {
0065     .entry_insert = mlxsw_sp2_acl_ctcam_region_entry_insert,
0066     .entry_remove = mlxsw_sp2_acl_ctcam_region_entry_remove,
0067 };
0068
0069 static int mlxsw_sp2_acl_tcam_init(struct mlxsw_sp *mlxsw_sp, void *priv,
0070                    struct mlxsw_sp_acl_tcam *_tcam)
0071 {
0072     struct mlxsw_sp2_acl_tcam *tcam = priv;
0073     struct mlxsw_afa_block *afa_block;
0074     char pefa_pl[MLXSW_REG_PEFA_LEN];
0075     char pgcr_pl[MLXSW_REG_PGCR_LEN];
0076     char *enc_actions;
0077     int i;
0078     int err;
0079
0080     /* Some TCAM regions are not exposed to the host and used internally
0081      * by the device. Allocate KVDL entries for the default actions of
0082      * these regions to avoid the host from overwriting them.
0083      */
0084     tcam->kvdl_count = _tcam->max_regions;
0085     if (MLXSW_CORE_RES_VALID(mlxsw_sp->core, ACL_MAX_DEFAULT_ACTIONS))
0086         tcam->kvdl_count = MLXSW_CORE_RES_GET(mlxsw_sp->core,
0087                               ACL_MAX_DEFAULT_ACTIONS);
0088     err = mlxsw_sp_kvdl_alloc(mlxsw_sp, MLXSW_SP_KVDL_ENTRY_TYPE_ACTSET,
0089                   tcam->kvdl_count, &tcam->kvdl_index);
0090     if (err)
0091         return err;
0092
0093     /* Create flex action block, set default action (continue)
0094      * but don't commit. We need just the current set encoding
0095      * to be written using PEFA register to all indexes for all regions.
0096      */
0097     afa_block = mlxsw_afa_block_create(mlxsw_sp->afa);
0098     if (IS_ERR(afa_block)) {
0099         err = PTR_ERR(afa_block);
0100         goto err_afa_block;
0101     }
0102     err = mlxsw_afa_block_continue(afa_block);
0103     if (WARN_ON(err))
0104         goto err_afa_block_continue;
0105     enc_actions = mlxsw_afa_block_cur_set(afa_block);
0106
0107     /* Only write to KVDL entries used by TCAM regions exposed to the
0108      * host.
0109      */
0110     for (i = 0; i < _tcam->max_regions; i++) {
0111         mlxsw_reg_pefa_pack(pefa_pl, tcam->kvdl_index + i,
0112                     true, enc_actions);
0113         err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pefa), pefa_pl);
0114         if (err)
0115             goto err_pefa_write;
0116     }
0117     mlxsw_reg_pgcr_pack(pgcr_pl, tcam->kvdl_index);
0118     err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pgcr), pgcr_pl);
0119     if (err)
0120         goto err_pgcr_write;
0121
0122     err = mlxsw_sp_acl_atcam_init(mlxsw_sp, &tcam->atcam);
0123     if (err)
0124         goto err_atcam_init;
0125
0126     mlxsw_afa_block_destroy(afa_block);
0127     return 0;
0128
0129 err_atcam_init:
0130 err_pgcr_write:
0131 err_pefa_write:
0132 err_afa_block_continue:
0133     mlxsw_afa_block_destroy(afa_block);
0134 err_afa_block:
0135     mlxsw_sp_kvdl_free(mlxsw_sp, MLXSW_SP_KVDL_ENTRY_TYPE_ACTSET,
0136                tcam->kvdl_count, tcam->kvdl_index);
0137     return err;
0138 }
0139
0140 static void mlxsw_sp2_acl_tcam_fini(struct mlxsw_sp *mlxsw_sp, void *priv)
0141 {
0142     struct mlxsw_sp2_acl_tcam *tcam = priv;
0143
0144     mlxsw_sp_acl_atcam_fini(mlxsw_sp, &tcam->atcam);
0145     mlxsw_sp_kvdl_free(mlxsw_sp, MLXSW_SP_KVDL_ENTRY_TYPE_ACTSET,
0146                tcam->kvdl_count, tcam->kvdl_index);
0147 }
0148
0149 static int
0150 mlxsw_sp2_acl_tcam_region_init(struct mlxsw_sp *mlxsw_sp, void *region_priv,
0151                    void *tcam_priv,
0152                    struct mlxsw_sp_acl_tcam_region *_region,
0153                    void *hints_priv)
0154 {
0155     struct mlxsw_sp2_acl_tcam_region *region = region_priv;
0156     struct mlxsw_sp2_acl_tcam *tcam = tcam_priv;
0157
0158     region->region = _region;
0159
0160     return mlxsw_sp_acl_atcam_region_init(mlxsw_sp, &tcam->atcam,
0161                           &region->aregion,
0162                           _region, hints_priv,
0163                           &mlxsw_sp2_acl_ctcam_region_ops);
0164 }
0165
0166 static void
0167 mlxsw_sp2_acl_tcam_region_fini(struct mlxsw_sp *mlxsw_sp, void *region_priv)
0168 {
0169     struct mlxsw_sp2_acl_tcam_region *region = region_priv;
0170
0171     mlxsw_sp_acl_atcam_region_fini(&region->aregion);
0172 }
0173
0174 static int
0175 mlxsw_sp2_acl_tcam_region_associate(struct mlxsw_sp *mlxsw_sp,
0176                     struct mlxsw_sp_acl_tcam_region *region)
0177 {
0178     return mlxsw_sp_acl_atcam_region_associate(mlxsw_sp, region->id);
0179 }
0180
0181 static void *mlxsw_sp2_acl_tcam_region_rehash_hints_get(void *region_priv)
0182 {
0183     struct mlxsw_sp2_acl_tcam_region *region = region_priv;
0184
0185     return mlxsw_sp_acl_atcam_rehash_hints_get(&region->aregion);
0186 }
0187
0188 static void mlxsw_sp2_acl_tcam_region_rehash_hints_put(void *hints_priv)
0189 {
0190     mlxsw_sp_acl_atcam_rehash_hints_put(hints_priv);
0191 }
0192
0193 static void mlxsw_sp2_acl_tcam_chunk_init(void *region_priv, void *chunk_priv,
0194                       unsigned int priority)
0195 {
0196     struct mlxsw_sp2_acl_tcam_region *region = region_priv;
0197     struct mlxsw_sp2_acl_tcam_chunk *chunk = chunk_priv;
0198
0199     mlxsw_sp_acl_atcam_chunk_init(&region->aregion, &chunk->achunk,
0200                       priority);
0201 }
0202
0203 static void mlxsw_sp2_acl_tcam_chunk_fini(void *chunk_priv)
0204 {
0205     struct mlxsw_sp2_acl_tcam_chunk *chunk = chunk_priv;
0206
0207     mlxsw_sp_acl_atcam_chunk_fini(&chunk->achunk);
0208 }
0209
0210 static int mlxsw_sp2_acl_tcam_entry_add(struct mlxsw_sp *mlxsw_sp,
0211                     void *region_priv, void *chunk_priv,
0212                     void *entry_priv,
0213                     struct mlxsw_sp_acl_rule_info *rulei)
0214 {
0215     struct mlxsw_sp2_acl_tcam_region *region = region_priv;
0216     struct mlxsw_sp2_acl_tcam_chunk *chunk = chunk_priv;
0217     struct mlxsw_sp2_acl_tcam_entry *entry = entry_priv;
0218
0219     entry->act_block = rulei->act_block;
0220     return mlxsw_sp_acl_atcam_entry_add(mlxsw_sp, &region->aregion,
0221                         &chunk->achunk, &entry->aentry,
0222                         rulei);
0223 }
0224
0225 static void mlxsw_sp2_acl_tcam_entry_del(struct mlxsw_sp *mlxsw_sp,
0226                      void *region_priv, void *chunk_priv,
0227                      void *entry_priv)
0228 {
0229     struct mlxsw_sp2_acl_tcam_region *region = region_priv;
0230     struct mlxsw_sp2_acl_tcam_chunk *chunk = chunk_priv;
0231     struct mlxsw_sp2_acl_tcam_entry *entry = entry_priv;
0232
0233     mlxsw_sp_acl_atcam_entry_del(mlxsw_sp, &region->aregion, &chunk->achunk,
0234                      &entry->aentry);
0235 }
0236
0237 static int
0238 mlxsw_sp2_acl_tcam_entry_action_replace(struct mlxsw_sp *mlxsw_sp,
0239                     void *region_priv, void *entry_priv,
0240                     struct mlxsw_sp_acl_rule_info *rulei)
0241 {
0242     struct mlxsw_sp2_acl_tcam_region *region = region_priv;
0243     struct mlxsw_sp2_acl_tcam_entry *entry = entry_priv;
0244
0245     entry->act_block = rulei->act_block;
0246     return mlxsw_sp_acl_atcam_entry_action_replace(mlxsw_sp,
0247                                &region->aregion,
0248                                &entry->aentry, rulei);
0249 }
0250
0251 static int
0252 mlxsw_sp2_acl_tcam_entry_activity_get(struct mlxsw_sp *mlxsw_sp,
0253                       void *region_priv, void *entry_priv,
0254                       bool *activity)
0255 {
0256     struct mlxsw_sp2_acl_tcam_entry *entry = entry_priv;
0257
0258     return mlxsw_afa_block_activity_get(entry->act_block, activity);
0259 }
0260
0261 const struct mlxsw_sp_acl_tcam_ops mlxsw_sp2_acl_tcam_ops = {
0262     .key_type       = MLXSW_REG_PTAR_KEY_TYPE_FLEX2,
0263     .priv_size      = sizeof(struct mlxsw_sp2_acl_tcam),
0264     .init           = mlxsw_sp2_acl_tcam_init,
0265     .fini           = mlxsw_sp2_acl_tcam_fini,
0266     .region_priv_size   = sizeof(struct mlxsw_sp2_acl_tcam_region),
0267     .region_init        = mlxsw_sp2_acl_tcam_region_init,
0268     .region_fini        = mlxsw_sp2_acl_tcam_region_fini,
0269     .region_associate   = mlxsw_sp2_acl_tcam_region_associate,
0270     .region_rehash_hints_get = mlxsw_sp2_acl_tcam_region_rehash_hints_get,
0271     .region_rehash_hints_put = mlxsw_sp2_acl_tcam_region_rehash_hints_put,
0272     .chunk_priv_size    = sizeof(struct mlxsw_sp2_acl_tcam_chunk),
0273     .chunk_init     = mlxsw_sp2_acl_tcam_chunk_init,
0274     .chunk_fini     = mlxsw_sp2_acl_tcam_chunk_fini,
0275     .entry_priv_size    = sizeof(struct mlxsw_sp2_acl_tcam_entry),
0276     .entry_add      = mlxsw_sp2_acl_tcam_entry_add,
0277     .entry_del      = mlxsw_sp2_acl_tcam_entry_del,
0278     .entry_action_replace   = mlxsw_sp2_acl_tcam_entry_action_replace,
0279     .entry_activity_get = mlxsw_sp2_acl_tcam_entry_activity_get,
0280 };