mellanox/mlxsw/resources.h

0001 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */
0002 /* Copyright (c) 2016-2018 Mellanox Technologies. All rights reserved */
0003
0004 #ifndef _MLXSW_RESOURCES_H
0005 #define _MLXSW_RESOURCES_H
0006
0007 #include <linux/kernel.h>
0008 #include <linux/types.h>
0009
0010 enum mlxsw_res_id {
0011     MLXSW_RES_ID_KVD_SIZE,
0012     MLXSW_RES_ID_KVD_SINGLE_MIN_SIZE,
0013     MLXSW_RES_ID_KVD_DOUBLE_MIN_SIZE,
0014     MLXSW_RES_ID_PGT_SIZE,
0015     MLXSW_RES_ID_MAX_KVD_LINEAR_RANGE,
0016     MLXSW_RES_ID_MAX_KVD_ACTION_SETS,
0017     MLXSW_RES_ID_MAX_TRAP_GROUPS,
0018     MLXSW_RES_ID_CQE_V0,
0019     MLXSW_RES_ID_CQE_V1,
0020     MLXSW_RES_ID_CQE_V2,
0021     MLXSW_RES_ID_COUNTER_POOL_SIZE,
0022     MLXSW_RES_ID_COUNTER_BANK_SIZE,
0023     MLXSW_RES_ID_MAX_SPAN,
0024     MLXSW_RES_ID_COUNTER_SIZE_PACKETS_BYTES,
0025     MLXSW_RES_ID_COUNTER_SIZE_ROUTER_BASIC,
0026     MLXSW_RES_ID_MAX_SYSTEM_PORT,
0027     MLXSW_RES_ID_FID,
0028     MLXSW_RES_ID_MAX_LAG,
0029     MLXSW_RES_ID_MAX_LAG_MEMBERS,
0030     MLXSW_RES_ID_GUARANTEED_SHARED_BUFFER,
0031     MLXSW_RES_ID_CELL_SIZE,
0032     MLXSW_RES_ID_MAX_HEADROOM_SIZE,
0033     MLXSW_RES_ID_ACL_MAX_TCAM_REGIONS,
0034     MLXSW_RES_ID_ACL_MAX_TCAM_RULES,
0035     MLXSW_RES_ID_ACL_MAX_REGIONS,
0036     MLXSW_RES_ID_ACL_MAX_GROUPS,
0037     MLXSW_RES_ID_ACL_MAX_GROUP_SIZE,
0038     MLXSW_RES_ID_ACL_MAX_DEFAULT_ACTIONS,
0039     MLXSW_RES_ID_ACL_FLEX_KEYS,
0040     MLXSW_RES_ID_ACL_MAX_ACTION_PER_RULE,
0041     MLXSW_RES_ID_ACL_ACTIONS_PER_SET,
0042     MLXSW_RES_ID_ACL_MAX_ERPT_BANKS,
0043     MLXSW_RES_ID_ACL_MAX_ERPT_BANK_SIZE,
0044     MLXSW_RES_ID_ACL_MAX_LARGE_KEY_ID,
0045     MLXSW_RES_ID_ACL_ERPT_ENTRIES_2KB,
0046     MLXSW_RES_ID_ACL_ERPT_ENTRIES_4KB,
0047     MLXSW_RES_ID_ACL_ERPT_ENTRIES_8KB,
0048     MLXSW_RES_ID_ACL_ERPT_ENTRIES_12KB,
0049     MLXSW_RES_ID_ACL_MAX_BF_LOG,
0050     MLXSW_RES_ID_MAX_GLOBAL_POLICERS,
0051     MLXSW_RES_ID_MAX_CPU_POLICERS,
0052     MLXSW_RES_ID_MAX_VRS,
0053     MLXSW_RES_ID_MAX_RIFS,
0054     MLXSW_RES_ID_MC_ERIF_LIST_ENTRIES,
0055     MLXSW_RES_ID_MAX_RIF_MAC_PROFILES,
0056     MLXSW_RES_ID_MAX_LPM_TREES,
0057     MLXSW_RES_ID_MAX_NVE_MC_ENTRIES_IPV4,
0058     MLXSW_RES_ID_MAX_NVE_MC_ENTRIES_IPV6,
0059
0060     /* Internal resources.
0061      * Determined by the SW, not queried from the HW.
0062      */
0063     MLXSW_RES_ID_KVD_SINGLE_SIZE,
0064     MLXSW_RES_ID_KVD_DOUBLE_SIZE,
0065     MLXSW_RES_ID_KVD_LINEAR_SIZE,
0066
0067     __MLXSW_RES_ID_MAX,
0068 };
0069
0070 static u16 mlxsw_res_ids[] = {
0071     [MLXSW_RES_ID_KVD_SIZE] = 0x1001,
0072     [MLXSW_RES_ID_KVD_SINGLE_MIN_SIZE] = 0x1002,
0073     [MLXSW_RES_ID_KVD_DOUBLE_MIN_SIZE] = 0x1003,
0074     [MLXSW_RES_ID_PGT_SIZE] = 0x1004,
0075     [MLXSW_RES_ID_MAX_KVD_LINEAR_RANGE] = 0x1005,
0076     [MLXSW_RES_ID_MAX_KVD_ACTION_SETS] = 0x1007,
0077     [MLXSW_RES_ID_MAX_TRAP_GROUPS] = 0x2201,
0078     [MLXSW_RES_ID_CQE_V0] = 0x2210,
0079     [MLXSW_RES_ID_CQE_V1] = 0x2211,
0080     [MLXSW_RES_ID_CQE_V2] = 0x2212,
0081     [MLXSW_RES_ID_COUNTER_POOL_SIZE] = 0x2410,
0082     [MLXSW_RES_ID_COUNTER_BANK_SIZE] = 0x2411,
0083     [MLXSW_RES_ID_MAX_SPAN] = 0x2420,
0084     [MLXSW_RES_ID_COUNTER_SIZE_PACKETS_BYTES] = 0x2443,
0085     [MLXSW_RES_ID_COUNTER_SIZE_ROUTER_BASIC] = 0x2449,
0086     [MLXSW_RES_ID_MAX_SYSTEM_PORT] = 0x2502,
0087     [MLXSW_RES_ID_FID] = 0x2512,
0088     [MLXSW_RES_ID_MAX_LAG] = 0x2520,
0089     [MLXSW_RES_ID_MAX_LAG_MEMBERS] = 0x2521,
0090     [MLXSW_RES_ID_GUARANTEED_SHARED_BUFFER] = 0x2805,   /* Bytes */
0091     [MLXSW_RES_ID_CELL_SIZE] = 0x2803,  /* Bytes */
0092     [MLXSW_RES_ID_MAX_HEADROOM_SIZE] = 0x2811,  /* Bytes */
0093     [MLXSW_RES_ID_ACL_MAX_TCAM_REGIONS] = 0x2901,
0094     [MLXSW_RES_ID_ACL_MAX_TCAM_RULES] = 0x2902,
0095     [MLXSW_RES_ID_ACL_MAX_REGIONS] = 0x2903,
0096     [MLXSW_RES_ID_ACL_MAX_GROUPS] = 0x2904,
0097     [MLXSW_RES_ID_ACL_MAX_GROUP_SIZE] = 0x2905,
0098     [MLXSW_RES_ID_ACL_MAX_DEFAULT_ACTIONS] = 0x2908,
0099     [MLXSW_RES_ID_ACL_FLEX_KEYS] = 0x2910,
0100     [MLXSW_RES_ID_ACL_MAX_ACTION_PER_RULE] = 0x2911,
0101     [MLXSW_RES_ID_ACL_ACTIONS_PER_SET] = 0x2912,
0102     [MLXSW_RES_ID_ACL_MAX_ERPT_BANKS] = 0x2940,
0103     [MLXSW_RES_ID_ACL_MAX_ERPT_BANK_SIZE] = 0x2941,
0104     [MLXSW_RES_ID_ACL_MAX_LARGE_KEY_ID] = 0x2942,
0105     [MLXSW_RES_ID_ACL_ERPT_ENTRIES_2KB] = 0x2950,
0106     [MLXSW_RES_ID_ACL_ERPT_ENTRIES_4KB] = 0x2951,
0107     [MLXSW_RES_ID_ACL_ERPT_ENTRIES_8KB] = 0x2952,
0108     [MLXSW_RES_ID_ACL_ERPT_ENTRIES_12KB] = 0x2953,
0109     [MLXSW_RES_ID_ACL_MAX_BF_LOG] = 0x2960,
0110     [MLXSW_RES_ID_MAX_GLOBAL_POLICERS] = 0x2A10,
0111     [MLXSW_RES_ID_MAX_CPU_POLICERS] = 0x2A13,
0112     [MLXSW_RES_ID_MAX_VRS] = 0x2C01,
0113     [MLXSW_RES_ID_MAX_RIFS] = 0x2C02,
0114     [MLXSW_RES_ID_MC_ERIF_LIST_ENTRIES] = 0x2C10,
0115     [MLXSW_RES_ID_MAX_RIF_MAC_PROFILES] = 0x2C14,
0116     [MLXSW_RES_ID_MAX_LPM_TREES] = 0x2C30,
0117     [MLXSW_RES_ID_MAX_NVE_MC_ENTRIES_IPV4] = 0x2E02,
0118     [MLXSW_RES_ID_MAX_NVE_MC_ENTRIES_IPV6] = 0x2E03,
0119 };
0120
0121 struct mlxsw_res {
0122     bool valid[__MLXSW_RES_ID_MAX];
0123     u64 values[__MLXSW_RES_ID_MAX];
0124 };
0125
0126 static inline bool mlxsw_res_valid(struct mlxsw_res *res,
0127                    enum mlxsw_res_id res_id)
0128 {
0129     return res->valid[res_id];
0130 }
0131
0132 #define MLXSW_RES_VALID(res, short_res_id)          \
0133     mlxsw_res_valid(res, MLXSW_RES_ID_##short_res_id)
0134
0135 static inline u64 mlxsw_res_get(struct mlxsw_res *res,
0136                 enum mlxsw_res_id res_id)
0137 {
0138     if (WARN_ON(!res->valid[res_id]))
0139         return 0;
0140     return res->values[res_id];
0141 }
0142
0143 #define MLXSW_RES_GET(res, short_res_id)            \
0144     mlxsw_res_get(res, MLXSW_RES_ID_##short_res_id)
0145
0146 static inline void mlxsw_res_set(struct mlxsw_res *res,
0147                  enum mlxsw_res_id res_id, u64 value)
0148 {
0149     res->valid[res_id] = true;
0150     res->values[res_id] = value;
0151 }
0152
0153 #define MLXSW_RES_SET(res, short_res_id, value)         \
0154     mlxsw_res_set(res, MLXSW_RES_ID_##short_res_id, value)
0155
0156 static inline void mlxsw_res_parse(struct mlxsw_res *res, u16 id, u64 value)
0157 {
0158     int i;
0159
0160     for (i = 0; i < ARRAY_SIZE(mlxsw_res_ids); i++) {
0161         if (mlxsw_res_ids[i] == id) {
0162             mlxsw_res_set(res, i, value);
0163             return;
0164         }
0165     }
0166 }
0167
0168 #endif