mellanox/mlxsw/port.h

0001 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */
0002 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */
0003
0004 #ifndef _MLXSW_PORT_H
0005 #define _MLXSW_PORT_H
0006
0007 #include <linux/types.h>
0008
0009 #define MLXSW_PORT_MAX_MTU      10000
0010
0011 #define MLXSW_PORT_DEFAULT_VID      1
0012
0013 #define MLXSW_PORT_SWID_DISABLED_PORT   255
0014 #define MLXSW_PORT_SWID_ALL_SWIDS   254
0015 #define MLXSW_PORT_SWID_TYPE_IB     1
0016 #define MLXSW_PORT_SWID_TYPE_ETH    2
0017
0018 #define MLXSW_PORT_MAX_IB_PHY_PORTS 36
0019 #define MLXSW_PORT_MAX_IB_PORTS     (MLXSW_PORT_MAX_IB_PHY_PORTS + 1)
0020
0021 #define MLXSW_PORT_CPU_PORT     0x0
0022
0023 #define MLXSW_PORT_DONT_CARE        0xFF
0024
0025 enum mlxsw_port_admin_status {
0026     MLXSW_PORT_ADMIN_STATUS_UP = 1,
0027     MLXSW_PORT_ADMIN_STATUS_DOWN = 2,
0028     MLXSW_PORT_ADMIN_STATUS_UP_ONCE = 3,
0029     MLXSW_PORT_ADMIN_STATUS_DISABLED = 4,
0030 };
0031
0032 enum mlxsw_reg_pude_oper_status {
0033     MLXSW_PORT_OPER_STATUS_UP = 1,
0034     MLXSW_PORT_OPER_STATUS_DOWN = 2,
0035     MLXSW_PORT_OPER_STATUS_FAILURE = 4, /* Can be set to up again. */
0036 };
0037
0038 #endif /* _MLXSW_PORT_H */