mellanox/mlxsw/pci_hw.h

0001 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */
0002 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */
0003
0004 #ifndef _MLXSW_PCI_HW_H
0005 #define _MLXSW_PCI_HW_H
0006
0007 #include <linux/bitops.h>
0008
0009 #include "item.h"
0010
0011 #define MLXSW_PCI_BAR0_SIZE     (1024 * 1024) /* 1MB */
0012 #define MLXSW_PCI_PAGE_SIZE     4096
0013
0014 #define MLXSW_PCI_CIR_BASE          0x71000
0015 #define MLXSW_PCI_CIR_IN_PARAM_HI       MLXSW_PCI_CIR_BASE
0016 #define MLXSW_PCI_CIR_IN_PARAM_LO       (MLXSW_PCI_CIR_BASE + 0x04)
0017 #define MLXSW_PCI_CIR_IN_MODIFIER       (MLXSW_PCI_CIR_BASE + 0x08)
0018 #define MLXSW_PCI_CIR_OUT_PARAM_HI      (MLXSW_PCI_CIR_BASE + 0x0C)
0019 #define MLXSW_PCI_CIR_OUT_PARAM_LO      (MLXSW_PCI_CIR_BASE + 0x10)
0020 #define MLXSW_PCI_CIR_TOKEN         (MLXSW_PCI_CIR_BASE + 0x14)
0021 #define MLXSW_PCI_CIR_CTRL          (MLXSW_PCI_CIR_BASE + 0x18)
0022 #define MLXSW_PCI_CIR_CTRL_GO_BIT       BIT(23)
0023 #define MLXSW_PCI_CIR_CTRL_EVREQ_BIT        BIT(22)
0024 #define MLXSW_PCI_CIR_CTRL_OPCODE_MOD_SHIFT 12
0025 #define MLXSW_PCI_CIR_CTRL_STATUS_SHIFT     24
0026 #define MLXSW_PCI_CIR_TIMEOUT_MSECS     1000
0027
0028 #define MLXSW_PCI_SW_RESET_TIMEOUT_MSECS    900000
0029 #define MLXSW_PCI_SW_RESET_WAIT_MSECS       200
0030 #define MLXSW_PCI_FW_READY          0xA1844
0031 #define MLXSW_PCI_FW_READY_MASK         0xFFFF
0032 #define MLXSW_PCI_FW_READY_MAGIC        0x5E
0033
0034 #define MLXSW_PCI_DOORBELL_SDQ_OFFSET       0x000
0035 #define MLXSW_PCI_DOORBELL_RDQ_OFFSET       0x200
0036 #define MLXSW_PCI_DOORBELL_CQ_OFFSET        0x400
0037 #define MLXSW_PCI_DOORBELL_EQ_OFFSET        0x600
0038 #define MLXSW_PCI_DOORBELL_ARM_CQ_OFFSET    0x800
0039 #define MLXSW_PCI_DOORBELL_ARM_EQ_OFFSET    0xA00
0040
0041 #define MLXSW_PCI_DOORBELL(offset, type_offset, num)    \
0042     ((offset) + (type_offset) + (num) * 4)
0043
0044 #define MLXSW_PCI_CQS_MAX   96
0045 #define MLXSW_PCI_EQS_COUNT 2
0046 #define MLXSW_PCI_EQ_ASYNC_NUM  0
0047 #define MLXSW_PCI_EQ_COMP_NUM   1
0048
0049 #define MLXSW_PCI_SDQS_MIN  2 /* EMAD and control traffic */
0050 #define MLXSW_PCI_SDQ_EMAD_INDEX    0
0051 #define MLXSW_PCI_SDQ_EMAD_TC   0
0052 #define MLXSW_PCI_SDQ_CTL_TC    3
0053
0054 #define MLXSW_PCI_AQ_PAGES  8
0055 #define MLXSW_PCI_AQ_SIZE   (MLXSW_PCI_PAGE_SIZE * MLXSW_PCI_AQ_PAGES)
0056 #define MLXSW_PCI_WQE_SIZE  32 /* 32 bytes per element */
0057 #define MLXSW_PCI_CQE01_SIZE    16 /* 16 bytes per element */
0058 #define MLXSW_PCI_CQE2_SIZE 32 /* 32 bytes per element */
0059 #define MLXSW_PCI_CQE_SIZE_MAX  MLXSW_PCI_CQE2_SIZE
0060 #define MLXSW_PCI_EQE_SIZE  16 /* 16 bytes per element */
0061 #define MLXSW_PCI_WQE_COUNT (MLXSW_PCI_AQ_SIZE / MLXSW_PCI_WQE_SIZE)
0062 #define MLXSW_PCI_CQE01_COUNT   (MLXSW_PCI_AQ_SIZE / MLXSW_PCI_CQE01_SIZE)
0063 #define MLXSW_PCI_CQE2_COUNT    (MLXSW_PCI_AQ_SIZE / MLXSW_PCI_CQE2_SIZE)
0064 #define MLXSW_PCI_EQE_COUNT (MLXSW_PCI_AQ_SIZE / MLXSW_PCI_EQE_SIZE)
0065 #define MLXSW_PCI_EQE_UPDATE_COUNT  0x80
0066
0067 #define MLXSW_PCI_WQE_SG_ENTRIES    3
0068 #define MLXSW_PCI_WQE_TYPE_ETHERNET 0xA
0069
0070 /* pci_wqe_c
0071  * If set it indicates that a completion should be reported upon
0072  * execution of this descriptor.
0073  */
0074 MLXSW_ITEM32(pci, wqe, c, 0x00, 31, 1);
0075
0076 /* pci_wqe_lp
0077  * Local Processing, set if packet should be processed by the local
0078  * switch hardware:
0079  * For Ethernet EMAD (Direct Route and non Direct Route) -
0080  * must be set if packet destination is local device
0081  * For InfiniBand CTL - must be set if packet destination is local device
0082  * Otherwise it must be clear
0083  * Local Process packets must not exceed the size of 2K (including payload
0084  * and headers).
0085  */
0086 MLXSW_ITEM32(pci, wqe, lp, 0x00, 30, 1);
0087
0088 /* pci_wqe_type
0089  * Packet type.
0090  */
0091 MLXSW_ITEM32(pci, wqe, type, 0x00, 23, 4);
0092
0093 /* pci_wqe_byte_count
0094  * Size of i-th scatter/gather entry, 0 if entry is unused.
0095  */
0096 MLXSW_ITEM16_INDEXED(pci, wqe, byte_count, 0x02, 0, 14, 0x02, 0x00, false);
0097
0098 /* pci_wqe_address
0099  * Physical address of i-th scatter/gather entry.
0100  * Gather Entries must be 2Byte aligned.
0101  */
0102 MLXSW_ITEM64_INDEXED(pci, wqe, address, 0x08, 0, 64, 0x8, 0x0, false);
0103
0104 enum mlxsw_pci_cqe_v {
0105     MLXSW_PCI_CQE_V0,
0106     MLXSW_PCI_CQE_V1,
0107     MLXSW_PCI_CQE_V2,
0108 };
0109
0110 #define mlxsw_pci_cqe_item_helpers(name, v0, v1, v2)                \
0111 static inline u32 mlxsw_pci_cqe_##name##_get(enum mlxsw_pci_cqe_v v, char *cqe) \
0112 {                                       \
0113     switch (v) {                                \
0114     default:                                \
0115     case MLXSW_PCI_CQE_V0:                          \
0116         return mlxsw_pci_cqe##v0##_##name##_get(cqe);           \
0117     case MLXSW_PCI_CQE_V1:                          \
0118         return mlxsw_pci_cqe##v1##_##name##_get(cqe);           \
0119     case MLXSW_PCI_CQE_V2:                          \
0120         return mlxsw_pci_cqe##v2##_##name##_get(cqe);           \
0121     }                                   \
0122 }                                       \
0123 static inline void mlxsw_pci_cqe_##name##_set(enum mlxsw_pci_cqe_v v,       \
0124                           char *cqe, u32 val)       \
0125 {                                       \
0126     switch (v) {                                \
0127     default:                                \
0128     case MLXSW_PCI_CQE_V0:                          \
0129         mlxsw_pci_cqe##v0##_##name##_set(cqe, val);         \
0130         break;                              \
0131     case MLXSW_PCI_CQE_V1:                          \
0132         mlxsw_pci_cqe##v1##_##name##_set(cqe, val);         \
0133         break;                              \
0134     case MLXSW_PCI_CQE_V2:                          \
0135         mlxsw_pci_cqe##v2##_##name##_set(cqe, val);         \
0136         break;                              \
0137     }                                   \
0138 }
0139
0140 /* pci_cqe_lag
0141  * Packet arrives from a port which is a LAG
0142  */
0143 MLXSW_ITEM32(pci, cqe0, lag, 0x00, 23, 1);
0144 MLXSW_ITEM32(pci, cqe12, lag, 0x00, 24, 1);
0145 mlxsw_pci_cqe_item_helpers(lag, 0, 12, 12);
0146
0147 /* pci_cqe_system_port/lag_id
0148  * When lag=0: System port on which the packet was received
0149  * When lag=1:
0150  * bits [15:4] LAG ID on which the packet was received
0151  * bits [3:0] sub_port on which the packet was received
0152  */
0153 MLXSW_ITEM32(pci, cqe, system_port, 0x00, 0, 16);
0154 MLXSW_ITEM32(pci, cqe0, lag_id, 0x00, 4, 12);
0155 MLXSW_ITEM32(pci, cqe12, lag_id, 0x00, 0, 16);
0156 mlxsw_pci_cqe_item_helpers(lag_id, 0, 12, 12);
0157 MLXSW_ITEM32(pci, cqe0, lag_subport, 0x00, 0, 4);
0158 MLXSW_ITEM32(pci, cqe12, lag_subport, 0x00, 16, 8);
0159 mlxsw_pci_cqe_item_helpers(lag_subport, 0, 12, 12);
0160
0161 /* pci_cqe_wqe_counter
0162  * WQE count of the WQEs completed on the associated dqn
0163  */
0164 MLXSW_ITEM32(pci, cqe, wqe_counter, 0x04, 16, 16);
0165
0166 /* pci_cqe_byte_count
0167  * Byte count of received packets including additional two
0168  * Reserved Bytes that are append to the end of the frame.
0169  * Reserved for Send CQE.
0170  */
0171 MLXSW_ITEM32(pci, cqe, byte_count, 0x04, 0, 14);
0172
0173 #define MLXSW_PCI_CQE2_MIRROR_CONG_INVALID  0xFFFF
0174
0175 /* pci_cqe_mirror_cong_high
0176  * Congestion level in units of 8KB of the egress traffic class of the original
0177  * packet that does mirroring to the CPU. Value of 0xFFFF means that the
0178  * congestion level is invalid.
0179  */
0180 MLXSW_ITEM32(pci, cqe2, mirror_cong_high, 0x08, 16, 4);
0181
0182 /* pci_cqe_trap_id
0183  * Trap ID that captured the packet.
0184  */
0185 MLXSW_ITEM32(pci, cqe, trap_id, 0x08, 0, 10);
0186
0187 /* pci_cqe_crc
0188  * Length include CRC. Indicates the length field includes
0189  * the packet's CRC.
0190  */
0191 MLXSW_ITEM32(pci, cqe0, crc, 0x0C, 8, 1);
0192 MLXSW_ITEM32(pci, cqe12, crc, 0x0C, 9, 1);
0193 mlxsw_pci_cqe_item_helpers(crc, 0, 12, 12);
0194
0195 /* pci_cqe_e
0196  * CQE with Error.
0197  */
0198 MLXSW_ITEM32(pci, cqe0, e, 0x0C, 7, 1);
0199 MLXSW_ITEM32(pci, cqe12, e, 0x00, 27, 1);
0200 mlxsw_pci_cqe_item_helpers(e, 0, 12, 12);
0201
0202 /* pci_cqe_sr
0203  * 1 - Send Queue
0204  * 0 - Receive Queue
0205  */
0206 MLXSW_ITEM32(pci, cqe0, sr, 0x0C, 6, 1);
0207 MLXSW_ITEM32(pci, cqe12, sr, 0x00, 26, 1);
0208 mlxsw_pci_cqe_item_helpers(sr, 0, 12, 12);
0209
0210 /* pci_cqe_dqn
0211  * Descriptor Queue (DQ) Number.
0212  */
0213 MLXSW_ITEM32(pci, cqe0, dqn, 0x0C, 1, 5);
0214 MLXSW_ITEM32(pci, cqe12, dqn, 0x0C, 1, 6);
0215 mlxsw_pci_cqe_item_helpers(dqn, 0, 12, 12);
0216
0217 /* pci_cqe_time_stamp_low
0218  * Time stamp of the CQE
0219  * Format according to time_stamp_type:
0220  * 0: uSec - 1.024uSec (default for devices which do not support
0221  * time_stamp_type). Only bits 15:0 are valid
0222  * 1: FRC - Free Running Clock - units of 1nSec
0223  * 2: UTC - time_stamp[37:30] = Sec
0224  *    - time_stamp[29:0] = nSec
0225  * 3: Mirror_UTC. UTC time stamp of the original packet that has
0226  * MIRROR_SESSION traps
0227  *   - time_stamp[37:30] = Sec
0228  *   - time_stamp[29:0] = nSec
0229  *   Formats 0..2 are configured by
0230  *   CONFIG_PROFILE.cqe_time_stamp_type for PTP traps
0231  *   Format 3 is used for MIRROR_SESSION traps
0232  *   Note that Spectrum does not reveal FRC, UTC and Mirror_UTC
0233  */
0234 MLXSW_ITEM32(pci, cqe2, time_stamp_low, 0x0C, 16, 16);
0235
0236 #define MLXSW_PCI_CQE2_MIRROR_TCLASS_INVALID    0x1F
0237
0238 /* pci_cqe_mirror_tclass
0239  * The egress traffic class of the original packet that does mirroring to the
0240  * CPU. Value of 0x1F means that the traffic class is invalid.
0241  */
0242 MLXSW_ITEM32(pci, cqe2, mirror_tclass, 0x10, 27, 5);
0243
0244 /* pci_cqe_tx_lag
0245  * The Tx port of a packet that is mirrored / sampled to the CPU is a LAG.
0246  */
0247 MLXSW_ITEM32(pci, cqe2, tx_lag, 0x10, 24, 1);
0248
0249 /* pci_cqe_tx_lag_subport
0250  * The port index within the LAG of a packet that is mirrored / sampled to the
0251  * CPU. Reserved when tx_lag is 0.
0252  */
0253 MLXSW_ITEM32(pci, cqe2, tx_lag_subport, 0x10, 16, 8);
0254
0255 #define MLXSW_PCI_CQE2_TX_PORT_MULTI_PORT   0xFFFE
0256 #define MLXSW_PCI_CQE2_TX_PORT_INVALID      0xFFFF
0257
0258 /* pci_cqe_tx_lag_id
0259  * The Tx LAG ID of the original packet that is mirrored / sampled to the CPU.
0260  * Value of 0xFFFE means multi-port. Value fo 0xFFFF means that the Tx LAG ID
0261  * is invalid. Reserved when tx_lag is 0.
0262  */
0263 MLXSW_ITEM32(pci, cqe2, tx_lag_id, 0x10, 0, 16);
0264
0265 /* pci_cqe_tx_system_port
0266  * The Tx port of the original packet that is mirrored / sampled to the CPU.
0267  * Value of 0xFFFE means multi-port. Value fo 0xFFFF means that the Tx port is
0268  * invalid. Reserved when tx_lag is 1.
0269  */
0270 MLXSW_ITEM32(pci, cqe2, tx_system_port, 0x10, 0, 16);
0271
0272 /* pci_cqe_mirror_cong_low
0273  * Congestion level in units of 8KB of the egress traffic class of the original
0274  * packet that does mirroring to the CPU. Value of 0xFFFF means that the
0275  * congestion level is invalid.
0276  */
0277 MLXSW_ITEM32(pci, cqe2, mirror_cong_low, 0x14, 20, 12);
0278
0279 #define MLXSW_PCI_CQE2_MIRROR_CONG_SHIFT    13  /* Units of 8KB. */
0280
0281 static inline u16 mlxsw_pci_cqe2_mirror_cong_get(const char *cqe)
0282 {
0283     u16 cong_high = mlxsw_pci_cqe2_mirror_cong_high_get(cqe);
0284     u16 cong_low = mlxsw_pci_cqe2_mirror_cong_low_get(cqe);
0285
0286     return cong_high << 12 | cong_low;
0287 }
0288
0289 /* pci_cqe_user_def_val_orig_pkt_len
0290  * When trap_id is an ACL: User defined value from policy engine action.
0291  */
0292 MLXSW_ITEM32(pci, cqe2, user_def_val_orig_pkt_len, 0x14, 0, 20);
0293
0294 /* pci_cqe_mirror_reason
0295  * Mirror reason.
0296  */
0297 MLXSW_ITEM32(pci, cqe2, mirror_reason, 0x18, 24, 8);
0298
0299 enum mlxsw_pci_cqe_time_stamp_type {
0300     MLXSW_PCI_CQE_TIME_STAMP_TYPE_USEC,
0301     MLXSW_PCI_CQE_TIME_STAMP_TYPE_FRC,
0302     MLXSW_PCI_CQE_TIME_STAMP_TYPE_UTC,
0303     MLXSW_PCI_CQE_TIME_STAMP_TYPE_MIRROR_UTC,
0304 };
0305
0306 /* pci_cqe_time_stamp_type
0307  * Time stamp type:
0308  * 0: uSec - 1.024uSec (default for devices which do not support
0309  * time_stamp_type)
0310  * 1: FRC - Free Running Clock - units of 1nSec
0311  * 2: UTC
0312  * 3: Mirror_UTC. UTC time stamp of the original packet that has
0313  * MIRROR_SESSION traps
0314  */
0315 MLXSW_ITEM32(pci, cqe2, time_stamp_type, 0x18, 22, 2);
0316
0317 #define MLXSW_PCI_CQE2_MIRROR_LATENCY_INVALID   0xFFFFFF
0318
0319 /* pci_cqe_time_stamp_high
0320  * Time stamp of the CQE
0321  * Format according to time_stamp_type:
0322  * 0: uSec - 1.024uSec (default for devices which do not support
0323  * time_stamp_type). Only bits 15:0 are valid
0324  * 1: FRC - Free Running Clock - units of 1nSec
0325  * 2: UTC - time_stamp[37:30] = Sec
0326  *    - time_stamp[29:0] = nSec
0327  * 3: Mirror_UTC. UTC time stamp of the original packet that has
0328  * MIRROR_SESSION traps
0329  *   - time_stamp[37:30] = Sec
0330  *   - time_stamp[29:0] = nSec
0331  *   Formats 0..2 are configured by
0332  *   CONFIG_PROFILE.cqe_time_stamp_type for PTP traps
0333  *   Format 3 is used for MIRROR_SESSION traps
0334  *   Note that Spectrum does not reveal FRC, UTC and Mirror_UTC
0335  */
0336 MLXSW_ITEM32(pci, cqe2, time_stamp_high, 0x18, 0, 22);
0337
0338 static inline u64 mlxsw_pci_cqe2_time_stamp_get(const char *cqe)
0339 {
0340     u64 ts_high = mlxsw_pci_cqe2_time_stamp_high_get(cqe);
0341     u64 ts_low = mlxsw_pci_cqe2_time_stamp_low_get(cqe);
0342
0343     return ts_high << 16 | ts_low;
0344 }
0345
0346 static inline u8 mlxsw_pci_cqe2_time_stamp_sec_get(const char *cqe)
0347 {
0348     u64 full_ts = mlxsw_pci_cqe2_time_stamp_get(cqe);
0349
0350     return full_ts >> 30 & 0xFF;
0351 }
0352
0353 static inline u32 mlxsw_pci_cqe2_time_stamp_nsec_get(const char *cqe)
0354 {
0355     u64 full_ts = mlxsw_pci_cqe2_time_stamp_get(cqe);
0356
0357     return full_ts & 0x3FFFFFFF;
0358 }
0359
0360 /* pci_cqe_mirror_latency
0361  * End-to-end latency of the original packet that does mirroring to the CPU.
0362  * Value of 0xFFFFFF means that the latency is invalid. Units are according to
0363  * MOGCR.mirror_latency_units.
0364  */
0365 MLXSW_ITEM32(pci, cqe2, mirror_latency, 0x1C, 8, 24);
0366
0367 /* pci_cqe_owner
0368  * Ownership bit.
0369  */
0370 MLXSW_ITEM32(pci, cqe01, owner, 0x0C, 0, 1);
0371 MLXSW_ITEM32(pci, cqe2, owner, 0x1C, 0, 1);
0372 mlxsw_pci_cqe_item_helpers(owner, 01, 01, 2);
0373
0374 /* pci_eqe_event_type
0375  * Event type.
0376  */
0377 MLXSW_ITEM32(pci, eqe, event_type, 0x0C, 24, 8);
0378 #define MLXSW_PCI_EQE_EVENT_TYPE_COMP   0x00
0379 #define MLXSW_PCI_EQE_EVENT_TYPE_CMD    0x0A
0380
0381 /* pci_eqe_event_sub_type
0382  * Event type.
0383  */
0384 MLXSW_ITEM32(pci, eqe, event_sub_type, 0x0C, 16, 8);
0385
0386 /* pci_eqe_cqn
0387  * Completion Queue that triggered this EQE.
0388  */
0389 MLXSW_ITEM32(pci, eqe, cqn, 0x0C, 8, 7);
0390
0391 /* pci_eqe_owner
0392  * Ownership bit.
0393  */
0394 MLXSW_ITEM32(pci, eqe, owner, 0x0C, 0, 1);
0395
0396 /* pci_eqe_cmd_token
0397  * Command completion event - token
0398  */
0399 MLXSW_ITEM32(pci, eqe, cmd_token, 0x00, 16, 16);
0400
0401 /* pci_eqe_cmd_status
0402  * Command completion event - status
0403  */
0404 MLXSW_ITEM32(pci, eqe, cmd_status, 0x00, 0, 8);
0405
0406 /* pci_eqe_cmd_out_param_h
0407  * Command completion event - output parameter - higher part
0408  */
0409 MLXSW_ITEM32(pci, eqe, cmd_out_param_h, 0x04, 0, 32);
0410
0411 /* pci_eqe_cmd_out_param_l
0412  * Command completion event - output parameter - lower part
0413  */
0414 MLXSW_ITEM32(pci, eqe, cmd_out_param_l, 0x08, 0, 32);
0415
0416 #endif