mellanox/mlxbf_gige/mlxbf_gige_regs.h

0001 /* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */
0002
0003 /* Header file for Mellanox BlueField GigE register defines
0004  *
0005  * Copyright (C) 2020-2021 NVIDIA CORPORATION & AFFILIATES
0006  */
0007
0008 #ifndef __MLXBF_GIGE_REGS_H__
0009 #define __MLXBF_GIGE_REGS_H__
0010
0011 #define MLXBF_GIGE_VERSION                            0x0000
0012 #define MLXBF_GIGE_VERSION_BF2                        0x0
0013 #define MLXBF_GIGE_STATUS                             0x0010
0014 #define MLXBF_GIGE_STATUS_READY                       BIT(0)
0015 #define MLXBF_GIGE_INT_STATUS                         0x0028
0016 #define MLXBF_GIGE_INT_STATUS_RX_RECEIVE_PACKET       BIT(0)
0017 #define MLXBF_GIGE_INT_STATUS_RX_MAC_ERROR            BIT(1)
0018 #define MLXBF_GIGE_INT_STATUS_RX_TRN_ERROR            BIT(2)
0019 #define MLXBF_GIGE_INT_STATUS_SW_ACCESS_ERROR         BIT(3)
0020 #define MLXBF_GIGE_INT_STATUS_SW_CONFIG_ERROR         BIT(4)
0021 #define MLXBF_GIGE_INT_STATUS_TX_PI_CI_EXCEED_WQ_SIZE BIT(5)
0022 #define MLXBF_GIGE_INT_STATUS_TX_SMALL_FRAME_SIZE     BIT(6)
0023 #define MLXBF_GIGE_INT_STATUS_TX_CHECKSUM_INPUTS      BIT(7)
0024 #define MLXBF_GIGE_INT_STATUS_HW_ACCESS_ERROR         BIT(8)
0025 #define MLXBF_GIGE_INT_EN                             0x0030
0026 #define MLXBF_GIGE_INT_EN_RX_RECEIVE_PACKET           BIT(0)
0027 #define MLXBF_GIGE_INT_EN_RX_MAC_ERROR                BIT(1)
0028 #define MLXBF_GIGE_INT_EN_RX_TRN_ERROR                BIT(2)
0029 #define MLXBF_GIGE_INT_EN_SW_ACCESS_ERROR             BIT(3)
0030 #define MLXBF_GIGE_INT_EN_SW_CONFIG_ERROR             BIT(4)
0031 #define MLXBF_GIGE_INT_EN_TX_PI_CI_EXCEED_WQ_SIZE     BIT(5)
0032 #define MLXBF_GIGE_INT_EN_TX_SMALL_FRAME_SIZE         BIT(6)
0033 #define MLXBF_GIGE_INT_EN_TX_CHECKSUM_INPUTS          BIT(7)
0034 #define MLXBF_GIGE_INT_EN_HW_ACCESS_ERROR             BIT(8)
0035 #define MLXBF_GIGE_INT_MASK                           0x0038
0036 #define MLXBF_GIGE_INT_MASK_RX_RECEIVE_PACKET         BIT(0)
0037 #define MLXBF_GIGE_CONTROL                            0x0040
0038 #define MLXBF_GIGE_CONTROL_PORT_EN                    BIT(0)
0039 #define MLXBF_GIGE_CONTROL_MAC_ID_RANGE_EN            BIT(1)
0040 #define MLXBF_GIGE_CONTROL_EN_SPECIFIC_MAC            BIT(4)
0041 #define MLXBF_GIGE_CONTROL_CLEAN_PORT_EN              BIT(31)
0042 #define MLXBF_GIGE_RX_WQ_BASE                         0x0200
0043 #define MLXBF_GIGE_RX_WQE_SIZE_LOG2                   0x0208
0044 #define MLXBF_GIGE_RX_WQE_SIZE_LOG2_RESET_VAL         7
0045 #define MLXBF_GIGE_RX_CQ_BASE                         0x0210
0046 #define MLXBF_GIGE_TX_WQ_BASE                         0x0218
0047 #define MLXBF_GIGE_TX_WQ_SIZE_LOG2                    0x0220
0048 #define MLXBF_GIGE_TX_WQ_SIZE_LOG2_RESET_VAL          7
0049 #define MLXBF_GIGE_TX_CI_UPDATE_ADDRESS               0x0228
0050 #define MLXBF_GIGE_RX_WQE_PI                          0x0230
0051 #define MLXBF_GIGE_TX_PRODUCER_INDEX                  0x0238
0052 #define MLXBF_GIGE_RX_MAC_FILTER                      0x0240
0053 #define MLXBF_GIGE_RX_MAC_FILTER_STRIDE               0x0008
0054 #define MLXBF_GIGE_RX_DIN_DROP_COUNTER                0x0260
0055 #define MLXBF_GIGE_TX_CONSUMER_INDEX                  0x0310
0056 #define MLXBF_GIGE_TX_CONTROL                         0x0318
0057 #define MLXBF_GIGE_TX_CONTROL_GRACEFUL_STOP           BIT(0)
0058 #define MLXBF_GIGE_TX_STATUS                          0x0388
0059 #define MLXBF_GIGE_TX_STATUS_DATA_FIFO_FULL           BIT(1)
0060 #define MLXBF_GIGE_RX_MAC_FILTER_DMAC_RANGE_START     0x0520
0061 #define MLXBF_GIGE_RX_MAC_FILTER_DMAC_RANGE_END       0x0528
0062 #define MLXBF_GIGE_RX_MAC_FILTER_COUNT_DISC           0x0540
0063 #define MLXBF_GIGE_RX_MAC_FILTER_COUNT_DISC_EN        BIT(0)
0064 #define MLXBF_GIGE_RX_MAC_FILTER_COUNT_PASS           0x0548
0065 #define MLXBF_GIGE_RX_MAC_FILTER_COUNT_PASS_EN        BIT(0)
0066 #define MLXBF_GIGE_RX_PASS_COUNTER_ALL                0x0550
0067 #define MLXBF_GIGE_RX_DISC_COUNTER_ALL                0x0560
0068 #define MLXBF_GIGE_RX                                 0x0578
0069 #define MLXBF_GIGE_RX_STRIP_CRC_EN                    BIT(1)
0070 #define MLXBF_GIGE_RX_DMA                             0x0580
0071 #define MLXBF_GIGE_RX_DMA_EN                          BIT(0)
0072 #define MLXBF_GIGE_RX_CQE_PACKET_CI                   0x05b0
0073 #define MLXBF_GIGE_MAC_CFG                            0x05e8
0074
0075 /* NOTE: MLXBF_GIGE_MAC_CFG is the last defined register offset,
0076  * so use that plus size of single register to derive total size
0077  */
0078 #define MLXBF_GIGE_MMIO_REG_SZ                        (MLXBF_GIGE_MAC_CFG + 8)
0079
0080 #endif /* !defined(__MLXBF_GIGE_REGS_H__) */