mellanox/mlxbf_gige/mlxbf_gige_mdio.c

0001 // SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
0002
0003 /* MDIO support for Mellanox Gigabit Ethernet driver
0004  *
0005  * Copyright (C) 2020-2021 NVIDIA CORPORATION & AFFILIATES
0006  */
0007
0008 #include <linux/acpi.h>
0009 #include <linux/bitfield.h>
0010 #include <linux/delay.h>
0011 #include <linux/device.h>
0012 #include <linux/err.h>
0013 #include <linux/io.h>
0014 #include <linux/iopoll.h>
0015 #include <linux/ioport.h>
0016 #include <linux/irqreturn.h>
0017 #include <linux/jiffies.h>
0018 #include <linux/module.h>
0019 #include <linux/mod_devicetable.h>
0020 #include <linux/phy.h>
0021 #include <linux/platform_device.h>
0022 #include <linux/property.h>
0023
0024 #include "mlxbf_gige.h"
0025 #include "mlxbf_gige_regs.h"
0026
0027 #define MLXBF_GIGE_MDIO_GW_OFFSET   0x0
0028 #define MLXBF_GIGE_MDIO_CFG_OFFSET  0x4
0029
0030 #define MLXBF_GIGE_MDIO_FREQ_REFERENCE 156250000ULL
0031 #define MLXBF_GIGE_MDIO_COREPLL_CONST  16384ULL
0032 #define MLXBF_GIGE_MDC_CLK_NS          400
0033 #define MLXBF_GIGE_MDIO_PLL_I1CLK_REG1 0x4
0034 #define MLXBF_GIGE_MDIO_PLL_I1CLK_REG2 0x8
0035 #define MLXBF_GIGE_MDIO_CORE_F_SHIFT   0
0036 #define MLXBF_GIGE_MDIO_CORE_F_MASK    GENMASK(25, 0)
0037 #define MLXBF_GIGE_MDIO_CORE_R_SHIFT   26
0038 #define MLXBF_GIGE_MDIO_CORE_R_MASK    GENMASK(31, 26)
0039 #define MLXBF_GIGE_MDIO_CORE_OD_SHIFT  0
0040 #define MLXBF_GIGE_MDIO_CORE_OD_MASK   GENMASK(3, 0)
0041
0042 /* Support clause 22 */
0043 #define MLXBF_GIGE_MDIO_CL22_ST1    0x1
0044 #define MLXBF_GIGE_MDIO_CL22_WRITE  0x1
0045 #define MLXBF_GIGE_MDIO_CL22_READ   0x2
0046
0047 /* Busy bit is set by software and cleared by hardware */
0048 #define MLXBF_GIGE_MDIO_SET_BUSY    0x1
0049
0050 /* MDIO GW register bits */
0051 #define MLXBF_GIGE_MDIO_GW_AD_MASK  GENMASK(15, 0)
0052 #define MLXBF_GIGE_MDIO_GW_DEVAD_MASK   GENMASK(20, 16)
0053 #define MLXBF_GIGE_MDIO_GW_PARTAD_MASK  GENMASK(25, 21)
0054 #define MLXBF_GIGE_MDIO_GW_OPCODE_MASK  GENMASK(27, 26)
0055 #define MLXBF_GIGE_MDIO_GW_ST1_MASK GENMASK(28, 28)
0056 #define MLXBF_GIGE_MDIO_GW_BUSY_MASK    GENMASK(30, 30)
0057
0058 /* MDIO config register bits */
0059 #define MLXBF_GIGE_MDIO_CFG_MDIO_MODE_MASK      GENMASK(1, 0)
0060 #define MLXBF_GIGE_MDIO_CFG_MDIO3_3_MASK        GENMASK(2, 2)
0061 #define MLXBF_GIGE_MDIO_CFG_MDIO_FULL_DRIVE_MASK    GENMASK(4, 4)
0062 #define MLXBF_GIGE_MDIO_CFG_MDC_PERIOD_MASK     GENMASK(15, 8)
0063 #define MLXBF_GIGE_MDIO_CFG_MDIO_IN_SAMP_MASK       GENMASK(23, 16)
0064 #define MLXBF_GIGE_MDIO_CFG_MDIO_OUT_SAMP_MASK      GENMASK(31, 24)
0065
0066 #define MLXBF_GIGE_MDIO_CFG_VAL (FIELD_PREP(MLXBF_GIGE_MDIO_CFG_MDIO_MODE_MASK, 1) | \
0067                  FIELD_PREP(MLXBF_GIGE_MDIO_CFG_MDIO3_3_MASK, 1) | \
0068                  FIELD_PREP(MLXBF_GIGE_MDIO_CFG_MDIO_FULL_DRIVE_MASK, 1) | \
0069                  FIELD_PREP(MLXBF_GIGE_MDIO_CFG_MDIO_IN_SAMP_MASK, 6) | \
0070                  FIELD_PREP(MLXBF_GIGE_MDIO_CFG_MDIO_OUT_SAMP_MASK, 13))
0071
0072 #define MLXBF_GIGE_BF2_COREPLL_ADDR 0x02800c30
0073 #define MLXBF_GIGE_BF2_COREPLL_SIZE 0x0000000c
0074
0075 static struct resource corepll_params[] = {
0076     [MLXBF_GIGE_VERSION_BF2] = {
0077         .start = MLXBF_GIGE_BF2_COREPLL_ADDR,
0078         .end = MLXBF_GIGE_BF2_COREPLL_ADDR + MLXBF_GIGE_BF2_COREPLL_SIZE - 1,
0079         .name = "COREPLL_RES"
0080     },
0081 };
0082
0083 /* Returns core clock i1clk in Hz */
0084 static u64 calculate_i1clk(struct mlxbf_gige *priv)
0085 {
0086     u8 core_od, core_r;
0087     u64 freq_output;
0088     u32 reg1, reg2;
0089     u32 core_f;
0090
0091     reg1 = readl(priv->clk_io + MLXBF_GIGE_MDIO_PLL_I1CLK_REG1);
0092     reg2 = readl(priv->clk_io + MLXBF_GIGE_MDIO_PLL_I1CLK_REG2);
0093
0094     core_f = (reg1 & MLXBF_GIGE_MDIO_CORE_F_MASK) >>
0095         MLXBF_GIGE_MDIO_CORE_F_SHIFT;
0096     core_r = (reg1 & MLXBF_GIGE_MDIO_CORE_R_MASK) >>
0097         MLXBF_GIGE_MDIO_CORE_R_SHIFT;
0098     core_od = (reg2 & MLXBF_GIGE_MDIO_CORE_OD_MASK) >>
0099         MLXBF_GIGE_MDIO_CORE_OD_SHIFT;
0100
0101     /* Compute PLL output frequency as follow:
0102      *
0103      *                                     CORE_F / 16384
0104      * freq_output = freq_reference * ----------------------------
0105      *                              (CORE_R + 1) * (CORE_OD + 1)
0106      */
0107     freq_output = div_u64((MLXBF_GIGE_MDIO_FREQ_REFERENCE * core_f),
0108                   MLXBF_GIGE_MDIO_COREPLL_CONST);
0109     freq_output = div_u64(freq_output, (core_r + 1) * (core_od + 1));
0110
0111     return freq_output;
0112 }
0113
0114 /* Formula for encoding the MDIO period. The encoded value is
0115  * passed to the MDIO config register.
0116  *
0117  * mdc_clk = 2*(val + 1)*(core clock in sec)
0118  *
0119  * i1clk is in Hz:
0120  * 400 ns = 2*(val + 1)*(1/i1clk)
0121  *
0122  * val = (((400/10^9) / (1/i1clk) / 2) - 1)
0123  * val = (400/2 * i1clk)/10^9 - 1
0124  */
0125 static u8 mdio_period_map(struct mlxbf_gige *priv)
0126 {
0127     u8 mdio_period;
0128     u64 i1clk;
0129
0130     i1clk = calculate_i1clk(priv);
0131
0132     mdio_period = div_u64((MLXBF_GIGE_MDC_CLK_NS >> 1) * i1clk, 1000000000) - 1;
0133
0134     return mdio_period;
0135 }
0136
0137 static u32 mlxbf_gige_mdio_create_cmd(u16 data, int phy_add,
0138                       int phy_reg, u32 opcode)
0139 {
0140     u32 gw_reg = 0;
0141
0142     gw_reg |= FIELD_PREP(MLXBF_GIGE_MDIO_GW_AD_MASK, data);
0143     gw_reg |= FIELD_PREP(MLXBF_GIGE_MDIO_GW_DEVAD_MASK, phy_reg);
0144     gw_reg |= FIELD_PREP(MLXBF_GIGE_MDIO_GW_PARTAD_MASK, phy_add);
0145     gw_reg |= FIELD_PREP(MLXBF_GIGE_MDIO_GW_OPCODE_MASK, opcode);
0146     gw_reg |= FIELD_PREP(MLXBF_GIGE_MDIO_GW_ST1_MASK,
0147                  MLXBF_GIGE_MDIO_CL22_ST1);
0148     gw_reg |= FIELD_PREP(MLXBF_GIGE_MDIO_GW_BUSY_MASK,
0149                  MLXBF_GIGE_MDIO_SET_BUSY);
0150
0151     return gw_reg;
0152 }
0153
0154 static int mlxbf_gige_mdio_read(struct mii_bus *bus, int phy_add, int phy_reg)
0155 {
0156     struct mlxbf_gige *priv = bus->priv;
0157     u32 cmd;
0158     int ret;
0159     u32 val;
0160
0161     if (phy_reg & MII_ADDR_C45)
0162         return -EOPNOTSUPP;
0163
0164     /* Send mdio read request */
0165     cmd = mlxbf_gige_mdio_create_cmd(0, phy_add, phy_reg, MLXBF_GIGE_MDIO_CL22_READ);
0166
0167     writel(cmd, priv->mdio_io + MLXBF_GIGE_MDIO_GW_OFFSET);
0168
0169     ret = readl_poll_timeout_atomic(priv->mdio_io + MLXBF_GIGE_MDIO_GW_OFFSET,
0170                     val, !(val & MLXBF_GIGE_MDIO_GW_BUSY_MASK),
0171                     5, 1000000);
0172
0173     if (ret) {
0174         writel(0, priv->mdio_io + MLXBF_GIGE_MDIO_GW_OFFSET);
0175         return ret;
0176     }
0177
0178     ret = readl(priv->mdio_io + MLXBF_GIGE_MDIO_GW_OFFSET);
0179     /* Only return ad bits of the gw register */
0180     ret &= MLXBF_GIGE_MDIO_GW_AD_MASK;
0181
0182     /* The MDIO lock is set on read. To release it, clear gw register */
0183     writel(0, priv->mdio_io + MLXBF_GIGE_MDIO_GW_OFFSET);
0184
0185     return ret;
0186 }
0187
0188 static int mlxbf_gige_mdio_write(struct mii_bus *bus, int phy_add,
0189                  int phy_reg, u16 val)
0190 {
0191     struct mlxbf_gige *priv = bus->priv;
0192     u32 temp;
0193     u32 cmd;
0194     int ret;
0195
0196     if (phy_reg & MII_ADDR_C45)
0197         return -EOPNOTSUPP;
0198
0199     /* Send mdio write request */
0200     cmd = mlxbf_gige_mdio_create_cmd(val, phy_add, phy_reg,
0201                      MLXBF_GIGE_MDIO_CL22_WRITE);
0202     writel(cmd, priv->mdio_io + MLXBF_GIGE_MDIO_GW_OFFSET);
0203
0204     /* If the poll timed out, drop the request */
0205     ret = readl_poll_timeout_atomic(priv->mdio_io + MLXBF_GIGE_MDIO_GW_OFFSET,
0206                     temp, !(temp & MLXBF_GIGE_MDIO_GW_BUSY_MASK),
0207                     5, 1000000);
0208
0209     /* The MDIO lock is set on read. To release it, clear gw register */
0210     writel(0, priv->mdio_io + MLXBF_GIGE_MDIO_GW_OFFSET);
0211
0212     return ret;
0213 }
0214
0215 static void mlxbf_gige_mdio_cfg(struct mlxbf_gige *priv)
0216 {
0217     u8 mdio_period;
0218     u32 val;
0219
0220     mdio_period = mdio_period_map(priv);
0221
0222     val = MLXBF_GIGE_MDIO_CFG_VAL;
0223     val |= FIELD_PREP(MLXBF_GIGE_MDIO_CFG_MDC_PERIOD_MASK, mdio_period);
0224     writel(val, priv->mdio_io + MLXBF_GIGE_MDIO_CFG_OFFSET);
0225 }
0226
0227 int mlxbf_gige_mdio_probe(struct platform_device *pdev, struct mlxbf_gige *priv)
0228 {
0229     struct device *dev = &pdev->dev;
0230     struct resource *res;
0231     int ret;
0232
0233     priv->mdio_io = devm_platform_ioremap_resource(pdev, MLXBF_GIGE_RES_MDIO9);
0234     if (IS_ERR(priv->mdio_io))
0235         return PTR_ERR(priv->mdio_io);
0236
0237     /* clk resource shared with other drivers so cannot use
0238      * devm_platform_ioremap_resource
0239      */
0240     res = platform_get_resource(pdev, IORESOURCE_MEM, MLXBF_GIGE_RES_CLK);
0241     if (!res) {
0242         /* For backward compatibility with older ACPI tables, also keep
0243          * CLK resource internal to the driver.
0244          */
0245         res = &corepll_params[MLXBF_GIGE_VERSION_BF2];
0246     }
0247
0248     priv->clk_io = devm_ioremap(dev, res->start, resource_size(res));
0249     if (!priv->clk_io)
0250         return -ENOMEM;
0251
0252     mlxbf_gige_mdio_cfg(priv);
0253
0254     priv->mdiobus = devm_mdiobus_alloc(dev);
0255     if (!priv->mdiobus) {
0256         dev_err(dev, "Failed to alloc MDIO bus\n");
0257         return -ENOMEM;
0258     }
0259
0260     priv->mdiobus->name = "mlxbf-mdio";
0261     priv->mdiobus->read = mlxbf_gige_mdio_read;
0262     priv->mdiobus->write = mlxbf_gige_mdio_write;
0263     priv->mdiobus->parent = dev;
0264     priv->mdiobus->priv = priv;
0265     snprintf(priv->mdiobus->id, MII_BUS_ID_SIZE, "%s",
0266          dev_name(dev));
0267
0268     ret = mdiobus_register(priv->mdiobus);
0269     if (ret)
0270         dev_err(dev, "Failed to register MDIO bus\n");
0271
0272     return ret;
0273 }
0274
0275 void mlxbf_gige_mdio_remove(struct mlxbf_gige *priv)
0276 {
0277     mdiobus_unregister(priv->mdiobus);
0278 }