mellanox/mlxbf_gige/mlxbf_gige_main.c

0001 // SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
0002
0003 /* Gigabit Ethernet driver for Mellanox BlueField SoC
0004  *
0005  * Copyright (C) 2020-2021 NVIDIA CORPORATION & AFFILIATES
0006  */
0007
0008 #include <linux/acpi.h>
0009 #include <linux/device.h>
0010 #include <linux/dma-mapping.h>
0011 #include <linux/etherdevice.h>
0012 #include <linux/interrupt.h>
0013 #include <linux/iopoll.h>
0014 #include <linux/module.h>
0015 #include <linux/phy.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/skbuff.h>
0018
0019 #include "mlxbf_gige.h"
0020 #include "mlxbf_gige_regs.h"
0021
0022 /* Allocate SKB whose payload pointer aligns with the Bluefield
0023  * hardware DMA limitation, i.e. DMA operation can't cross
0024  * a 4KB boundary.  A maximum packet size of 2KB is assumed in the
0025  * alignment formula.  The alignment logic overallocates an SKB,
0026  * and then adjusts the headroom so that the SKB data pointer is
0027  * naturally aligned to a 2KB boundary.
0028  */
0029 struct sk_buff *mlxbf_gige_alloc_skb(struct mlxbf_gige *priv,
0030                      unsigned int map_len,
0031                      dma_addr_t *buf_dma,
0032                      enum dma_data_direction dir)
0033 {
0034     struct sk_buff *skb;
0035     u64 addr, offset;
0036
0037     /* Overallocate the SKB so that any headroom adjustment (to
0038      * provide 2KB natural alignment) does not exceed payload area
0039      */
0040     skb = netdev_alloc_skb(priv->netdev, MLXBF_GIGE_DEFAULT_BUF_SZ * 2);
0041     if (!skb)
0042         return NULL;
0043
0044     /* Adjust the headroom so that skb->data is naturally aligned to
0045      * a 2KB boundary, which is the maximum packet size supported.
0046      */
0047     addr = (long)skb->data;
0048     offset = (addr + MLXBF_GIGE_DEFAULT_BUF_SZ - 1) &
0049         ~(MLXBF_GIGE_DEFAULT_BUF_SZ - 1);
0050     offset -= addr;
0051     if (offset)
0052         skb_reserve(skb, offset);
0053
0054     /* Return streaming DMA mapping to caller */
0055     *buf_dma = dma_map_single(priv->dev, skb->data, map_len, dir);
0056     if (dma_mapping_error(priv->dev, *buf_dma)) {
0057         dev_kfree_skb(skb);
0058         *buf_dma = (dma_addr_t)0;
0059         return NULL;
0060     }
0061
0062     return skb;
0063 }
0064
0065 static void mlxbf_gige_initial_mac(struct mlxbf_gige *priv)
0066 {
0067     u8 mac[ETH_ALEN];
0068     u64 local_mac;
0069
0070     eth_zero_addr(mac);
0071     mlxbf_gige_get_mac_rx_filter(priv, MLXBF_GIGE_LOCAL_MAC_FILTER_IDX,
0072                      &local_mac);
0073     u64_to_ether_addr(local_mac, mac);
0074
0075     if (is_valid_ether_addr(mac)) {
0076         eth_hw_addr_set(priv->netdev, mac);
0077     } else {
0078         /* Provide a random MAC if for some reason the device has
0079          * not been configured with a valid MAC address already.
0080          */
0081         eth_hw_addr_random(priv->netdev);
0082     }
0083
0084     local_mac = ether_addr_to_u64(priv->netdev->dev_addr);
0085     mlxbf_gige_set_mac_rx_filter(priv, MLXBF_GIGE_LOCAL_MAC_FILTER_IDX,
0086                      local_mac);
0087 }
0088
0089 static void mlxbf_gige_cache_stats(struct mlxbf_gige *priv)
0090 {
0091     struct mlxbf_gige_stats *p;
0092
0093     /* Cache stats that will be cleared by clean port operation */
0094     p = &priv->stats;
0095     p->rx_din_dropped_pkts += readq(priv->base +
0096                     MLXBF_GIGE_RX_DIN_DROP_COUNTER);
0097     p->rx_filter_passed_pkts += readq(priv->base +
0098                       MLXBF_GIGE_RX_PASS_COUNTER_ALL);
0099     p->rx_filter_discard_pkts += readq(priv->base +
0100                        MLXBF_GIGE_RX_DISC_COUNTER_ALL);
0101 }
0102
0103 static int mlxbf_gige_clean_port(struct mlxbf_gige *priv)
0104 {
0105     u64 control;
0106     u64 temp;
0107     int err;
0108
0109     /* Set the CLEAN_PORT_EN bit to trigger SW reset */
0110     control = readq(priv->base + MLXBF_GIGE_CONTROL);
0111     control |= MLXBF_GIGE_CONTROL_CLEAN_PORT_EN;
0112     writeq(control, priv->base + MLXBF_GIGE_CONTROL);
0113
0114     /* Ensure completion of "clean port" write before polling status */
0115     mb();
0116
0117     err = readq_poll_timeout_atomic(priv->base + MLXBF_GIGE_STATUS, temp,
0118                     (temp & MLXBF_GIGE_STATUS_READY),
0119                     100, 100000);
0120
0121     /* Clear the CLEAN_PORT_EN bit at end of this loop */
0122     control = readq(priv->base + MLXBF_GIGE_CONTROL);
0123     control &= ~MLXBF_GIGE_CONTROL_CLEAN_PORT_EN;
0124     writeq(control, priv->base + MLXBF_GIGE_CONTROL);
0125
0126     return err;
0127 }
0128
0129 static int mlxbf_gige_open(struct net_device *netdev)
0130 {
0131     struct mlxbf_gige *priv = netdev_priv(netdev);
0132     struct phy_device *phydev = netdev->phydev;
0133     u64 int_en;
0134     int err;
0135
0136     err = mlxbf_gige_request_irqs(priv);
0137     if (err)
0138         return err;
0139     mlxbf_gige_cache_stats(priv);
0140     err = mlxbf_gige_clean_port(priv);
0141     if (err)
0142         goto free_irqs;
0143
0144     /* Clear driver's valid_polarity to match hardware,
0145      * since the above call to clean_port() resets the
0146      * receive polarity used by hardware.
0147      */
0148     priv->valid_polarity = 0;
0149
0150     err = mlxbf_gige_rx_init(priv);
0151     if (err)
0152         goto free_irqs;
0153     err = mlxbf_gige_tx_init(priv);
0154     if (err)
0155         goto rx_deinit;
0156
0157     phy_start(phydev);
0158
0159     netif_napi_add(netdev, &priv->napi, mlxbf_gige_poll, NAPI_POLL_WEIGHT);
0160     napi_enable(&priv->napi);
0161     netif_start_queue(netdev);
0162
0163     /* Set bits in INT_EN that we care about */
0164     int_en = MLXBF_GIGE_INT_EN_HW_ACCESS_ERROR |
0165          MLXBF_GIGE_INT_EN_TX_CHECKSUM_INPUTS |
0166          MLXBF_GIGE_INT_EN_TX_SMALL_FRAME_SIZE |
0167          MLXBF_GIGE_INT_EN_TX_PI_CI_EXCEED_WQ_SIZE |
0168          MLXBF_GIGE_INT_EN_SW_CONFIG_ERROR |
0169          MLXBF_GIGE_INT_EN_SW_ACCESS_ERROR |
0170          MLXBF_GIGE_INT_EN_RX_RECEIVE_PACKET;
0171
0172     /* Ensure completion of all initialization before enabling interrupts */
0173     mb();
0174
0175     writeq(int_en, priv->base + MLXBF_GIGE_INT_EN);
0176
0177     return 0;
0178
0179 rx_deinit:
0180     mlxbf_gige_rx_deinit(priv);
0181
0182 free_irqs:
0183     mlxbf_gige_free_irqs(priv);
0184     return err;
0185 }
0186
0187 static int mlxbf_gige_stop(struct net_device *netdev)
0188 {
0189     struct mlxbf_gige *priv = netdev_priv(netdev);
0190
0191     writeq(0, priv->base + MLXBF_GIGE_INT_EN);
0192     netif_stop_queue(netdev);
0193     napi_disable(&priv->napi);
0194     netif_napi_del(&priv->napi);
0195     mlxbf_gige_free_irqs(priv);
0196
0197     phy_stop(netdev->phydev);
0198
0199     mlxbf_gige_rx_deinit(priv);
0200     mlxbf_gige_tx_deinit(priv);
0201     mlxbf_gige_cache_stats(priv);
0202     mlxbf_gige_clean_port(priv);
0203
0204     return 0;
0205 }
0206
0207 static int mlxbf_gige_eth_ioctl(struct net_device *netdev,
0208                    struct ifreq *ifr, int cmd)
0209 {
0210     if (!(netif_running(netdev)))
0211         return -EINVAL;
0212
0213     return phy_mii_ioctl(netdev->phydev, ifr, cmd);
0214 }
0215
0216 static void mlxbf_gige_set_rx_mode(struct net_device *netdev)
0217 {
0218     struct mlxbf_gige *priv = netdev_priv(netdev);
0219     bool new_promisc_enabled;
0220
0221     new_promisc_enabled = netdev->flags & IFF_PROMISC;
0222
0223     /* Only write to the hardware registers if the new setting
0224      * of promiscuous mode is different from the current one.
0225      */
0226     if (new_promisc_enabled != priv->promisc_enabled) {
0227         priv->promisc_enabled = new_promisc_enabled;
0228
0229         if (new_promisc_enabled)
0230             mlxbf_gige_enable_promisc(priv);
0231         else
0232             mlxbf_gige_disable_promisc(priv);
0233     }
0234 }
0235
0236 static void mlxbf_gige_get_stats64(struct net_device *netdev,
0237                    struct rtnl_link_stats64 *stats)
0238 {
0239     struct mlxbf_gige *priv = netdev_priv(netdev);
0240
0241     netdev_stats_to_stats64(stats, &netdev->stats);
0242
0243     stats->rx_length_errors = priv->stats.rx_truncate_errors;
0244     stats->rx_fifo_errors = priv->stats.rx_din_dropped_pkts +
0245                 readq(priv->base + MLXBF_GIGE_RX_DIN_DROP_COUNTER);
0246     stats->rx_crc_errors = priv->stats.rx_mac_errors;
0247     stats->rx_errors = stats->rx_length_errors +
0248                stats->rx_fifo_errors +
0249                stats->rx_crc_errors;
0250
0251     stats->tx_fifo_errors = priv->stats.tx_fifo_full;
0252     stats->tx_errors = stats->tx_fifo_errors;
0253 }
0254
0255 static const struct net_device_ops mlxbf_gige_netdev_ops = {
0256     .ndo_open       = mlxbf_gige_open,
0257     .ndo_stop       = mlxbf_gige_stop,
0258     .ndo_start_xmit     = mlxbf_gige_start_xmit,
0259     .ndo_set_mac_address    = eth_mac_addr,
0260     .ndo_validate_addr  = eth_validate_addr,
0261     .ndo_eth_ioctl      = mlxbf_gige_eth_ioctl,
0262     .ndo_set_rx_mode        = mlxbf_gige_set_rx_mode,
0263     .ndo_get_stats64        = mlxbf_gige_get_stats64,
0264 };
0265
0266 static void mlxbf_gige_adjust_link(struct net_device *netdev)
0267 {
0268     struct phy_device *phydev = netdev->phydev;
0269
0270     phy_print_status(phydev);
0271 }
0272
0273 static int mlxbf_gige_probe(struct platform_device *pdev)
0274 {
0275     struct phy_device *phydev;
0276     struct net_device *netdev;
0277     struct mlxbf_gige *priv;
0278     void __iomem *llu_base;
0279     void __iomem *plu_base;
0280     void __iomem *base;
0281     int addr, phy_irq;
0282     u64 control;
0283     int err;
0284
0285     base = devm_platform_ioremap_resource(pdev, MLXBF_GIGE_RES_MAC);
0286     if (IS_ERR(base))
0287         return PTR_ERR(base);
0288
0289     llu_base = devm_platform_ioremap_resource(pdev, MLXBF_GIGE_RES_LLU);
0290     if (IS_ERR(llu_base))
0291         return PTR_ERR(llu_base);
0292
0293     plu_base = devm_platform_ioremap_resource(pdev, MLXBF_GIGE_RES_PLU);
0294     if (IS_ERR(plu_base))
0295         return PTR_ERR(plu_base);
0296
0297     /* Perform general init of GigE block */
0298     control = readq(base + MLXBF_GIGE_CONTROL);
0299     control |= MLXBF_GIGE_CONTROL_PORT_EN;
0300     writeq(control, base + MLXBF_GIGE_CONTROL);
0301
0302     netdev = devm_alloc_etherdev(&pdev->dev, sizeof(*priv));
0303     if (!netdev)
0304         return -ENOMEM;
0305
0306     SET_NETDEV_DEV(netdev, &pdev->dev);
0307     netdev->netdev_ops = &mlxbf_gige_netdev_ops;
0308     netdev->ethtool_ops = &mlxbf_gige_ethtool_ops;
0309     priv = netdev_priv(netdev);
0310     priv->netdev = netdev;
0311
0312     platform_set_drvdata(pdev, priv);
0313     priv->dev = &pdev->dev;
0314     priv->pdev = pdev;
0315
0316     spin_lock_init(&priv->lock);
0317
0318     /* Attach MDIO device */
0319     err = mlxbf_gige_mdio_probe(pdev, priv);
0320     if (err)
0321         return err;
0322
0323     priv->base = base;
0324     priv->llu_base = llu_base;
0325     priv->plu_base = plu_base;
0326
0327     priv->rx_q_entries = MLXBF_GIGE_DEFAULT_RXQ_SZ;
0328     priv->tx_q_entries = MLXBF_GIGE_DEFAULT_TXQ_SZ;
0329
0330     /* Write initial MAC address to hardware */
0331     mlxbf_gige_initial_mac(priv);
0332
0333     err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
0334     if (err) {
0335         dev_err(&pdev->dev, "DMA configuration failed: 0x%x\n", err);
0336         goto out;
0337     }
0338
0339     priv->error_irq = platform_get_irq(pdev, MLXBF_GIGE_ERROR_INTR_IDX);
0340     priv->rx_irq = platform_get_irq(pdev, MLXBF_GIGE_RECEIVE_PKT_INTR_IDX);
0341     priv->llu_plu_irq = platform_get_irq(pdev, MLXBF_GIGE_LLU_PLU_INTR_IDX);
0342
0343     phy_irq = acpi_dev_gpio_irq_get_by(ACPI_COMPANION(&pdev->dev), "phy-gpios", 0);
0344     if (phy_irq < 0) {
0345         dev_err(&pdev->dev, "Error getting PHY irq. Use polling instead");
0346         phy_irq = PHY_POLL;
0347     }
0348
0349     phydev = phy_find_first(priv->mdiobus);
0350     if (!phydev) {
0351         err = -ENODEV;
0352         goto out;
0353     }
0354
0355     addr = phydev->mdio.addr;
0356     priv->mdiobus->irq[addr] = phy_irq;
0357     phydev->irq = phy_irq;
0358
0359     err = phy_connect_direct(netdev, phydev,
0360                  mlxbf_gige_adjust_link,
0361                  PHY_INTERFACE_MODE_GMII);
0362     if (err) {
0363         dev_err(&pdev->dev, "Could not attach to PHY\n");
0364         goto out;
0365     }
0366
0367     /* MAC only supports 1000T full duplex mode */
0368     phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
0369     phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Full_BIT);
0370     phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Half_BIT);
0371     phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Full_BIT);
0372     phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT);
0373
0374     /* Only symmetric pause with flow control enabled is supported so no
0375      * need to negotiate pause.
0376      */
0377     linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->advertising);
0378     linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->advertising);
0379
0380     /* Display information about attached PHY device */
0381     phy_attached_info(phydev);
0382
0383     err = register_netdev(netdev);
0384     if (err) {
0385         dev_err(&pdev->dev, "Failed to register netdev\n");
0386         phy_disconnect(phydev);
0387         goto out;
0388     }
0389
0390     return 0;
0391
0392 out:
0393     mlxbf_gige_mdio_remove(priv);
0394     return err;
0395 }
0396
0397 static int mlxbf_gige_remove(struct platform_device *pdev)
0398 {
0399     struct mlxbf_gige *priv = platform_get_drvdata(pdev);
0400
0401     unregister_netdev(priv->netdev);
0402     phy_disconnect(priv->netdev->phydev);
0403     mlxbf_gige_mdio_remove(priv);
0404     platform_set_drvdata(pdev, NULL);
0405
0406     return 0;
0407 }
0408
0409 static void mlxbf_gige_shutdown(struct platform_device *pdev)
0410 {
0411     struct mlxbf_gige *priv = platform_get_drvdata(pdev);
0412
0413     writeq(0, priv->base + MLXBF_GIGE_INT_EN);
0414     mlxbf_gige_clean_port(priv);
0415 }
0416
0417 static const struct acpi_device_id __maybe_unused mlxbf_gige_acpi_match[] = {
0418     { "MLNXBF17", 0 },
0419     {},
0420 };
0421 MODULE_DEVICE_TABLE(acpi, mlxbf_gige_acpi_match);
0422
0423 static struct platform_driver mlxbf_gige_driver = {
0424     .probe = mlxbf_gige_probe,
0425     .remove = mlxbf_gige_remove,
0426     .shutdown = mlxbf_gige_shutdown,
0427     .driver = {
0428         .name = KBUILD_MODNAME,
0429         .acpi_match_table = ACPI_PTR(mlxbf_gige_acpi_match),
0430     },
0431 };
0432
0433 module_platform_driver(mlxbf_gige_driver);
0434
0435 MODULE_DESCRIPTION("Mellanox BlueField SoC Gigabit Ethernet Driver");
0436 MODULE_AUTHOR("David Thompson <davthompson@nvidia.com>");
0437 MODULE_AUTHOR("Asmaa Mnebhi <asmaa@nvidia.com>");
0438 MODULE_LICENSE("Dual BSD/GPL");