mellanox/mlxbf_gige/mlxbf_gige.h

0001 /* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */
0002
0003 /* Header file for Gigabit Ethernet driver for Mellanox BlueField SoC
0004  * - this file contains software data structures and any chip-specific
0005  *   data structures (e.g. TX WQE format) that are memory resident.
0006  *
0007  * Copyright (C) 2020-2021 NVIDIA CORPORATION & AFFILIATES
0008  */
0009
0010 #ifndef __MLXBF_GIGE_H__
0011 #define __MLXBF_GIGE_H__
0012
0013 #include <linux/io-64-nonatomic-lo-hi.h>
0014 #include <linux/irqreturn.h>
0015 #include <linux/netdevice.h>
0016 #include <linux/irq.h>
0017
0018 /* The silicon design supports a maximum RX ring size of
0019  * 32K entries. Based on current testing this maximum size
0020  * is not required to be supported.  Instead the RX ring
0021  * will be capped at a realistic value of 1024 entries.
0022  */
0023 #define MLXBF_GIGE_MIN_RXQ_SZ     32
0024 #define MLXBF_GIGE_MAX_RXQ_SZ     1024
0025 #define MLXBF_GIGE_DEFAULT_RXQ_SZ 128
0026
0027 #define MLXBF_GIGE_MIN_TXQ_SZ     4
0028 #define MLXBF_GIGE_MAX_TXQ_SZ     256
0029 #define MLXBF_GIGE_DEFAULT_TXQ_SZ 128
0030
0031 #define MLXBF_GIGE_DEFAULT_BUF_SZ 2048
0032
0033 #define MLXBF_GIGE_DMA_PAGE_SZ    4096
0034 #define MLXBF_GIGE_DMA_PAGE_SHIFT 12
0035
0036 /* There are four individual MAC RX filters. Currently
0037  * two of them are being used: one for the broadcast MAC
0038  * (index 0) and one for local MAC (index 1)
0039  */
0040 #define MLXBF_GIGE_BCAST_MAC_FILTER_IDX 0
0041 #define MLXBF_GIGE_LOCAL_MAC_FILTER_IDX 1
0042
0043 /* Define for broadcast MAC literal */
0044 #define BCAST_MAC_ADDR 0xFFFFFFFFFFFF
0045
0046 /* There are three individual interrupts:
0047  *   1) Errors, "OOB" interrupt line
0048  *   2) Receive Packet, "OOB_LLU" interrupt line
0049  *   3) LLU and PLU Events, "OOB_PLU" interrupt line
0050  */
0051 #define MLXBF_GIGE_ERROR_INTR_IDX       0
0052 #define MLXBF_GIGE_RECEIVE_PKT_INTR_IDX 1
0053 #define MLXBF_GIGE_LLU_PLU_INTR_IDX     2
0054
0055 struct mlxbf_gige_stats {
0056     u64 hw_access_errors;
0057     u64 tx_invalid_checksums;
0058     u64 tx_small_frames;
0059     u64 tx_index_errors;
0060     u64 sw_config_errors;
0061     u64 sw_access_errors;
0062     u64 rx_truncate_errors;
0063     u64 rx_mac_errors;
0064     u64 rx_din_dropped_pkts;
0065     u64 tx_fifo_full;
0066     u64 rx_filter_passed_pkts;
0067     u64 rx_filter_discard_pkts;
0068 };
0069
0070 struct mlxbf_gige {
0071     void __iomem *base;
0072     void __iomem *llu_base;
0073     void __iomem *plu_base;
0074     struct device *dev;
0075     struct net_device *netdev;
0076     struct platform_device *pdev;
0077     void __iomem *mdio_io;
0078     void __iomem *clk_io;
0079     struct mii_bus *mdiobus;
0080     spinlock_t lock;      /* for packet processing indices */
0081     u16 rx_q_entries;
0082     u16 tx_q_entries;
0083     u64 *tx_wqe_base;
0084     dma_addr_t tx_wqe_base_dma;
0085     u64 *tx_wqe_next;
0086     u64 *tx_cc;
0087     dma_addr_t tx_cc_dma;
0088     dma_addr_t *rx_wqe_base;
0089     dma_addr_t rx_wqe_base_dma;
0090     u64 *rx_cqe_base;
0091     dma_addr_t rx_cqe_base_dma;
0092     u16 tx_pi;
0093     u16 prev_tx_ci;
0094     struct sk_buff *rx_skb[MLXBF_GIGE_MAX_RXQ_SZ];
0095     struct sk_buff *tx_skb[MLXBF_GIGE_MAX_TXQ_SZ];
0096     int error_irq;
0097     int rx_irq;
0098     int llu_plu_irq;
0099     int phy_irq;
0100     int hw_phy_irq;
0101     bool promisc_enabled;
0102     u8 valid_polarity;
0103     struct napi_struct napi;
0104     struct mlxbf_gige_stats stats;
0105 };
0106
0107 /* Rx Work Queue Element definitions */
0108 #define MLXBF_GIGE_RX_WQE_SZ                   8
0109
0110 /* Rx Completion Queue Element definitions */
0111 #define MLXBF_GIGE_RX_CQE_SZ                   8
0112 #define MLXBF_GIGE_RX_CQE_PKT_LEN_MASK         GENMASK(10, 0)
0113 #define MLXBF_GIGE_RX_CQE_VALID_MASK           GENMASK(11, 11)
0114 #define MLXBF_GIGE_RX_CQE_PKT_STATUS_MASK      GENMASK(15, 12)
0115 #define MLXBF_GIGE_RX_CQE_PKT_STATUS_MAC_ERR   GENMASK(12, 12)
0116 #define MLXBF_GIGE_RX_CQE_PKT_STATUS_TRUNCATED GENMASK(13, 13)
0117 #define MLXBF_GIGE_RX_CQE_CHKSUM_MASK          GENMASK(31, 16)
0118
0119 /* Tx Work Queue Element definitions */
0120 #define MLXBF_GIGE_TX_WQE_SZ_QWORDS            2
0121 #define MLXBF_GIGE_TX_WQE_SZ                   16
0122 #define MLXBF_GIGE_TX_WQE_PKT_LEN_MASK         GENMASK(10, 0)
0123 #define MLXBF_GIGE_TX_WQE_UPDATE_MASK          GENMASK(31, 31)
0124 #define MLXBF_GIGE_TX_WQE_CHKSUM_LEN_MASK      GENMASK(42, 32)
0125 #define MLXBF_GIGE_TX_WQE_CHKSUM_START_MASK    GENMASK(55, 48)
0126 #define MLXBF_GIGE_TX_WQE_CHKSUM_OFFSET_MASK   GENMASK(63, 56)
0127
0128 /* Macro to return packet length of specified TX WQE */
0129 #define MLXBF_GIGE_TX_WQE_PKT_LEN(tx_wqe_addr) \
0130     (*((tx_wqe_addr) + 1) & MLXBF_GIGE_TX_WQE_PKT_LEN_MASK)
0131
0132 /* Tx Completion Count */
0133 #define MLXBF_GIGE_TX_CC_SZ                    8
0134
0135 /* List of resources in ACPI table */
0136 enum mlxbf_gige_res {
0137     MLXBF_GIGE_RES_MAC,
0138     MLXBF_GIGE_RES_MDIO9,
0139     MLXBF_GIGE_RES_GPIO0,
0140     MLXBF_GIGE_RES_LLU,
0141     MLXBF_GIGE_RES_PLU,
0142     MLXBF_GIGE_RES_CLK
0143 };
0144
0145 /* Version of register data returned by mlxbf_gige_get_regs() */
0146 #define MLXBF_GIGE_REGS_VERSION 1
0147
0148 int mlxbf_gige_mdio_probe(struct platform_device *pdev,
0149               struct mlxbf_gige *priv);
0150 void mlxbf_gige_mdio_remove(struct mlxbf_gige *priv);
0151 irqreturn_t mlxbf_gige_mdio_handle_phy_interrupt(int irq, void *dev_id);
0152 void mlxbf_gige_mdio_enable_phy_int(struct mlxbf_gige *priv);
0153
0154 void mlxbf_gige_set_mac_rx_filter(struct mlxbf_gige *priv,
0155                   unsigned int index, u64 dmac);
0156 void mlxbf_gige_get_mac_rx_filter(struct mlxbf_gige *priv,
0157                   unsigned int index, u64 *dmac);
0158 void mlxbf_gige_enable_promisc(struct mlxbf_gige *priv);
0159 void mlxbf_gige_disable_promisc(struct mlxbf_gige *priv);
0160 int mlxbf_gige_rx_init(struct mlxbf_gige *priv);
0161 void mlxbf_gige_rx_deinit(struct mlxbf_gige *priv);
0162 int mlxbf_gige_tx_init(struct mlxbf_gige *priv);
0163 void mlxbf_gige_tx_deinit(struct mlxbf_gige *priv);
0164 bool mlxbf_gige_handle_tx_complete(struct mlxbf_gige *priv);
0165 netdev_tx_t mlxbf_gige_start_xmit(struct sk_buff *skb,
0166                   struct net_device *netdev);
0167 struct sk_buff *mlxbf_gige_alloc_skb(struct mlxbf_gige *priv,
0168                      unsigned int map_len,
0169                      dma_addr_t *buf_dma,
0170                      enum dma_data_direction dir);
0171 int mlxbf_gige_request_irqs(struct mlxbf_gige *priv);
0172 void mlxbf_gige_free_irqs(struct mlxbf_gige *priv);
0173 int mlxbf_gige_poll(struct napi_struct *napi, int budget);
0174 extern const struct ethtool_ops mlxbf_gige_ethtool_ops;
0175 void mlxbf_gige_update_tx_wqe_next(struct mlxbf_gige *priv);
0176
0177 #endif /* !defined(__MLXBF_GIGE_H__) */