mlx5/core/qos.c

0001 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
0002 /* Copyright (c) 2020, Mellanox Technologies inc. All rights reserved. */
0003
0004 #include "qos.h"
0005
0006 #define MLX5_QOS_DEFAULT_DWRR_UID 0
0007
0008 bool mlx5_qos_is_supported(struct mlx5_core_dev *mdev)
0009 {
0010     if (!MLX5_CAP_GEN(mdev, qos))
0011         return false;
0012     if (!MLX5_CAP_QOS(mdev, nic_sq_scheduling))
0013         return false;
0014     if (!MLX5_CAP_QOS(mdev, nic_bw_share))
0015         return false;
0016     if (!MLX5_CAP_QOS(mdev, nic_rate_limit))
0017         return false;
0018     return true;
0019 }
0020
0021 int mlx5_qos_max_leaf_nodes(struct mlx5_core_dev *mdev)
0022 {
0023     return 1 << MLX5_CAP_QOS(mdev, log_max_qos_nic_queue_group);
0024 }
0025
0026 int mlx5_qos_create_leaf_node(struct mlx5_core_dev *mdev, u32 parent_id,
0027                   u32 bw_share, u32 max_avg_bw, u32 *id)
0028 {
0029     u32 sched_ctx[MLX5_ST_SZ_DW(scheduling_context)] = {0};
0030
0031     MLX5_SET(scheduling_context, sched_ctx, parent_element_id, parent_id);
0032     MLX5_SET(scheduling_context, sched_ctx, element_type,
0033          SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP);
0034     MLX5_SET(scheduling_context, sched_ctx, bw_share, bw_share);
0035     MLX5_SET(scheduling_context, sched_ctx, max_average_bw, max_avg_bw);
0036
0037     return mlx5_create_scheduling_element_cmd(mdev, SCHEDULING_HIERARCHY_NIC,
0038                           sched_ctx, id);
0039 }
0040
0041 int mlx5_qos_create_inner_node(struct mlx5_core_dev *mdev, u32 parent_id,
0042                    u32 bw_share, u32 max_avg_bw, u32 *id)
0043 {
0044     u32 sched_ctx[MLX5_ST_SZ_DW(scheduling_context)] = {0};
0045     void *attr;
0046
0047     MLX5_SET(scheduling_context, sched_ctx, parent_element_id, parent_id);
0048     MLX5_SET(scheduling_context, sched_ctx, element_type,
0049          SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR);
0050     MLX5_SET(scheduling_context, sched_ctx, bw_share, bw_share);
0051     MLX5_SET(scheduling_context, sched_ctx, max_average_bw, max_avg_bw);
0052
0053     attr = MLX5_ADDR_OF(scheduling_context, sched_ctx, element_attributes);
0054     MLX5_SET(tsar_element, attr, tsar_type, TSAR_ELEMENT_TSAR_TYPE_DWRR);
0055
0056     return mlx5_create_scheduling_element_cmd(mdev, SCHEDULING_HIERARCHY_NIC,
0057                           sched_ctx, id);
0058 }
0059
0060 int mlx5_qos_create_root_node(struct mlx5_core_dev *mdev, u32 *id)
0061 {
0062     return mlx5_qos_create_inner_node(mdev, MLX5_QOS_DEFAULT_DWRR_UID, 0, 0, id);
0063 }
0064
0065 int mlx5_qos_update_node(struct mlx5_core_dev *mdev, u32 parent_id,
0066              u32 bw_share, u32 max_avg_bw, u32 id)
0067 {
0068     u32 sched_ctx[MLX5_ST_SZ_DW(scheduling_context)] = {0};
0069     u32 bitmask = 0;
0070
0071     MLX5_SET(scheduling_context, sched_ctx, parent_element_id, parent_id);
0072     MLX5_SET(scheduling_context, sched_ctx, bw_share, bw_share);
0073     MLX5_SET(scheduling_context, sched_ctx, max_average_bw, max_avg_bw);
0074
0075     bitmask |= MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE;
0076     bitmask |= MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW;
0077
0078     return mlx5_modify_scheduling_element_cmd(mdev, SCHEDULING_HIERARCHY_NIC,
0079                           sched_ctx, id, bitmask);
0080 }
0081
0082 int mlx5_qos_destroy_node(struct mlx5_core_dev *mdev, u32 id)
0083 {
0084     return mlx5_destroy_scheduling_element_cmd(mdev, SCHEDULING_HIERARCHY_NIC, id);
0085 }