mlx5/core/pci_irq.h

0001 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
0002 /* Copyright (c) 2021, NVIDIA CORPORATION & AFFILIATES. All rights reserved. */
0003
0004 #ifndef __PCI_IRQ_H__
0005 #define __PCI_IRQ_H__
0006
0007 #include <linux/mlx5/driver.h>
0008
0009 #define MLX5_MAX_IRQ_NAME (32)
0010 /* max irq_index is 2047, so four chars */
0011 #define MLX5_MAX_IRQ_IDX_CHARS (4)
0012 #define MLX5_EQ_REFS_PER_IRQ (2)
0013
0014 struct mlx5_irq;
0015
0016 struct mlx5_irq_pool {
0017     char name[MLX5_MAX_IRQ_NAME - MLX5_MAX_IRQ_IDX_CHARS];
0018     struct xa_limit xa_num_irqs;
0019     struct mutex lock; /* sync IRQs creations */
0020     struct xarray irqs;
0021     u32 max_threshold;
0022     u32 min_threshold;
0023     u16 *irqs_per_cpu;
0024     struct mlx5_core_dev *dev;
0025 };
0026
0027 struct mlx5_irq_pool *mlx5_irq_pool_get(struct mlx5_core_dev *dev);
0028 static inline bool mlx5_irq_pool_is_sf_pool(struct mlx5_irq_pool *pool)
0029 {
0030     return !strncmp("mlx5_sf", pool->name, strlen("mlx5_sf"));
0031 }
0032
0033 struct mlx5_irq *mlx5_irq_alloc(struct mlx5_irq_pool *pool, int i,
0034                 const struct cpumask *affinity);
0035 int mlx5_irq_get_locked(struct mlx5_irq *irq);
0036 int mlx5_irq_read_locked(struct mlx5_irq *irq);
0037 int mlx5_irq_put(struct mlx5_irq *irq);
0038
0039 #endif /* __PCI_IRQ_H__ */