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0033 #ifndef __LIB_MLX5_H__
0034 #define __LIB_MLX5_H__
0035
0036 #include "mlx5_core.h"
0037
0038 void mlx5_init_reserved_gids(struct mlx5_core_dev *dev);
0039 void mlx5_cleanup_reserved_gids(struct mlx5_core_dev *dev);
0040 int mlx5_core_reserve_gids(struct mlx5_core_dev *dev, unsigned int count);
0041 void mlx5_core_unreserve_gids(struct mlx5_core_dev *dev, unsigned int count);
0042 int mlx5_core_reserved_gid_alloc(struct mlx5_core_dev *dev, int *gid_index);
0043 void mlx5_core_reserved_gid_free(struct mlx5_core_dev *dev, int gid_index);
0044 int mlx5_crdump_enable(struct mlx5_core_dev *dev);
0045 void mlx5_crdump_disable(struct mlx5_core_dev *dev);
0046 int mlx5_crdump_collect(struct mlx5_core_dev *dev, u32 *cr_data);
0047
0048
0049
0050 #define PORT_MODULE_EVENT_MODULE_STATUS_MASK 0xF
0051 #define PORT_MODULE_EVENT_ERROR_TYPE_MASK 0xF
0052
0053 enum port_module_event_status_type {
0054 MLX5_MODULE_STATUS_PLUGGED = 0x1,
0055 MLX5_MODULE_STATUS_UNPLUGGED = 0x2,
0056 MLX5_MODULE_STATUS_ERROR = 0x3,
0057 MLX5_MODULE_STATUS_DISABLED = 0x4,
0058 MLX5_MODULE_STATUS_NUM,
0059 };
0060
0061 enum port_module_event_error_type {
0062 MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED = 0x0,
0063 MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX = 0x1,
0064 MLX5_MODULE_EVENT_ERROR_BUS_STUCK = 0x2,
0065 MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT = 0x3,
0066 MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST = 0x4,
0067 MLX5_MODULE_EVENT_ERROR_UNKNOWN_IDENTIFIER = 0x5,
0068 MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE = 0x6,
0069 MLX5_MODULE_EVENT_ERROR_BAD_CABLE = 0x7,
0070 MLX5_MODULE_EVENT_ERROR_PCIE_POWER_SLOT_EXCEEDED = 0xc,
0071 MLX5_MODULE_EVENT_ERROR_NUM,
0072 };
0073
0074 struct mlx5_pme_stats {
0075 u64 status_counters[MLX5_MODULE_STATUS_NUM];
0076 u64 error_counters[MLX5_MODULE_EVENT_ERROR_NUM];
0077 };
0078
0079 void mlx5_get_pme_stats(struct mlx5_core_dev *dev, struct mlx5_pme_stats *stats);
0080 int mlx5_notifier_call_chain(struct mlx5_events *events, unsigned int event, void *data);
0081
0082
0083 enum {
0084 MLX5_ACCEL_OBJ_TLS_KEY = MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS,
0085 MLX5_ACCEL_OBJ_IPSEC_KEY = MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC,
0086 };
0087
0088 int mlx5_create_encryption_key(struct mlx5_core_dev *mdev,
0089 void *key, u32 sz_bytes,
0090 u32 key_type, u32 *p_key_id);
0091 void mlx5_destroy_encryption_key(struct mlx5_core_dev *mdev, u32 key_id);
0092
0093 static inline struct net *mlx5_core_net(struct mlx5_core_dev *dev)
0094 {
0095 return devlink_net(priv_to_devlink(dev));
0096 }
0097
0098 static inline void mlx5_uplink_netdev_set(struct mlx5_core_dev *mdev, struct net_device *netdev)
0099 {
0100 mdev->mlx5e_res.uplink_netdev = netdev;
0101 }
0102
0103 static inline struct net_device *mlx5_uplink_netdev_get(struct mlx5_core_dev *mdev)
0104 {
0105 return mdev->mlx5e_res.uplink_netdev;
0106 }
0107 #endif