core/lib/aso.h

0001 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
0002 /* Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved. */
0003
0004 #ifndef __MLX5_LIB_ASO_H__
0005 #define __MLX5_LIB_ASO_H__
0006
0007 #include <linux/mlx5/qp.h>
0008 #include "mlx5_core.h"
0009
0010 #define MLX5_ASO_WQEBBS \
0011     (DIV_ROUND_UP(sizeof(struct mlx5_aso_wqe), MLX5_SEND_WQE_BB))
0012 #define MLX5_ASO_WQEBBS_DATA \
0013     (DIV_ROUND_UP(sizeof(struct mlx5_aso_wqe_data), MLX5_SEND_WQE_BB))
0014 #define MLX5_WQE_CTRL_WQE_OPC_MOD_SHIFT 24
0015
0016 struct mlx5_wqe_aso_ctrl_seg {
0017     __be32  va_h;
0018     __be32  va_l; /* include read_enable */
0019     __be32  l_key;
0020     u8      data_mask_mode;
0021     u8      condition_1_0_operand;
0022     u8      condition_1_0_offset;
0023     u8      data_offset_condition_operand;
0024     __be32  condition_0_data;
0025     __be32  condition_0_mask;
0026     __be32  condition_1_data;
0027     __be32  condition_1_mask;
0028     __be64  bitwise_data;
0029     __be64  data_mask;
0030 };
0031
0032 struct mlx5_wqe_aso_data_seg {
0033     __be32  bytewise_data[16];
0034 };
0035
0036 struct mlx5_aso_wqe {
0037     struct mlx5_wqe_ctrl_seg      ctrl;
0038     struct mlx5_wqe_aso_ctrl_seg  aso_ctrl;
0039 };
0040
0041 struct mlx5_aso_wqe_data {
0042     struct mlx5_wqe_ctrl_seg      ctrl;
0043     struct mlx5_wqe_aso_ctrl_seg  aso_ctrl;
0044     struct mlx5_wqe_aso_data_seg  aso_data;
0045 };
0046
0047 enum {
0048     MLX5_ASO_LOGICAL_AND,
0049     MLX5_ASO_LOGICAL_OR,
0050 };
0051
0052 enum {
0053     MLX5_ASO_ALWAYS_FALSE,
0054     MLX5_ASO_ALWAYS_TRUE,
0055     MLX5_ASO_EQUAL,
0056     MLX5_ASO_NOT_EQUAL,
0057     MLX5_ASO_GREATER_OR_EQUAL,
0058     MLX5_ASO_LESSER_OR_EQUAL,
0059     MLX5_ASO_LESSER,
0060     MLX5_ASO_GREATER,
0061     MLX5_ASO_CYCLIC_GREATER,
0062     MLX5_ASO_CYCLIC_LESSER,
0063 };
0064
0065 enum {
0066     MLX5_ASO_DATA_MASK_MODE_BITWISE_64BIT,
0067     MLX5_ASO_DATA_MASK_MODE_BYTEWISE_64BYTE,
0068     MLX5_ASO_DATA_MASK_MODE_CALCULATED_64BYTE,
0069 };
0070
0071 enum {
0072     MLX5_ACCESS_ASO_OPC_MOD_FLOW_METER = 0x2,
0073 };
0074
0075 struct mlx5_aso;
0076
0077 void *mlx5_aso_get_wqe(struct mlx5_aso *aso);
0078 void mlx5_aso_build_wqe(struct mlx5_aso *aso, u8 ds_cnt,
0079             struct mlx5_aso_wqe *aso_wqe,
0080             u32 obj_id, u32 opc_mode);
0081 void mlx5_aso_post_wqe(struct mlx5_aso *aso, bool with_data,
0082                struct mlx5_wqe_ctrl_seg *doorbell_cseg);
0083 int mlx5_aso_poll_cq(struct mlx5_aso *aso, bool with_data, u32 interval_ms);
0084
0085 struct mlx5_aso *mlx5_aso_create(struct mlx5_core_dev *mdev, u32 pdn);
0086 void mlx5_aso_destroy(struct mlx5_aso *aso);
0087 #endif /* __MLX5_LIB_ASO_H__ */