core/fpga/conn.h

0001 /*
0002  * Copyright (c) 2017 Mellanox Technologies. All rights reserved.
0003  *
0004  * This software is available to you under a choice of one of two
0005  * licenses.  You may choose to be licensed under the terms of the GNU
0006  * General Public License (GPL) Version 2, available from the file
0007  * COPYING in the main directory of this source tree, or the
0008  * OpenIB.org BSD license below:
0009  *
0010  *     Redistribution and use in source and binary forms, with or
0011  *     without modification, are permitted provided that the following
0012  *     conditions are met:
0013  *
0014  *      - Redistributions of source code must retain the above
0015  *        copyright notice, this list of conditions and the following
0016  *        disclaimer.
0017  *
0018  *      - Redistributions in binary form must reproduce the above
0019  *        copyright notice, this list of conditions and the following
0020  *        disclaimer in the documentation and/or other materials
0021  *        provided with the distribution.
0022  *
0023  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
0024  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
0025  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
0026  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
0027  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
0028  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
0029  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
0030  * SOFTWARE.
0031  *
0032  */
0033
0034 #ifndef __MLX5_FPGA_CONN_H__
0035 #define __MLX5_FPGA_CONN_H__
0036
0037 #include <linux/mlx5/cq.h>
0038 #include <linux/mlx5/qp.h>
0039
0040 #include "fpga/core.h"
0041 #include "fpga/sdk.h"
0042 #include "wq.h"
0043
0044 struct mlx5_fpga_conn {
0045     struct mlx5_fpga_device *fdev;
0046
0047     void (*recv_cb)(void *cb_arg, struct mlx5_fpga_dma_buf *buf);
0048     void *cb_arg;
0049
0050     /* FPGA QP */
0051     u32 fpga_qpc[MLX5_ST_SZ_DW(fpga_qpc)];
0052     u32 fpga_qpn;
0053
0054     /* CQ */
0055     struct {
0056         struct mlx5_cqwq wq;
0057         struct mlx5_wq_ctrl wq_ctrl;
0058         struct mlx5_core_cq mcq;
0059         struct tasklet_struct tasklet;
0060     } cq;
0061
0062     /* QP */
0063     struct {
0064         bool active;
0065         int sgid_index;
0066         struct mlx5_wq_qp wq;
0067         struct mlx5_wq_ctrl wq_ctrl;
0068         u32 qpn;
0069         struct {
0070             spinlock_t lock; /* Protects all SQ state */
0071             unsigned int pc;
0072             unsigned int cc;
0073             unsigned int size;
0074             struct mlx5_fpga_dma_buf **bufs;
0075             struct list_head backlog;
0076         } sq;
0077         struct {
0078             unsigned int pc;
0079             unsigned int cc;
0080             unsigned int size;
0081             struct mlx5_fpga_dma_buf **bufs;
0082         } rq;
0083     } qp;
0084 };
0085
0086 int mlx5_fpga_conn_device_init(struct mlx5_fpga_device *fdev);
0087 void mlx5_fpga_conn_device_cleanup(struct mlx5_fpga_device *fdev);
0088 struct mlx5_fpga_conn *
0089 mlx5_fpga_conn_create(struct mlx5_fpga_device *fdev,
0090               struct mlx5_fpga_conn_attr *attr,
0091               enum mlx5_ifc_fpga_qp_type qp_type);
0092 void mlx5_fpga_conn_destroy(struct mlx5_fpga_conn *conn);
0093 int mlx5_fpga_conn_send(struct mlx5_fpga_conn *conn,
0094             struct mlx5_fpga_dma_buf *buf);
0095
0096 #endif /* __MLX5_FPGA_CONN_H__ */