core/fpga/cmd.h

0001 /*
0002  * Copyright (c) 2017, Mellanox Technologies, Ltd.  All rights reserved.
0003  *
0004  * This software is available to you under a choice of one of two
0005  * licenses.  You may choose to be licensed under the terms of the GNU
0006  * General Public License (GPL) Version 2, available from the file
0007  * COPYING in the main directory of this source tree, or the
0008  * OpenIB.org BSD license below:
0009  *
0010  *     Redistribution and use in source and binary forms, with or
0011  *     without modification, are permitted provided that the following
0012  *     conditions are met:
0013  *
0014  *      - Redistributions of source code must retain the above
0015  *        copyright notice, this list of conditions and the following
0016  *        disclaimer.
0017  *
0018  *      - Redistributions in binary form must reproduce the above
0019  *        copyright notice, this list of conditions and the following
0020  *        disclaimer in the documentation and/or other materials
0021  *        provided with the distribution.
0022  *
0023  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
0024  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
0025  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
0026  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
0027  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
0028  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
0029  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
0030  * SOFTWARE.
0031  */
0032
0033 #ifndef __MLX5_FPGA_H__
0034 #define __MLX5_FPGA_H__
0035
0036 #include <linux/mlx5/driver.h>
0037
0038 enum mlx5_fpga_id {
0039     MLX5_FPGA_NEWTON = 0,
0040     MLX5_FPGA_EDISON = 1,
0041     MLX5_FPGA_MORSE = 2,
0042     MLX5_FPGA_MORSEQ = 3,
0043 };
0044
0045 enum mlx5_fpga_image {
0046     MLX5_FPGA_IMAGE_USER = 0,
0047     MLX5_FPGA_IMAGE_FACTORY,
0048 };
0049
0050 enum mlx5_fpga_status {
0051     MLX5_FPGA_STATUS_SUCCESS = 0,
0052     MLX5_FPGA_STATUS_FAILURE = 1,
0053     MLX5_FPGA_STATUS_IN_PROGRESS = 2,
0054     MLX5_FPGA_STATUS_NONE = 0xFFFF,
0055 };
0056
0057 struct mlx5_fpga_query {
0058     enum mlx5_fpga_image admin_image;
0059     enum mlx5_fpga_image oper_image;
0060     enum mlx5_fpga_status status;
0061 };
0062
0063 enum mlx5_fpga_qpc_field_select {
0064     MLX5_FPGA_QPC_STATE = BIT(0),
0065 };
0066
0067 struct mlx5_fpga_qp_counters {
0068     u64 rx_ack_packets;
0069     u64 rx_send_packets;
0070     u64 tx_ack_packets;
0071     u64 tx_send_packets;
0072     u64 rx_total_drop;
0073 };
0074
0075 int mlx5_fpga_caps(struct mlx5_core_dev *dev);
0076 int mlx5_fpga_query(struct mlx5_core_dev *dev, struct mlx5_fpga_query *query);
0077 int mlx5_fpga_ctrl_op(struct mlx5_core_dev *dev, u8 op);
0078 int mlx5_fpga_access_reg(struct mlx5_core_dev *dev, u8 size, u64 addr,
0079              void *buf, bool write);
0080 int mlx5_fpga_sbu_caps(struct mlx5_core_dev *dev, void *caps, int size);
0081
0082 int mlx5_fpga_create_qp(struct mlx5_core_dev *dev, void *fpga_qpc,
0083             u32 *fpga_qpn);
0084 int mlx5_fpga_modify_qp(struct mlx5_core_dev *dev, u32 fpga_qpn,
0085             enum mlx5_fpga_qpc_field_select fields, void *fpga_qpc);
0086 int mlx5_fpga_query_qp(struct mlx5_core_dev *dev, u32 fpga_qpn, void *fpga_qpc);
0087 int mlx5_fpga_query_qp_counters(struct mlx5_core_dev *dev, u32 fpga_qpn,
0088                 bool clear, struct mlx5_fpga_qp_counters *data);
0089 int mlx5_fpga_destroy_qp(struct mlx5_core_dev *dev, u32 fpga_qpn);
0090
0091 #endif /* __MLX5_FPGA_H__ */