mlx5/core/en_tc.h

0001 /*
0002  * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
0003  *
0004  * This software is available to you under a choice of one of two
0005  * licenses.  You may choose to be licensed under the terms of the GNU
0006  * General Public License (GPL) Version 2, available from the file
0007  * COPYING in the main directory of this source tree, or the
0008  * OpenIB.org BSD license below:
0009  *
0010  *     Redistribution and use in source and binary forms, with or
0011  *     without modification, are permitted provided that the following
0012  *     conditions are met:
0013  *
0014  *      - Redistributions of source code must retain the above
0015  *        copyright notice, this list of conditions and the following
0016  *        disclaimer.
0017  *
0018  *      - Redistributions in binary form must reproduce the above
0019  *        copyright notice, this list of conditions and the following
0020  *        disclaimer in the documentation and/or other materials
0021  *        provided with the distribution.
0022  *
0023  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
0024  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
0025  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
0026  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
0027  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
0028  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
0029  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
0030  * SOFTWARE.
0031  */
0032
0033 #ifndef __MLX5_EN_TC_H__
0034 #define __MLX5_EN_TC_H__
0035
0036 #include <net/pkt_cls.h>
0037 #include "en.h"
0038 #include "eswitch.h"
0039 #include "en/tc_ct.h"
0040 #include "en/tc_tun.h"
0041 #include "en/tc/int_port.h"
0042 #include "en/tc/meter.h"
0043 #include "en_rep.h"
0044
0045 #define MLX5E_TC_FLOW_ID_MASK 0x0000ffff
0046
0047 #ifdef CONFIG_MLX5_ESWITCH
0048
0049 #define NIC_FLOW_ATTR_SZ (sizeof(struct mlx5_flow_attr) +\
0050               sizeof(struct mlx5_nic_flow_attr))
0051 #define ESW_FLOW_ATTR_SZ (sizeof(struct mlx5_flow_attr) +\
0052               sizeof(struct mlx5_esw_flow_attr))
0053 #define ns_to_attr_sz(ns) (((ns) == MLX5_FLOW_NAMESPACE_FDB) ?\
0054                 ESW_FLOW_ATTR_SZ :\
0055                 NIC_FLOW_ATTR_SZ)
0056
0057 int mlx5e_tc_num_filters(struct mlx5e_priv *priv, unsigned long flags);
0058
0059 struct mlx5e_tc_update_priv {
0060     struct net_device *fwd_dev;
0061 };
0062
0063 struct mlx5_nic_flow_attr {
0064     u32 flow_tag;
0065     u32 hairpin_tirn;
0066     struct mlx5_flow_table *hairpin_ft;
0067 };
0068
0069 struct mlx5_flow_attr {
0070     u32 action;
0071     struct mlx5_fc *counter;
0072     struct mlx5_modify_hdr *modify_hdr;
0073     struct mlx5_ct_attr ct_attr;
0074     struct mlx5e_sample_attr sample_attr;
0075     struct mlx5e_meter_attr meter_attr;
0076     struct mlx5e_tc_flow_parse_attr *parse_attr;
0077     u32 chain;
0078     u16 prio;
0079     u32 dest_chain;
0080     struct mlx5_flow_table *ft;
0081     struct mlx5_flow_table *dest_ft;
0082     u8 inner_match_level;
0083     u8 outer_match_level;
0084     u8 ip_version;
0085     u8 tun_ip_version;
0086     int tunnel_id; /* mapped tunnel id */
0087     u32 flags;
0088     u32 exe_aso_type;
0089     struct list_head list;
0090     struct mlx5e_post_act_handle *post_act_handle;
0091     struct {
0092         /* Indicate whether the parsed flow should be counted for lag mode decision
0093          * making
0094          */
0095         bool count;
0096     } lag;
0097     /* keep this union last */
0098     union {
0099         struct mlx5_esw_flow_attr esw_attr[0];
0100         struct mlx5_nic_flow_attr nic_attr[0];
0101     };
0102 };
0103
0104 enum {
0105     MLX5_ATTR_FLAG_VLAN_HANDLED  = BIT(0),
0106     MLX5_ATTR_FLAG_SLOW_PATH     = BIT(1),
0107     MLX5_ATTR_FLAG_NO_IN_PORT    = BIT(2),
0108     MLX5_ATTR_FLAG_SRC_REWRITE   = BIT(3),
0109     MLX5_ATTR_FLAG_SAMPLE        = BIT(4),
0110     MLX5_ATTR_FLAG_ACCEPT        = BIT(5),
0111     MLX5_ATTR_FLAG_CT            = BIT(6),
0112 };
0113
0114 /* Returns true if any of the flags that require skipping further TC/NF processing are set. */
0115 static inline bool
0116 mlx5e_tc_attr_flags_skip(u32 attr_flags)
0117 {
0118     return attr_flags & (MLX5_ATTR_FLAG_SLOW_PATH | MLX5_ATTR_FLAG_ACCEPT);
0119 }
0120
0121 struct mlx5_rx_tun_attr {
0122     u16 decap_vport;
0123     union {
0124         __be32 v4;
0125         struct in6_addr v6;
0126     } src_ip; /* Valid if decap_vport is not zero */
0127     union {
0128         __be32 v4;
0129         struct in6_addr v6;
0130     } dst_ip; /* Valid if decap_vport is not zero */
0131     u32 vni;
0132 };
0133
0134 #define MLX5E_TC_TABLE_CHAIN_TAG_BITS 16
0135 #define MLX5E_TC_TABLE_CHAIN_TAG_MASK GENMASK(MLX5E_TC_TABLE_CHAIN_TAG_BITS - 1, 0)
0136
0137 #define MLX5E_TC_MAX_INT_PORT_NUM (8)
0138
0139 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
0140
0141 struct tunnel_match_key {
0142     struct flow_dissector_key_control enc_control;
0143     struct flow_dissector_key_keyid enc_key_id;
0144     struct flow_dissector_key_ports enc_tp;
0145     struct flow_dissector_key_ip enc_ip;
0146     union {
0147         struct flow_dissector_key_ipv4_addrs enc_ipv4;
0148         struct flow_dissector_key_ipv6_addrs enc_ipv6;
0149     };
0150
0151     int filter_ifindex;
0152 };
0153
0154 struct tunnel_match_enc_opts {
0155     struct flow_dissector_key_enc_opts key;
0156     struct flow_dissector_key_enc_opts mask;
0157 };
0158
0159 /* Tunnel_id mapping is TUNNEL_INFO_BITS + ENC_OPTS_BITS.
0160  * Upper TUNNEL_INFO_BITS for general tunnel info.
0161  * Lower ENC_OPTS_BITS bits for enc_opts.
0162  */
0163 #define TUNNEL_INFO_BITS 12
0164 #define TUNNEL_INFO_BITS_MASK GENMASK(TUNNEL_INFO_BITS - 1, 0)
0165 #define ENC_OPTS_BITS 11
0166 #define ENC_OPTS_BITS_MASK GENMASK(ENC_OPTS_BITS - 1, 0)
0167 #define TUNNEL_ID_BITS (TUNNEL_INFO_BITS + ENC_OPTS_BITS)
0168 #define TUNNEL_ID_MASK GENMASK(TUNNEL_ID_BITS - 1, 0)
0169
0170 enum {
0171     MLX5E_TC_FLAG_INGRESS_BIT,
0172     MLX5E_TC_FLAG_EGRESS_BIT,
0173     MLX5E_TC_FLAG_NIC_OFFLOAD_BIT,
0174     MLX5E_TC_FLAG_ESW_OFFLOAD_BIT,
0175     MLX5E_TC_FLAG_FT_OFFLOAD_BIT,
0176     MLX5E_TC_FLAG_LAST_EXPORTED_BIT = MLX5E_TC_FLAG_FT_OFFLOAD_BIT,
0177 };
0178
0179 #define MLX5_TC_FLAG(flag) BIT(MLX5E_TC_FLAG_##flag##_BIT)
0180
0181 int mlx5e_tc_esw_init(struct mlx5_rep_uplink_priv *uplink_priv);
0182 void mlx5e_tc_esw_cleanup(struct mlx5_rep_uplink_priv *uplink_priv);
0183
0184 int mlx5e_tc_ht_init(struct rhashtable *tc_ht);
0185 void mlx5e_tc_ht_cleanup(struct rhashtable *tc_ht);
0186
0187 int mlx5e_configure_flower(struct net_device *dev, struct mlx5e_priv *priv,
0188                struct flow_cls_offload *f, unsigned long flags);
0189 int mlx5e_delete_flower(struct net_device *dev, struct mlx5e_priv *priv,
0190             struct flow_cls_offload *f, unsigned long flags);
0191
0192 int mlx5e_stats_flower(struct net_device *dev, struct mlx5e_priv *priv,
0193                struct flow_cls_offload *f, unsigned long flags);
0194
0195 int mlx5e_tc_configure_matchall(struct mlx5e_priv *priv,
0196                 struct tc_cls_matchall_offload *f);
0197 int mlx5e_tc_delete_matchall(struct mlx5e_priv *priv,
0198                  struct tc_cls_matchall_offload *f);
0199 void mlx5e_tc_stats_matchall(struct mlx5e_priv *priv,
0200                  struct tc_cls_matchall_offload *ma);
0201
0202 struct mlx5e_encap_entry;
0203 void mlx5e_tc_encap_flows_add(struct mlx5e_priv *priv,
0204                   struct mlx5e_encap_entry *e,
0205                   struct list_head *flow_list);
0206 void mlx5e_tc_encap_flows_del(struct mlx5e_priv *priv,
0207                   struct mlx5e_encap_entry *e,
0208                   struct list_head *flow_list);
0209 bool mlx5e_encap_take(struct mlx5e_encap_entry *e);
0210 void mlx5e_encap_put(struct mlx5e_priv *priv, struct mlx5e_encap_entry *e);
0211
0212 void mlx5e_take_all_encap_flows(struct mlx5e_encap_entry *e, struct list_head *flow_list);
0213 void mlx5e_put_flow_list(struct mlx5e_priv *priv, struct list_head *flow_list);
0214
0215 struct mlx5e_neigh_hash_entry;
0216 struct mlx5e_encap_entry *
0217 mlx5e_get_next_init_encap(struct mlx5e_neigh_hash_entry *nhe,
0218               struct mlx5e_encap_entry *e);
0219 void mlx5e_tc_update_neigh_used_value(struct mlx5e_neigh_hash_entry *nhe);
0220
0221 void mlx5e_tc_reoffload_flows_work(struct work_struct *work);
0222
0223 enum mlx5e_tc_attr_to_reg {
0224     CHAIN_TO_REG,
0225     VPORT_TO_REG,
0226     TUNNEL_TO_REG,
0227     CTSTATE_TO_REG,
0228     ZONE_TO_REG,
0229     ZONE_RESTORE_TO_REG,
0230     MARK_TO_REG,
0231     LABELS_TO_REG,
0232     FTEID_TO_REG,
0233     NIC_CHAIN_TO_REG,
0234     NIC_ZONE_RESTORE_TO_REG,
0235     PACKET_COLOR_TO_REG,
0236 };
0237
0238 struct mlx5e_tc_attr_to_reg_mapping {
0239     int mfield; /* rewrite field */
0240     int moffset; /* bit offset of mfield */
0241     int mlen; /* bits to rewrite/match */
0242
0243     int soffset; /* byte offset of spec for match */
0244 };
0245
0246 extern struct mlx5e_tc_attr_to_reg_mapping mlx5e_tc_attr_to_reg_mappings[];
0247
0248 #define MLX5_REG_MAPPING_MOFFSET(reg_id) (mlx5e_tc_attr_to_reg_mappings[reg_id].moffset)
0249 #define MLX5_REG_MAPPING_MBITS(reg_id) (mlx5e_tc_attr_to_reg_mappings[reg_id].mlen)
0250 #define MLX5_REG_MAPPING_MASK(reg_id) (GENMASK(mlx5e_tc_attr_to_reg_mappings[reg_id].mlen - 1, 0))
0251
0252 bool mlx5e_is_valid_eswitch_fwd_dev(struct mlx5e_priv *priv,
0253                     struct net_device *out_dev);
0254
0255 int mlx5e_tc_match_to_reg_set(struct mlx5_core_dev *mdev,
0256                   struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
0257                   enum mlx5_flow_namespace_type ns,
0258                   enum mlx5e_tc_attr_to_reg type,
0259                   u32 data);
0260
0261 void mlx5e_tc_match_to_reg_mod_hdr_change(struct mlx5_core_dev *mdev,
0262                       struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
0263                       enum mlx5e_tc_attr_to_reg type,
0264                       int act_id, u32 data);
0265
0266 void mlx5e_tc_match_to_reg_match(struct mlx5_flow_spec *spec,
0267                  enum mlx5e_tc_attr_to_reg type,
0268                  u32 data,
0269                  u32 mask);
0270
0271 void mlx5e_tc_match_to_reg_get_match(struct mlx5_flow_spec *spec,
0272                      enum mlx5e_tc_attr_to_reg type,
0273                      u32 *data,
0274                      u32 *mask);
0275
0276 int mlx5e_tc_match_to_reg_set_and_get_id(struct mlx5_core_dev *mdev,
0277                      struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
0278                      enum mlx5_flow_namespace_type ns,
0279                      enum mlx5e_tc_attr_to_reg type,
0280                      u32 data);
0281
0282 int mlx5e_tc_add_flow_mod_hdr(struct mlx5e_priv *priv,
0283                   struct mlx5e_tc_flow *flow,
0284                   struct mlx5_flow_attr *attr);
0285
0286 void mlx5e_tc_set_ethertype(struct mlx5_core_dev *mdev,
0287                 struct flow_match_basic *match, bool outer,
0288                 void *headers_c, void *headers_v);
0289
0290 int mlx5e_tc_nic_init(struct mlx5e_priv *priv);
0291 void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv);
0292
0293 int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
0294                 void *cb_priv);
0295
0296 struct mlx5_flow_handle *
0297 mlx5e_add_offloaded_nic_rule(struct mlx5e_priv *priv,
0298                  struct mlx5_flow_spec *spec,
0299                  struct mlx5_flow_attr *attr);
0300 void mlx5e_del_offloaded_nic_rule(struct mlx5e_priv *priv,
0301                   struct mlx5_flow_handle *rule,
0302                   struct mlx5_flow_attr *attr);
0303
0304 struct mlx5_flow_handle *
0305 mlx5_tc_rule_insert(struct mlx5e_priv *priv,
0306             struct mlx5_flow_spec *spec,
0307             struct mlx5_flow_attr *attr);
0308 void
0309 mlx5_tc_rule_delete(struct mlx5e_priv *priv,
0310             struct mlx5_flow_handle *rule,
0311             struct mlx5_flow_attr *attr);
0312
0313 bool mlx5e_tc_is_vf_tunnel(struct net_device *out_dev, struct net_device *route_dev);
0314 int mlx5e_tc_query_route_vport(struct net_device *out_dev, struct net_device *route_dev,
0315                    u16 *vport);
0316
0317 int mlx5e_set_fwd_to_int_port_actions(struct mlx5e_priv *priv,
0318                       struct mlx5_flow_attr *attr,
0319                       int ifindex,
0320                       enum mlx5e_tc_int_port_type type,
0321                       u32 *action,
0322                       int out_index);
0323 #else /* CONFIG_MLX5_CLS_ACT */
0324 static inline int  mlx5e_tc_nic_init(struct mlx5e_priv *priv) { return 0; }
0325 static inline void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv) {}
0326 static inline int mlx5e_tc_ht_init(struct rhashtable *tc_ht) { return 0; }
0327 static inline void mlx5e_tc_ht_cleanup(struct rhashtable *tc_ht) {}
0328 static inline int
0329 mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data, void *cb_priv)
0330 { return -EOPNOTSUPP; }
0331
0332 #endif /* CONFIG_MLX5_CLS_ACT */
0333
0334 struct mlx5_flow_attr *mlx5_alloc_flow_attr(enum mlx5_flow_namespace_type type);
0335
0336 struct mlx5_flow_handle *
0337 mlx5e_add_offloaded_nic_rule(struct mlx5e_priv *priv,
0338                  struct mlx5_flow_spec *spec,
0339                  struct mlx5_flow_attr *attr);
0340 void mlx5e_del_offloaded_nic_rule(struct mlx5e_priv *priv,
0341                   struct mlx5_flow_handle *rule,
0342                   struct mlx5_flow_attr *attr);
0343
0344 #else /* CONFIG_MLX5_ESWITCH */
0345 static inline int  mlx5e_tc_nic_init(struct mlx5e_priv *priv) { return 0; }
0346 static inline void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv) {}
0347 static inline int  mlx5e_tc_num_filters(struct mlx5e_priv *priv,
0348                     unsigned long flags)
0349 {
0350     return 0;
0351 }
0352
0353 static inline int
0354 mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data, void *cb_priv)
0355 { return -EOPNOTSUPP; }
0356 #endif
0357
0358 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
0359 struct mlx5e_tc_table *mlx5e_tc_table_alloc(void);
0360 void mlx5e_tc_table_free(struct mlx5e_tc_table *tc);
0361 static inline bool mlx5e_cqe_regb_chain(struct mlx5_cqe64 *cqe)
0362 {
0363 #if IS_ENABLED(CONFIG_NET_TC_SKB_EXT)
0364     u32 chain, reg_b;
0365
0366     reg_b = be32_to_cpu(cqe->ft_metadata);
0367
0368     if (reg_b >> (MLX5E_TC_TABLE_CHAIN_TAG_BITS + ESW_ZONE_ID_BITS))
0369         return false;
0370
0371     chain = reg_b & MLX5E_TC_TABLE_CHAIN_TAG_MASK;
0372     if (chain)
0373         return true;
0374 #endif
0375
0376     return false;
0377 }
0378
0379 bool mlx5e_tc_update_skb(struct mlx5_cqe64 *cqe, struct sk_buff *skb);
0380 #else /* CONFIG_MLX5_CLS_ACT */
0381 static inline struct mlx5e_tc_table *mlx5e_tc_table_alloc(void) { return NULL; }
0382 static inline void mlx5e_tc_table_free(struct mlx5e_tc_table *tc) {}
0383 static inline bool mlx5e_cqe_regb_chain(struct mlx5_cqe64 *cqe)
0384 { return false; }
0385 static inline bool
0386 mlx5e_tc_update_skb(struct mlx5_cqe64 *cqe, struct sk_buff *skb)
0387 { return true; }
0388 #endif
0389
0390 #endif /* __MLX5_EN_TC_H__ */