mlx5/core/en_common.c

0001 /*
0002  * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
0003  *
0004  * This software is available to you under a choice of one of two
0005  * licenses.  You may choose to be licensed under the terms of the GNU
0006  * General Public License (GPL) Version 2, available from the file
0007  * COPYING in the main directory of this source tree, or the
0008  * OpenIB.org BSD license below:
0009  *
0010  *     Redistribution and use in source and binary forms, with or
0011  *     without modification, are permitted provided that the following
0012  *     conditions are met:
0013  *
0014  *      - Redistributions of source code must retain the above
0015  *        copyright notice, this list of conditions and the following
0016  *        disclaimer.
0017  *
0018  *      - Redistributions in binary form must reproduce the above
0019  *        copyright notice, this list of conditions and the following
0020  *        disclaimer in the documentation and/or other materials
0021  *        provided with the distribution.
0022  *
0023  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
0024  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
0025  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
0026  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
0027  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
0028  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
0029  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
0030  * SOFTWARE.
0031  */
0032
0033 #include "en.h"
0034
0035 /* mlx5e global resources should be placed in this file.
0036  * Global resources are common to all the netdevices created on the same nic.
0037  */
0038
0039 void mlx5e_mkey_set_relaxed_ordering(struct mlx5_core_dev *mdev, void *mkc)
0040 {
0041     bool ro_pci_enable = pcie_relaxed_ordering_enabled(mdev->pdev);
0042     bool ro_write = MLX5_CAP_GEN(mdev, relaxed_ordering_write);
0043     bool ro_read = MLX5_CAP_GEN(mdev, relaxed_ordering_read);
0044
0045     MLX5_SET(mkc, mkc, relaxed_ordering_read, ro_pci_enable && ro_read);
0046     MLX5_SET(mkc, mkc, relaxed_ordering_write, ro_pci_enable && ro_write);
0047 }
0048
0049 static int mlx5e_create_mkey(struct mlx5_core_dev *mdev, u32 pdn,
0050                  u32 *mkey)
0051 {
0052     int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
0053     void *mkc;
0054     u32 *in;
0055     int err;
0056
0057     in = kvzalloc(inlen, GFP_KERNEL);
0058     if (!in)
0059         return -ENOMEM;
0060
0061     mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
0062     MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_PA);
0063     MLX5_SET(mkc, mkc, lw, 1);
0064     MLX5_SET(mkc, mkc, lr, 1);
0065     mlx5e_mkey_set_relaxed_ordering(mdev, mkc);
0066     MLX5_SET(mkc, mkc, pd, pdn);
0067     MLX5_SET(mkc, mkc, length64, 1);
0068     MLX5_SET(mkc, mkc, qpn, 0xffffff);
0069
0070     err = mlx5_core_create_mkey(mdev, mkey, in, inlen);
0071
0072     kvfree(in);
0073     return err;
0074 }
0075
0076 int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev)
0077 {
0078     struct mlx5e_hw_objs *res = &mdev->mlx5e_res.hw_objs;
0079     int err;
0080
0081     err = mlx5_core_alloc_pd(mdev, &res->pdn);
0082     if (err) {
0083         mlx5_core_err(mdev, "alloc pd failed, %d\n", err);
0084         return err;
0085     }
0086
0087     err = mlx5_core_alloc_transport_domain(mdev, &res->td.tdn);
0088     if (err) {
0089         mlx5_core_err(mdev, "alloc td failed, %d\n", err);
0090         goto err_dealloc_pd;
0091     }
0092
0093     err = mlx5e_create_mkey(mdev, res->pdn, &res->mkey);
0094     if (err) {
0095         mlx5_core_err(mdev, "create mkey failed, %d\n", err);
0096         goto err_dealloc_transport_domain;
0097     }
0098
0099     err = mlx5_alloc_bfreg(mdev, &res->bfreg, false, false);
0100     if (err) {
0101         mlx5_core_err(mdev, "alloc bfreg failed, %d\n", err);
0102         goto err_destroy_mkey;
0103     }
0104
0105     INIT_LIST_HEAD(&res->td.tirs_list);
0106     mutex_init(&res->td.list_lock);
0107
0108     return 0;
0109
0110 err_destroy_mkey:
0111     mlx5_core_destroy_mkey(mdev, res->mkey);
0112 err_dealloc_transport_domain:
0113     mlx5_core_dealloc_transport_domain(mdev, res->td.tdn);
0114 err_dealloc_pd:
0115     mlx5_core_dealloc_pd(mdev, res->pdn);
0116     return err;
0117 }
0118
0119 void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev)
0120 {
0121     struct mlx5e_hw_objs *res = &mdev->mlx5e_res.hw_objs;
0122
0123     mlx5_free_bfreg(mdev, &res->bfreg);
0124     mlx5_core_destroy_mkey(mdev, res->mkey);
0125     mlx5_core_dealloc_transport_domain(mdev, res->td.tdn);
0126     mlx5_core_dealloc_pd(mdev, res->pdn);
0127     memset(res, 0, sizeof(*res));
0128 }
0129
0130 int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb,
0131                bool enable_mc_lb)
0132 {
0133     struct mlx5_core_dev *mdev = priv->mdev;
0134     struct mlx5e_tir *tir;
0135     u8 lb_flags = 0;
0136     int err  = 0;
0137     u32 tirn = 0;
0138     int inlen;
0139     void *in;
0140
0141     inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
0142     in = kvzalloc(inlen, GFP_KERNEL);
0143     if (!in) {
0144         err = -ENOMEM;
0145         goto out;
0146     }
0147
0148     if (enable_uc_lb)
0149         lb_flags = MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
0150
0151     if (enable_mc_lb)
0152         lb_flags |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST;
0153
0154     if (lb_flags)
0155         MLX5_SET(modify_tir_in, in, ctx.self_lb_block, lb_flags);
0156
0157     MLX5_SET(modify_tir_in, in, bitmask.self_lb_en, 1);
0158
0159     mutex_lock(&mdev->mlx5e_res.hw_objs.td.list_lock);
0160     list_for_each_entry(tir, &mdev->mlx5e_res.hw_objs.td.tirs_list, list) {
0161         tirn = tir->tirn;
0162         err = mlx5_core_modify_tir(mdev, tirn, in);
0163         if (err)
0164             goto out;
0165     }
0166
0167 out:
0168     kvfree(in);
0169     if (err)
0170         netdev_err(priv->netdev, "refresh tir(0x%x) failed, %d\n", tirn, err);
0171     mutex_unlock(&mdev->mlx5e_res.hw_objs.td.list_lock);
0172
0173     return err;
0174 }