Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /* Copyright (C) 2021 Felix Fietkau <nbd@nbd.name> */
0003 
0004 #include <linux/kernel.h>
0005 #include <linux/slab.h>
0006 #include <linux/module.h>
0007 #include <linux/bitfield.h>
0008 #include <linux/dma-mapping.h>
0009 #include <linux/skbuff.h>
0010 #include <linux/of_platform.h>
0011 #include <linux/of_address.h>
0012 #include <linux/mfd/syscon.h>
0013 #include <linux/debugfs.h>
0014 #include <linux/soc/mediatek/mtk_wed.h>
0015 #include "mtk_eth_soc.h"
0016 #include "mtk_wed_regs.h"
0017 #include "mtk_wed.h"
0018 #include "mtk_ppe.h"
0019 
0020 #define MTK_PCIE_BASE(n)        (0x1a143000 + (n) * 0x2000)
0021 
0022 #define MTK_WED_PKT_SIZE        1900
0023 #define MTK_WED_BUF_SIZE        2048
0024 #define MTK_WED_BUF_PER_PAGE        (PAGE_SIZE / 2048)
0025 
0026 #define MTK_WED_TX_RING_SIZE        2048
0027 #define MTK_WED_WDMA_RING_SIZE      1024
0028 
0029 static struct mtk_wed_hw *hw_list[2];
0030 static DEFINE_MUTEX(hw_lock);
0031 
0032 static void
0033 wed_m32(struct mtk_wed_device *dev, u32 reg, u32 mask, u32 val)
0034 {
0035     regmap_update_bits(dev->hw->regs, reg, mask | val, val);
0036 }
0037 
0038 static void
0039 wed_set(struct mtk_wed_device *dev, u32 reg, u32 mask)
0040 {
0041     return wed_m32(dev, reg, 0, mask);
0042 }
0043 
0044 static void
0045 wed_clr(struct mtk_wed_device *dev, u32 reg, u32 mask)
0046 {
0047     return wed_m32(dev, reg, mask, 0);
0048 }
0049 
0050 static void
0051 wdma_m32(struct mtk_wed_device *dev, u32 reg, u32 mask, u32 val)
0052 {
0053     wdma_w32(dev, reg, (wdma_r32(dev, reg) & ~mask) | val);
0054 }
0055 
0056 static void
0057 wdma_set(struct mtk_wed_device *dev, u32 reg, u32 mask)
0058 {
0059     wdma_m32(dev, reg, 0, mask);
0060 }
0061 
0062 static u32
0063 mtk_wed_read_reset(struct mtk_wed_device *dev)
0064 {
0065     return wed_r32(dev, MTK_WED_RESET);
0066 }
0067 
0068 static void
0069 mtk_wed_reset(struct mtk_wed_device *dev, u32 mask)
0070 {
0071     u32 status;
0072 
0073     wed_w32(dev, MTK_WED_RESET, mask);
0074     if (readx_poll_timeout(mtk_wed_read_reset, dev, status,
0075                    !(status & mask), 0, 1000))
0076         WARN_ON_ONCE(1);
0077 }
0078 
0079 static struct mtk_wed_hw *
0080 mtk_wed_assign(struct mtk_wed_device *dev)
0081 {
0082     struct mtk_wed_hw *hw;
0083 
0084     hw = hw_list[pci_domain_nr(dev->wlan.pci_dev->bus)];
0085     if (!hw || hw->wed_dev)
0086         return NULL;
0087 
0088     hw->wed_dev = dev;
0089     return hw;
0090 }
0091 
0092 static int
0093 mtk_wed_buffer_alloc(struct mtk_wed_device *dev)
0094 {
0095     struct mtk_wdma_desc *desc;
0096     dma_addr_t desc_phys;
0097     void **page_list;
0098     int token = dev->wlan.token_start;
0099     int ring_size;
0100     int n_pages;
0101     int i, page_idx;
0102 
0103     ring_size = dev->wlan.nbuf & ~(MTK_WED_BUF_PER_PAGE - 1);
0104     n_pages = ring_size / MTK_WED_BUF_PER_PAGE;
0105 
0106     page_list = kcalloc(n_pages, sizeof(*page_list), GFP_KERNEL);
0107     if (!page_list)
0108         return -ENOMEM;
0109 
0110     dev->buf_ring.size = ring_size;
0111     dev->buf_ring.pages = page_list;
0112 
0113     desc = dma_alloc_coherent(dev->hw->dev, ring_size * sizeof(*desc),
0114                   &desc_phys, GFP_KERNEL);
0115     if (!desc)
0116         return -ENOMEM;
0117 
0118     dev->buf_ring.desc = desc;
0119     dev->buf_ring.desc_phys = desc_phys;
0120 
0121     for (i = 0, page_idx = 0; i < ring_size; i += MTK_WED_BUF_PER_PAGE) {
0122         dma_addr_t page_phys, buf_phys;
0123         struct page *page;
0124         void *buf;
0125         int s;
0126 
0127         page = __dev_alloc_pages(GFP_KERNEL, 0);
0128         if (!page)
0129             return -ENOMEM;
0130 
0131         page_phys = dma_map_page(dev->hw->dev, page, 0, PAGE_SIZE,
0132                      DMA_BIDIRECTIONAL);
0133         if (dma_mapping_error(dev->hw->dev, page_phys)) {
0134             __free_page(page);
0135             return -ENOMEM;
0136         }
0137 
0138         page_list[page_idx++] = page;
0139         dma_sync_single_for_cpu(dev->hw->dev, page_phys, PAGE_SIZE,
0140                     DMA_BIDIRECTIONAL);
0141 
0142         buf = page_to_virt(page);
0143         buf_phys = page_phys;
0144 
0145         for (s = 0; s < MTK_WED_BUF_PER_PAGE; s++) {
0146             u32 txd_size;
0147             u32 ctrl;
0148 
0149             txd_size = dev->wlan.init_buf(buf, buf_phys, token++);
0150 
0151             desc->buf0 = cpu_to_le32(buf_phys);
0152             desc->buf1 = cpu_to_le32(buf_phys + txd_size);
0153             ctrl = FIELD_PREP(MTK_WDMA_DESC_CTRL_LEN0, txd_size) |
0154                    FIELD_PREP(MTK_WDMA_DESC_CTRL_LEN1,
0155                       MTK_WED_BUF_SIZE - txd_size) |
0156                    MTK_WDMA_DESC_CTRL_LAST_SEG1;
0157             desc->ctrl = cpu_to_le32(ctrl);
0158             desc->info = 0;
0159             desc++;
0160 
0161             buf += MTK_WED_BUF_SIZE;
0162             buf_phys += MTK_WED_BUF_SIZE;
0163         }
0164 
0165         dma_sync_single_for_device(dev->hw->dev, page_phys, PAGE_SIZE,
0166                        DMA_BIDIRECTIONAL);
0167     }
0168 
0169     return 0;
0170 }
0171 
0172 static void
0173 mtk_wed_free_buffer(struct mtk_wed_device *dev)
0174 {
0175     struct mtk_wdma_desc *desc = dev->buf_ring.desc;
0176     void **page_list = dev->buf_ring.pages;
0177     int page_idx;
0178     int i;
0179 
0180     if (!page_list)
0181         return;
0182 
0183     if (!desc)
0184         goto free_pagelist;
0185 
0186     for (i = 0, page_idx = 0; i < dev->buf_ring.size; i += MTK_WED_BUF_PER_PAGE) {
0187         void *page = page_list[page_idx++];
0188         dma_addr_t buf_addr;
0189 
0190         if (!page)
0191             break;
0192 
0193         buf_addr = le32_to_cpu(desc[i].buf0);
0194         dma_unmap_page(dev->hw->dev, buf_addr, PAGE_SIZE,
0195                    DMA_BIDIRECTIONAL);
0196         __free_page(page);
0197     }
0198 
0199     dma_free_coherent(dev->hw->dev, dev->buf_ring.size * sizeof(*desc),
0200               desc, dev->buf_ring.desc_phys);
0201 
0202 free_pagelist:
0203     kfree(page_list);
0204 }
0205 
0206 static void
0207 mtk_wed_free_ring(struct mtk_wed_device *dev, struct mtk_wed_ring *ring)
0208 {
0209     if (!ring->desc)
0210         return;
0211 
0212     dma_free_coherent(dev->hw->dev, ring->size * sizeof(*ring->desc),
0213               ring->desc, ring->desc_phys);
0214 }
0215 
0216 static void
0217 mtk_wed_free_tx_rings(struct mtk_wed_device *dev)
0218 {
0219     int i;
0220 
0221     for (i = 0; i < ARRAY_SIZE(dev->tx_ring); i++)
0222         mtk_wed_free_ring(dev, &dev->tx_ring[i]);
0223     for (i = 0; i < ARRAY_SIZE(dev->tx_wdma); i++)
0224         mtk_wed_free_ring(dev, &dev->tx_wdma[i]);
0225 }
0226 
0227 static void
0228 mtk_wed_set_ext_int(struct mtk_wed_device *dev, bool en)
0229 {
0230     u32 mask = MTK_WED_EXT_INT_STATUS_ERROR_MASK;
0231 
0232     if (!dev->hw->num_flows)
0233         mask &= ~MTK_WED_EXT_INT_STATUS_TKID_WO_PYLD;
0234 
0235     wed_w32(dev, MTK_WED_EXT_INT_MASK, en ? mask : 0);
0236     wed_r32(dev, MTK_WED_EXT_INT_MASK);
0237 }
0238 
0239 static void
0240 mtk_wed_stop(struct mtk_wed_device *dev)
0241 {
0242     regmap_write(dev->hw->mirror, dev->hw->index * 4, 0);
0243     mtk_wed_set_ext_int(dev, false);
0244 
0245     wed_clr(dev, MTK_WED_CTRL,
0246         MTK_WED_CTRL_WDMA_INT_AGENT_EN |
0247         MTK_WED_CTRL_WPDMA_INT_AGENT_EN |
0248         MTK_WED_CTRL_WED_TX_BM_EN |
0249         MTK_WED_CTRL_WED_TX_FREE_AGENT_EN);
0250     wed_w32(dev, MTK_WED_WPDMA_INT_TRIGGER, 0);
0251     wed_w32(dev, MTK_WED_WDMA_INT_TRIGGER, 0);
0252     wdma_w32(dev, MTK_WDMA_INT_MASK, 0);
0253     wdma_w32(dev, MTK_WDMA_INT_GRP2, 0);
0254     wed_w32(dev, MTK_WED_WPDMA_INT_MASK, 0);
0255 
0256     wed_clr(dev, MTK_WED_GLO_CFG,
0257         MTK_WED_GLO_CFG_TX_DMA_EN |
0258         MTK_WED_GLO_CFG_RX_DMA_EN);
0259     wed_clr(dev, MTK_WED_WPDMA_GLO_CFG,
0260         MTK_WED_WPDMA_GLO_CFG_TX_DRV_EN |
0261         MTK_WED_WPDMA_GLO_CFG_RX_DRV_EN);
0262     wed_clr(dev, MTK_WED_WDMA_GLO_CFG,
0263         MTK_WED_WDMA_GLO_CFG_RX_DRV_EN);
0264 }
0265 
0266 static void
0267 mtk_wed_detach(struct mtk_wed_device *dev)
0268 {
0269     struct device_node *wlan_node = dev->wlan.pci_dev->dev.of_node;
0270     struct mtk_wed_hw *hw = dev->hw;
0271 
0272     mutex_lock(&hw_lock);
0273 
0274     mtk_wed_stop(dev);
0275 
0276     wdma_w32(dev, MTK_WDMA_RESET_IDX, MTK_WDMA_RESET_IDX_RX);
0277     wdma_w32(dev, MTK_WDMA_RESET_IDX, 0);
0278 
0279     mtk_wed_reset(dev, MTK_WED_RESET_WED);
0280 
0281     mtk_wed_free_buffer(dev);
0282     mtk_wed_free_tx_rings(dev);
0283 
0284     if (of_dma_is_coherent(wlan_node))
0285         regmap_update_bits(hw->hifsys, HIFSYS_DMA_AG_MAP,
0286                    BIT(hw->index), BIT(hw->index));
0287 
0288     if (!hw_list[!hw->index]->wed_dev &&
0289         hw->eth->dma_dev != hw->eth->dev)
0290         mtk_eth_set_dma_device(hw->eth, hw->eth->dev);
0291 
0292     memset(dev, 0, sizeof(*dev));
0293     module_put(THIS_MODULE);
0294 
0295     hw->wed_dev = NULL;
0296     mutex_unlock(&hw_lock);
0297 }
0298 
0299 static void
0300 mtk_wed_hw_init_early(struct mtk_wed_device *dev)
0301 {
0302     u32 mask, set;
0303     u32 offset;
0304 
0305     mtk_wed_stop(dev);
0306     mtk_wed_reset(dev, MTK_WED_RESET_WED);
0307 
0308     mask = MTK_WED_WDMA_GLO_CFG_BT_SIZE |
0309            MTK_WED_WDMA_GLO_CFG_DYNAMIC_DMAD_RECYCLE |
0310            MTK_WED_WDMA_GLO_CFG_RX_DIS_FSM_AUTO_IDLE;
0311     set = FIELD_PREP(MTK_WED_WDMA_GLO_CFG_BT_SIZE, 2) |
0312           MTK_WED_WDMA_GLO_CFG_DYNAMIC_SKIP_DMAD_PREP |
0313           MTK_WED_WDMA_GLO_CFG_IDLE_DMAD_SUPPLY;
0314     wed_m32(dev, MTK_WED_WDMA_GLO_CFG, mask, set);
0315 
0316     wdma_set(dev, MTK_WDMA_GLO_CFG, MTK_WDMA_GLO_CFG_RX_INFO_PRERES);
0317 
0318     offset = dev->hw->index ? 0x04000400 : 0;
0319     wed_w32(dev, MTK_WED_WDMA_OFFSET0, 0x2a042a20 + offset);
0320     wed_w32(dev, MTK_WED_WDMA_OFFSET1, 0x29002800 + offset);
0321 
0322     wed_w32(dev, MTK_WED_PCIE_CFG_BASE, MTK_PCIE_BASE(dev->hw->index));
0323     wed_w32(dev, MTK_WED_WPDMA_CFG_BASE, dev->wlan.wpdma_phys);
0324 }
0325 
0326 static void
0327 mtk_wed_hw_init(struct mtk_wed_device *dev)
0328 {
0329     if (dev->init_done)
0330         return;
0331 
0332     dev->init_done = true;
0333     mtk_wed_set_ext_int(dev, false);
0334     wed_w32(dev, MTK_WED_TX_BM_CTRL,
0335         MTK_WED_TX_BM_CTRL_PAUSE |
0336         FIELD_PREP(MTK_WED_TX_BM_CTRL_VLD_GRP_NUM,
0337                dev->buf_ring.size / 128) |
0338         FIELD_PREP(MTK_WED_TX_BM_CTRL_RSV_GRP_NUM,
0339                MTK_WED_TX_RING_SIZE / 256));
0340 
0341     wed_w32(dev, MTK_WED_TX_BM_BASE, dev->buf_ring.desc_phys);
0342 
0343     wed_w32(dev, MTK_WED_TX_BM_TKID,
0344         FIELD_PREP(MTK_WED_TX_BM_TKID_START,
0345                dev->wlan.token_start) |
0346         FIELD_PREP(MTK_WED_TX_BM_TKID_END,
0347                dev->wlan.token_start + dev->wlan.nbuf - 1));
0348 
0349     wed_w32(dev, MTK_WED_TX_BM_BUF_LEN, MTK_WED_PKT_SIZE);
0350 
0351     wed_w32(dev, MTK_WED_TX_BM_DYN_THR,
0352         FIELD_PREP(MTK_WED_TX_BM_DYN_THR_LO, 1) |
0353         MTK_WED_TX_BM_DYN_THR_HI);
0354 
0355     mtk_wed_reset(dev, MTK_WED_RESET_TX_BM);
0356 
0357     wed_set(dev, MTK_WED_CTRL,
0358         MTK_WED_CTRL_WED_TX_BM_EN |
0359         MTK_WED_CTRL_WED_TX_FREE_AGENT_EN);
0360 
0361     wed_clr(dev, MTK_WED_TX_BM_CTRL, MTK_WED_TX_BM_CTRL_PAUSE);
0362 }
0363 
0364 static void
0365 mtk_wed_ring_reset(struct mtk_wdma_desc *desc, int size)
0366 {
0367     int i;
0368 
0369     for (i = 0; i < size; i++) {
0370         desc[i].buf0 = 0;
0371         desc[i].ctrl = cpu_to_le32(MTK_WDMA_DESC_CTRL_DMA_DONE);
0372         desc[i].buf1 = 0;
0373         desc[i].info = 0;
0374     }
0375 }
0376 
0377 static u32
0378 mtk_wed_check_busy(struct mtk_wed_device *dev)
0379 {
0380     if (wed_r32(dev, MTK_WED_GLO_CFG) & MTK_WED_GLO_CFG_TX_DMA_BUSY)
0381         return true;
0382 
0383     if (wed_r32(dev, MTK_WED_WPDMA_GLO_CFG) &
0384         MTK_WED_WPDMA_GLO_CFG_TX_DRV_BUSY)
0385         return true;
0386 
0387     if (wed_r32(dev, MTK_WED_CTRL) & MTK_WED_CTRL_WDMA_INT_AGENT_BUSY)
0388         return true;
0389 
0390     if (wed_r32(dev, MTK_WED_WDMA_GLO_CFG) &
0391         MTK_WED_WDMA_GLO_CFG_RX_DRV_BUSY)
0392         return true;
0393 
0394     if (wdma_r32(dev, MTK_WDMA_GLO_CFG) &
0395         MTK_WED_WDMA_GLO_CFG_RX_DRV_BUSY)
0396         return true;
0397 
0398     if (wed_r32(dev, MTK_WED_CTRL) &
0399         (MTK_WED_CTRL_WED_TX_BM_BUSY | MTK_WED_CTRL_WED_TX_FREE_AGENT_BUSY))
0400         return true;
0401 
0402     return false;
0403 }
0404 
0405 static int
0406 mtk_wed_poll_busy(struct mtk_wed_device *dev)
0407 {
0408     int sleep = 15000;
0409     int timeout = 100 * sleep;
0410     u32 val;
0411 
0412     return read_poll_timeout(mtk_wed_check_busy, val, !val, sleep,
0413                  timeout, false, dev);
0414 }
0415 
0416 static void
0417 mtk_wed_reset_dma(struct mtk_wed_device *dev)
0418 {
0419     bool busy = false;
0420     u32 val;
0421     int i;
0422 
0423     for (i = 0; i < ARRAY_SIZE(dev->tx_ring); i++) {
0424         struct mtk_wdma_desc *desc = dev->tx_ring[i].desc;
0425 
0426         if (!desc)
0427             continue;
0428 
0429         mtk_wed_ring_reset(desc, MTK_WED_TX_RING_SIZE);
0430     }
0431 
0432     if (mtk_wed_poll_busy(dev))
0433         busy = mtk_wed_check_busy(dev);
0434 
0435     if (busy) {
0436         mtk_wed_reset(dev, MTK_WED_RESET_WED_TX_DMA);
0437     } else {
0438         wed_w32(dev, MTK_WED_RESET_IDX,
0439             MTK_WED_RESET_IDX_TX |
0440             MTK_WED_RESET_IDX_RX);
0441         wed_w32(dev, MTK_WED_RESET_IDX, 0);
0442     }
0443 
0444     wdma_w32(dev, MTK_WDMA_RESET_IDX, MTK_WDMA_RESET_IDX_RX);
0445     wdma_w32(dev, MTK_WDMA_RESET_IDX, 0);
0446 
0447     if (busy) {
0448         mtk_wed_reset(dev, MTK_WED_RESET_WDMA_INT_AGENT);
0449         mtk_wed_reset(dev, MTK_WED_RESET_WDMA_RX_DRV);
0450     } else {
0451         wed_w32(dev, MTK_WED_WDMA_RESET_IDX,
0452             MTK_WED_WDMA_RESET_IDX_RX | MTK_WED_WDMA_RESET_IDX_DRV);
0453         wed_w32(dev, MTK_WED_WDMA_RESET_IDX, 0);
0454 
0455         wed_set(dev, MTK_WED_WDMA_GLO_CFG,
0456             MTK_WED_WDMA_GLO_CFG_RST_INIT_COMPLETE);
0457 
0458         wed_clr(dev, MTK_WED_WDMA_GLO_CFG,
0459             MTK_WED_WDMA_GLO_CFG_RST_INIT_COMPLETE);
0460     }
0461 
0462     for (i = 0; i < 100; i++) {
0463         val = wed_r32(dev, MTK_WED_TX_BM_INTF);
0464         if (FIELD_GET(MTK_WED_TX_BM_INTF_TKFIFO_FDEP, val) == 0x40)
0465             break;
0466     }
0467 
0468     mtk_wed_reset(dev, MTK_WED_RESET_TX_FREE_AGENT);
0469     mtk_wed_reset(dev, MTK_WED_RESET_TX_BM);
0470 
0471     if (busy) {
0472         mtk_wed_reset(dev, MTK_WED_RESET_WPDMA_INT_AGENT);
0473         mtk_wed_reset(dev, MTK_WED_RESET_WPDMA_TX_DRV);
0474         mtk_wed_reset(dev, MTK_WED_RESET_WPDMA_RX_DRV);
0475     } else {
0476         wed_w32(dev, MTK_WED_WPDMA_RESET_IDX,
0477             MTK_WED_WPDMA_RESET_IDX_TX |
0478             MTK_WED_WPDMA_RESET_IDX_RX);
0479         wed_w32(dev, MTK_WED_WPDMA_RESET_IDX, 0);
0480     }
0481 
0482 }
0483 
0484 static int
0485 mtk_wed_ring_alloc(struct mtk_wed_device *dev, struct mtk_wed_ring *ring,
0486            int size)
0487 {
0488     ring->desc = dma_alloc_coherent(dev->hw->dev,
0489                     size * sizeof(*ring->desc),
0490                     &ring->desc_phys, GFP_KERNEL);
0491     if (!ring->desc)
0492         return -ENOMEM;
0493 
0494     ring->size = size;
0495     mtk_wed_ring_reset(ring->desc, size);
0496 
0497     return 0;
0498 }
0499 
0500 static int
0501 mtk_wed_wdma_ring_setup(struct mtk_wed_device *dev, int idx, int size)
0502 {
0503     struct mtk_wed_ring *wdma = &dev->tx_wdma[idx];
0504 
0505     if (mtk_wed_ring_alloc(dev, wdma, MTK_WED_WDMA_RING_SIZE))
0506         return -ENOMEM;
0507 
0508     wdma_w32(dev, MTK_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_BASE,
0509          wdma->desc_phys);
0510     wdma_w32(dev, MTK_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_COUNT,
0511          size);
0512     wdma_w32(dev, MTK_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_CPU_IDX, 0);
0513 
0514     wed_w32(dev, MTK_WED_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_BASE,
0515         wdma->desc_phys);
0516     wed_w32(dev, MTK_WED_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_COUNT,
0517         size);
0518 
0519     return 0;
0520 }
0521 
0522 static void
0523 mtk_wed_start(struct mtk_wed_device *dev, u32 irq_mask)
0524 {
0525     u32 wdma_mask;
0526     u32 val;
0527     int i;
0528 
0529     for (i = 0; i < ARRAY_SIZE(dev->tx_wdma); i++)
0530         if (!dev->tx_wdma[i].desc)
0531             mtk_wed_wdma_ring_setup(dev, i, 16);
0532 
0533     wdma_mask = FIELD_PREP(MTK_WDMA_INT_MASK_RX_DONE, GENMASK(1, 0));
0534 
0535     mtk_wed_hw_init(dev);
0536 
0537     wed_set(dev, MTK_WED_CTRL,
0538         MTK_WED_CTRL_WDMA_INT_AGENT_EN |
0539         MTK_WED_CTRL_WPDMA_INT_AGENT_EN |
0540         MTK_WED_CTRL_WED_TX_BM_EN |
0541         MTK_WED_CTRL_WED_TX_FREE_AGENT_EN);
0542 
0543     wed_w32(dev, MTK_WED_PCIE_INT_TRIGGER, MTK_WED_PCIE_INT_TRIGGER_STATUS);
0544 
0545     wed_w32(dev, MTK_WED_WPDMA_INT_TRIGGER,
0546         MTK_WED_WPDMA_INT_TRIGGER_RX_DONE |
0547         MTK_WED_WPDMA_INT_TRIGGER_TX_DONE);
0548 
0549     wed_set(dev, MTK_WED_WPDMA_INT_CTRL,
0550         MTK_WED_WPDMA_INT_CTRL_SUBRT_ADV);
0551 
0552     wed_w32(dev, MTK_WED_WDMA_INT_TRIGGER, wdma_mask);
0553     wed_clr(dev, MTK_WED_WDMA_INT_CTRL, wdma_mask);
0554 
0555     wdma_w32(dev, MTK_WDMA_INT_MASK, wdma_mask);
0556     wdma_w32(dev, MTK_WDMA_INT_GRP2, wdma_mask);
0557 
0558     wed_w32(dev, MTK_WED_WPDMA_INT_MASK, irq_mask);
0559     wed_w32(dev, MTK_WED_INT_MASK, irq_mask);
0560 
0561     wed_set(dev, MTK_WED_GLO_CFG,
0562         MTK_WED_GLO_CFG_TX_DMA_EN |
0563         MTK_WED_GLO_CFG_RX_DMA_EN);
0564     wed_set(dev, MTK_WED_WPDMA_GLO_CFG,
0565         MTK_WED_WPDMA_GLO_CFG_TX_DRV_EN |
0566         MTK_WED_WPDMA_GLO_CFG_RX_DRV_EN);
0567     wed_set(dev, MTK_WED_WDMA_GLO_CFG,
0568         MTK_WED_WDMA_GLO_CFG_RX_DRV_EN);
0569 
0570     mtk_wed_set_ext_int(dev, true);
0571     val = dev->wlan.wpdma_phys |
0572           MTK_PCIE_MIRROR_MAP_EN |
0573           FIELD_PREP(MTK_PCIE_MIRROR_MAP_WED_ID, dev->hw->index);
0574 
0575     if (dev->hw->index)
0576         val |= BIT(1);
0577     val |= BIT(0);
0578     regmap_write(dev->hw->mirror, dev->hw->index * 4, val);
0579 
0580     dev->running = true;
0581 }
0582 
0583 static int
0584 mtk_wed_attach(struct mtk_wed_device *dev)
0585     __releases(RCU)
0586 {
0587     struct mtk_wed_hw *hw;
0588     int ret = 0;
0589 
0590     RCU_LOCKDEP_WARN(!rcu_read_lock_held(),
0591              "mtk_wed_attach without holding the RCU read lock");
0592 
0593     if (pci_domain_nr(dev->wlan.pci_dev->bus) > 1 ||
0594         !try_module_get(THIS_MODULE))
0595         ret = -ENODEV;
0596 
0597     rcu_read_unlock();
0598 
0599     if (ret)
0600         return ret;
0601 
0602     mutex_lock(&hw_lock);
0603 
0604     hw = mtk_wed_assign(dev);
0605     if (!hw) {
0606         module_put(THIS_MODULE);
0607         ret = -ENODEV;
0608         goto out;
0609     }
0610 
0611     dev_info(&dev->wlan.pci_dev->dev, "attaching wed device %d\n", hw->index);
0612 
0613     dev->hw = hw;
0614     dev->dev = hw->dev;
0615     dev->irq = hw->irq;
0616     dev->wdma_idx = hw->index;
0617 
0618     if (hw->eth->dma_dev == hw->eth->dev &&
0619         of_dma_is_coherent(hw->eth->dev->of_node))
0620         mtk_eth_set_dma_device(hw->eth, hw->dev);
0621 
0622     ret = mtk_wed_buffer_alloc(dev);
0623     if (ret) {
0624         mtk_wed_detach(dev);
0625         goto out;
0626     }
0627 
0628     mtk_wed_hw_init_early(dev);
0629     regmap_update_bits(hw->hifsys, HIFSYS_DMA_AG_MAP, BIT(hw->index), 0);
0630 
0631 out:
0632     mutex_unlock(&hw_lock);
0633 
0634     return ret;
0635 }
0636 
0637 static int
0638 mtk_wed_tx_ring_setup(struct mtk_wed_device *dev, int idx, void __iomem *regs)
0639 {
0640     struct mtk_wed_ring *ring = &dev->tx_ring[idx];
0641 
0642     /*
0643      * Tx ring redirection:
0644      * Instead of configuring the WLAN PDMA TX ring directly, the WLAN
0645      * driver allocated DMA ring gets configured into WED MTK_WED_RING_TX(n)
0646      * registers.
0647      *
0648      * WED driver posts its own DMA ring as WLAN PDMA TX and configures it
0649      * into MTK_WED_WPDMA_RING_TX(n) registers.
0650      * It gets filled with packets picked up from WED TX ring and from
0651      * WDMA RX.
0652      */
0653 
0654     BUG_ON(idx >= ARRAY_SIZE(dev->tx_ring));
0655 
0656     if (mtk_wed_ring_alloc(dev, ring, MTK_WED_TX_RING_SIZE))
0657         return -ENOMEM;
0658 
0659     if (mtk_wed_wdma_ring_setup(dev, idx, MTK_WED_WDMA_RING_SIZE))
0660         return -ENOMEM;
0661 
0662     ring->reg_base = MTK_WED_RING_TX(idx);
0663     ring->wpdma = regs;
0664 
0665     /* WED -> WPDMA */
0666     wpdma_tx_w32(dev, idx, MTK_WED_RING_OFS_BASE, ring->desc_phys);
0667     wpdma_tx_w32(dev, idx, MTK_WED_RING_OFS_COUNT, MTK_WED_TX_RING_SIZE);
0668     wpdma_tx_w32(dev, idx, MTK_WED_RING_OFS_CPU_IDX, 0);
0669 
0670     wed_w32(dev, MTK_WED_WPDMA_RING_TX(idx) + MTK_WED_RING_OFS_BASE,
0671         ring->desc_phys);
0672     wed_w32(dev, MTK_WED_WPDMA_RING_TX(idx) + MTK_WED_RING_OFS_COUNT,
0673         MTK_WED_TX_RING_SIZE);
0674     wed_w32(dev, MTK_WED_WPDMA_RING_TX(idx) + MTK_WED_RING_OFS_CPU_IDX, 0);
0675 
0676     return 0;
0677 }
0678 
0679 static int
0680 mtk_wed_txfree_ring_setup(struct mtk_wed_device *dev, void __iomem *regs)
0681 {
0682     struct mtk_wed_ring *ring = &dev->txfree_ring;
0683     int i;
0684 
0685     /*
0686      * For txfree event handling, the same DMA ring is shared between WED
0687      * and WLAN. The WLAN driver accesses the ring index registers through
0688      * WED
0689      */
0690     ring->reg_base = MTK_WED_RING_RX(1);
0691     ring->wpdma = regs;
0692 
0693     for (i = 0; i < 12; i += 4) {
0694         u32 val = readl(regs + i);
0695 
0696         wed_w32(dev, MTK_WED_RING_RX(1) + i, val);
0697         wed_w32(dev, MTK_WED_WPDMA_RING_RX(1) + i, val);
0698     }
0699 
0700     return 0;
0701 }
0702 
0703 static u32
0704 mtk_wed_irq_get(struct mtk_wed_device *dev, u32 mask)
0705 {
0706     u32 val;
0707 
0708     val = wed_r32(dev, MTK_WED_EXT_INT_STATUS);
0709     wed_w32(dev, MTK_WED_EXT_INT_STATUS, val);
0710     val &= MTK_WED_EXT_INT_STATUS_ERROR_MASK;
0711     if (!dev->hw->num_flows)
0712         val &= ~MTK_WED_EXT_INT_STATUS_TKID_WO_PYLD;
0713     if (val && net_ratelimit())
0714         pr_err("mtk_wed%d: error status=%08x\n", dev->hw->index, val);
0715 
0716     val = wed_r32(dev, MTK_WED_INT_STATUS);
0717     val &= mask;
0718     wed_w32(dev, MTK_WED_INT_STATUS, val); /* ACK */
0719 
0720     return val;
0721 }
0722 
0723 static void
0724 mtk_wed_irq_set_mask(struct mtk_wed_device *dev, u32 mask)
0725 {
0726     if (!dev->running)
0727         return;
0728 
0729     mtk_wed_set_ext_int(dev, !!mask);
0730     wed_w32(dev, MTK_WED_INT_MASK, mask);
0731 }
0732 
0733 int mtk_wed_flow_add(int index)
0734 {
0735     struct mtk_wed_hw *hw = hw_list[index];
0736     int ret;
0737 
0738     if (!hw || !hw->wed_dev)
0739         return -ENODEV;
0740 
0741     if (hw->num_flows) {
0742         hw->num_flows++;
0743         return 0;
0744     }
0745 
0746     mutex_lock(&hw_lock);
0747     if (!hw->wed_dev) {
0748         ret = -ENODEV;
0749         goto out;
0750     }
0751 
0752     ret = hw->wed_dev->wlan.offload_enable(hw->wed_dev);
0753     if (!ret)
0754         hw->num_flows++;
0755     mtk_wed_set_ext_int(hw->wed_dev, true);
0756 
0757 out:
0758     mutex_unlock(&hw_lock);
0759 
0760     return ret;
0761 }
0762 
0763 void mtk_wed_flow_remove(int index)
0764 {
0765     struct mtk_wed_hw *hw = hw_list[index];
0766 
0767     if (!hw)
0768         return;
0769 
0770     if (--hw->num_flows)
0771         return;
0772 
0773     mutex_lock(&hw_lock);
0774     if (!hw->wed_dev)
0775         goto out;
0776 
0777     hw->wed_dev->wlan.offload_disable(hw->wed_dev);
0778     mtk_wed_set_ext_int(hw->wed_dev, true);
0779 
0780 out:
0781     mutex_unlock(&hw_lock);
0782 }
0783 
0784 void mtk_wed_add_hw(struct device_node *np, struct mtk_eth *eth,
0785             void __iomem *wdma, int index)
0786 {
0787     static const struct mtk_wed_ops wed_ops = {
0788         .attach = mtk_wed_attach,
0789         .tx_ring_setup = mtk_wed_tx_ring_setup,
0790         .txfree_ring_setup = mtk_wed_txfree_ring_setup,
0791         .start = mtk_wed_start,
0792         .stop = mtk_wed_stop,
0793         .reset_dma = mtk_wed_reset_dma,
0794         .reg_read = wed_r32,
0795         .reg_write = wed_w32,
0796         .irq_get = mtk_wed_irq_get,
0797         .irq_set_mask = mtk_wed_irq_set_mask,
0798         .detach = mtk_wed_detach,
0799     };
0800     struct device_node *eth_np = eth->dev->of_node;
0801     struct platform_device *pdev;
0802     struct mtk_wed_hw *hw;
0803     struct regmap *regs;
0804     int irq;
0805 
0806     if (!np)
0807         return;
0808 
0809     pdev = of_find_device_by_node(np);
0810     if (!pdev)
0811         return;
0812 
0813     get_device(&pdev->dev);
0814     irq = platform_get_irq(pdev, 0);
0815     if (irq < 0)
0816         return;
0817 
0818     regs = syscon_regmap_lookup_by_phandle(np, NULL);
0819     if (IS_ERR(regs))
0820         return;
0821 
0822     rcu_assign_pointer(mtk_soc_wed_ops, &wed_ops);
0823 
0824     mutex_lock(&hw_lock);
0825 
0826     if (WARN_ON(hw_list[index]))
0827         goto unlock;
0828 
0829     hw = kzalloc(sizeof(*hw), GFP_KERNEL);
0830     if (!hw)
0831         goto unlock;
0832     hw->node = np;
0833     hw->regs = regs;
0834     hw->eth = eth;
0835     hw->dev = &pdev->dev;
0836     hw->wdma = wdma;
0837     hw->index = index;
0838     hw->irq = irq;
0839     hw->mirror = syscon_regmap_lookup_by_phandle(eth_np,
0840                              "mediatek,pcie-mirror");
0841     hw->hifsys = syscon_regmap_lookup_by_phandle(eth_np,
0842                              "mediatek,hifsys");
0843     if (IS_ERR(hw->mirror) || IS_ERR(hw->hifsys)) {
0844         kfree(hw);
0845         goto unlock;
0846     }
0847 
0848     if (!index) {
0849         regmap_write(hw->mirror, 0, 0);
0850         regmap_write(hw->mirror, 4, 0);
0851     }
0852     mtk_wed_hw_add_debugfs(hw);
0853 
0854     hw_list[index] = hw;
0855 
0856 unlock:
0857     mutex_unlock(&hw_lock);
0858 }
0859 
0860 void mtk_wed_exit(void)
0861 {
0862     int i;
0863 
0864     rcu_assign_pointer(mtk_soc_wed_ops, NULL);
0865 
0866     synchronize_rcu();
0867 
0868     for (i = 0; i < ARRAY_SIZE(hw_list); i++) {
0869         struct mtk_wed_hw *hw;
0870 
0871         hw = hw_list[i];
0872         if (!hw)
0873             continue;
0874 
0875         hw_list[i] = NULL;
0876         debugfs_remove(hw->debugfs_dir);
0877         put_device(hw->dev);
0878         kfree(hw);
0879     }
0880 }
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!