octeontx2/nic/otx2_reg.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Marvell RVU Ethernet driver
0003  *
0004  * Copyright (C) 2020 Marvell.
0005  *
0006  */
0007
0008 #ifndef OTX2_REG_H
0009 #define OTX2_REG_H
0010
0011 #include <rvu_struct.h>
0012
0013 /* RVU PF registers */
0014 #define RVU_PF_VFX_PFVF_MBOX0           (0x00000)
0015 #define RVU_PF_VFX_PFVF_MBOX1           (0x00008)
0016 #define RVU_PF_VFX_PFVF_MBOXX(a, b)         (0x0 | (a) << 12 | (b) << 3)
0017 #define RVU_PF_VF_BAR4_ADDR                 (0x10)
0018 #define RVU_PF_BLOCK_ADDRX_DISC(a)          (0x200 | (a) << 3)
0019 #define RVU_PF_VFME_STATUSX(a)              (0x800 | (a) << 3)
0020 #define RVU_PF_VFTRPENDX(a)                 (0x820 | (a) << 3)
0021 #define RVU_PF_VFTRPEND_W1SX(a)             (0x840 | (a) << 3)
0022 #define RVU_PF_VFPF_MBOX_INTX(a)            (0x880 | (a) << 3)
0023 #define RVU_PF_VFPF_MBOX_INT_W1SX(a)        (0x8A0 | (a) << 3)
0024 #define RVU_PF_VFPF_MBOX_INT_ENA_W1SX(a)    (0x8C0 | (a) << 3)
0025 #define RVU_PF_VFPF_MBOX_INT_ENA_W1CX(a)    (0x8E0 | (a) << 3)
0026 #define RVU_PF_VFFLR_INTX(a)                (0x900 | (a) << 3)
0027 #define RVU_PF_VFFLR_INT_W1SX(a)            (0x920 | (a) << 3)
0028 #define RVU_PF_VFFLR_INT_ENA_W1SX(a)        (0x940 | (a) << 3)
0029 #define RVU_PF_VFFLR_INT_ENA_W1CX(a)        (0x960 | (a) << 3)
0030 #define RVU_PF_VFME_INTX(a)                 (0x980 | (a) << 3)
0031 #define RVU_PF_VFME_INT_W1SX(a)             (0x9A0 | (a) << 3)
0032 #define RVU_PF_VFME_INT_ENA_W1SX(a)         (0x9C0 | (a) << 3)
0033 #define RVU_PF_VFME_INT_ENA_W1CX(a)         (0x9E0 | (a) << 3)
0034 #define RVU_PF_PFAF_MBOX0                   (0xC00)
0035 #define RVU_PF_PFAF_MBOX1                   (0xC08)
0036 #define RVU_PF_PFAF_MBOXX(a)                (0xC00 | (a) << 3)
0037 #define RVU_PF_INT                          (0xc20)
0038 #define RVU_PF_INT_W1S                      (0xc28)
0039 #define RVU_PF_INT_ENA_W1S                  (0xc30)
0040 #define RVU_PF_INT_ENA_W1C                  (0xc38)
0041 #define RVU_PF_MSIX_VECX_ADDR(a)            (0x000 | (a) << 4)
0042 #define RVU_PF_MSIX_VECX_CTL(a)             (0x008 | (a) << 4)
0043 #define RVU_PF_MSIX_PBAX(a)                 (0xF0000 | (a) << 3)
0044 #define RVU_PF_VF_MBOX_ADDR                 (0xC40)
0045 #define RVU_PF_LMTLINE_ADDR                 (0xC48)
0046
0047 /* RVU VF registers */
0048 #define RVU_VF_VFPF_MBOX0           (0x00000)
0049 #define RVU_VF_VFPF_MBOX1           (0x00008)
0050 #define RVU_VF_VFPF_MBOXX(a)            (0x00 | (a) << 3)
0051 #define RVU_VF_INT              (0x20)
0052 #define RVU_VF_INT_W1S              (0x28)
0053 #define RVU_VF_INT_ENA_W1S          (0x30)
0054 #define RVU_VF_INT_ENA_W1C          (0x38)
0055 #define RVU_VF_BLOCK_ADDRX_DISC(a)      (0x200 | (a) << 3)
0056 #define RVU_VF_MSIX_VECX_ADDR(a)        (0x000 | (a) << 4)
0057 #define RVU_VF_MSIX_VECX_CTL(a)         (0x008 | (a) << 4)
0058 #define RVU_VF_MSIX_PBAX(a)         (0xF0000 | (a) << 3)
0059 #define RVU_VF_MBOX_REGION                  (0xC0000)
0060
0061 #define RVU_FUNC_BLKADDR_SHIFT      20
0062 #define RVU_FUNC_BLKADDR_MASK       0x1FULL
0063
0064 /* NPA LF registers */
0065 #define NPA_LFBASE          (BLKTYPE_NPA << RVU_FUNC_BLKADDR_SHIFT)
0066 #define NPA_LF_AURA_OP_ALLOCX(a)    (NPA_LFBASE | 0x10 | (a) << 3)
0067 #define NPA_LF_AURA_OP_FREE0            (NPA_LFBASE | 0x20)
0068 #define NPA_LF_AURA_OP_FREE1            (NPA_LFBASE | 0x28)
0069 #define NPA_LF_AURA_OP_CNT              (NPA_LFBASE | 0x30)
0070 #define NPA_LF_AURA_OP_LIMIT            (NPA_LFBASE | 0x50)
0071 #define NPA_LF_AURA_OP_INT              (NPA_LFBASE | 0x60)
0072 #define NPA_LF_AURA_OP_THRESH           (NPA_LFBASE | 0x70)
0073 #define NPA_LF_POOL_OP_PC               (NPA_LFBASE | 0x100)
0074 #define NPA_LF_POOL_OP_AVAILABLE        (NPA_LFBASE | 0x110)
0075 #define NPA_LF_POOL_OP_PTR_START0       (NPA_LFBASE | 0x120)
0076 #define NPA_LF_POOL_OP_PTR_START1       (NPA_LFBASE | 0x128)
0077 #define NPA_LF_POOL_OP_PTR_END0         (NPA_LFBASE | 0x130)
0078 #define NPA_LF_POOL_OP_PTR_END1         (NPA_LFBASE | 0x138)
0079 #define NPA_LF_POOL_OP_INT              (NPA_LFBASE | 0x160)
0080 #define NPA_LF_POOL_OP_THRESH           (NPA_LFBASE | 0x170)
0081 #define NPA_LF_ERR_INT                  (NPA_LFBASE | 0x200)
0082 #define NPA_LF_ERR_INT_W1S              (NPA_LFBASE | 0x208)
0083 #define NPA_LF_ERR_INT_ENA_W1C          (NPA_LFBASE | 0x210)
0084 #define NPA_LF_ERR_INT_ENA_W1S          (NPA_LFBASE | 0x218)
0085 #define NPA_LF_RAS                      (NPA_LFBASE | 0x220)
0086 #define NPA_LF_RAS_W1S                  (NPA_LFBASE | 0x228)
0087 #define NPA_LF_RAS_ENA_W1C              (NPA_LFBASE | 0x230)
0088 #define NPA_LF_RAS_ENA_W1S              (NPA_LFBASE | 0x238)
0089 #define NPA_LF_QINTX_CNT(a)             (NPA_LFBASE | 0x300 | (a) << 12)
0090 #define NPA_LF_QINTX_INT(a)             (NPA_LFBASE | 0x310 | (a) << 12)
0091 #define NPA_LF_QINTX_INT_W1S(a)         (NPA_LFBASE | 0x318 | (a) << 12)
0092 #define NPA_LF_QINTX_ENA_W1S(a)         (NPA_LFBASE | 0x320 | (a) << 12)
0093 #define NPA_LF_QINTX_ENA_W1C(a)         (NPA_LFBASE | 0x330 | (a) << 12)
0094 #define NPA_LF_AURA_BATCH_FREE0         (NPA_LFBASE | 0x400)
0095
0096 /* NIX LF registers */
0097 #define NIX_LFBASE          (BLKTYPE_NIX << RVU_FUNC_BLKADDR_SHIFT)
0098 #define NIX_LF_RX_SECRETX(a)        (NIX_LFBASE | 0x0 | (a) << 3)
0099 #define NIX_LF_CFG          (NIX_LFBASE | 0x100)
0100 #define NIX_LF_GINT         (NIX_LFBASE | 0x200)
0101 #define NIX_LF_GINT_W1S         (NIX_LFBASE | 0x208)
0102 #define NIX_LF_GINT_ENA_W1C     (NIX_LFBASE | 0x210)
0103 #define NIX_LF_GINT_ENA_W1S     (NIX_LFBASE | 0x218)
0104 #define NIX_LF_ERR_INT          (NIX_LFBASE | 0x220)
0105 #define NIX_LF_ERR_INT_W1S      (NIX_LFBASE | 0x228)
0106 #define NIX_LF_ERR_INT_ENA_W1C      (NIX_LFBASE | 0x230)
0107 #define NIX_LF_ERR_INT_ENA_W1S      (NIX_LFBASE | 0x238)
0108 #define NIX_LF_RAS          (NIX_LFBASE | 0x240)
0109 #define NIX_LF_RAS_W1S          (NIX_LFBASE | 0x248)
0110 #define NIX_LF_RAS_ENA_W1C      (NIX_LFBASE | 0x250)
0111 #define NIX_LF_RAS_ENA_W1S      (NIX_LFBASE | 0x258)
0112 #define NIX_LF_SQ_OP_ERR_DBG        (NIX_LFBASE | 0x260)
0113 #define NIX_LF_MNQ_ERR_DBG      (NIX_LFBASE | 0x270)
0114 #define NIX_LF_SEND_ERR_DBG     (NIX_LFBASE | 0x280)
0115 #define NIX_LF_TX_STATX(a)      (NIX_LFBASE | 0x300 | (a) << 3)
0116 #define NIX_LF_RX_STATX(a)      (NIX_LFBASE | 0x400 | (a) << 3)
0117 #define NIX_LF_OP_SENDX(a)      (NIX_LFBASE | 0x800 | (a) << 3)
0118 #define NIX_LF_RQ_OP_INT        (NIX_LFBASE | 0x900)
0119 #define NIX_LF_RQ_OP_OCTS       (NIX_LFBASE | 0x910)
0120 #define NIX_LF_RQ_OP_PKTS       (NIX_LFBASE | 0x920)
0121 #define NIX_LF_OP_IPSEC_DYNO_CN     (NIX_LFBASE | 0x980)
0122 #define NIX_LF_SQ_OP_INT        (NIX_LFBASE | 0xa00)
0123 #define NIX_LF_SQ_OP_OCTS       (NIX_LFBASE | 0xa10)
0124 #define NIX_LF_SQ_OP_PKTS       (NIX_LFBASE | 0xa20)
0125 #define NIX_LF_SQ_OP_STATUS     (NIX_LFBASE | 0xa30)
0126 #define NIX_LF_CQ_OP_INT        (NIX_LFBASE | 0xb00)
0127 #define NIX_LF_CQ_OP_DOOR       (NIX_LFBASE | 0xb30)
0128 #define NIX_LF_CQ_OP_STATUS     (NIX_LFBASE | 0xb40)
0129 #define NIX_LF_QINTX_CNT(a)     (NIX_LFBASE | 0xC00 | (a) << 12)
0130 #define NIX_LF_QINTX_INT(a)     (NIX_LFBASE | 0xC10 | (a) << 12)
0131 #define NIX_LF_QINTX_INT_W1S(a)     (NIX_LFBASE | 0xC18 | (a) << 12)
0132 #define NIX_LF_QINTX_ENA_W1S(a)     (NIX_LFBASE | 0xC20 | (a) << 12)
0133 #define NIX_LF_QINTX_ENA_W1C(a)     (NIX_LFBASE | 0xC30 | (a) << 12)
0134 #define NIX_LF_CINTX_CNT(a)     (NIX_LFBASE | 0xD00 | (a) << 12)
0135 #define NIX_LF_CINTX_WAIT(a)        (NIX_LFBASE | 0xD10 | (a) << 12)
0136 #define NIX_LF_CINTX_INT(a)     (NIX_LFBASE | 0xD20 | (a) << 12)
0137 #define NIX_LF_CINTX_INT_W1S(a)     (NIX_LFBASE | 0xD30 | (a) << 12)
0138 #define NIX_LF_CINTX_ENA_W1S(a)     (NIX_LFBASE | 0xD40 | (a) << 12)
0139 #define NIX_LF_CINTX_ENA_W1C(a)     (NIX_LFBASE | 0xD50 | (a) << 12)
0140
0141 /* NIX AF transmit scheduler registers */
0142 #define NIX_AF_SMQX_CFG(a)      (0x700 | (a) << 16)
0143 #define NIX_AF_TL1X_SCHEDULE(a)     (0xC00 | (a) << 16)
0144 #define NIX_AF_TL1X_CIR(a)      (0xC20 | (a) << 16)
0145 #define NIX_AF_TL1X_TOPOLOGY(a)     (0xC80 | (a) << 16)
0146 #define NIX_AF_TL2X_PARENT(a)       (0xE88 | (a) << 16)
0147 #define NIX_AF_TL2X_SCHEDULE(a)     (0xE00 | (a) << 16)
0148 #define NIX_AF_TL3X_PARENT(a)       (0x1088 | (a) << 16)
0149 #define NIX_AF_TL3X_SCHEDULE(a)     (0x1000 | (a) << 16)
0150 #define NIX_AF_TL4X_PARENT(a)       (0x1288 | (a) << 16)
0151 #define NIX_AF_TL4X_SCHEDULE(a)     (0x1200 | (a) << 16)
0152 #define NIX_AF_TL4X_PIR(a)      (0x1230 | (a) << 16)
0153 #define NIX_AF_MDQX_SCHEDULE(a)     (0x1400 | (a) << 16)
0154 #define NIX_AF_MDQX_PARENT(a)       (0x1480 | (a) << 16)
0155 #define NIX_AF_TL3_TL2X_LINKX_CFG(a, b) (0x1700 | (a) << 16 | (b) << 3)
0156
0157 /* LMT LF registers */
0158 #define LMT_LFBASE          BIT_ULL(RVU_FUNC_BLKADDR_SHIFT)
0159 #define LMT_LF_LMTLINEX(a)      (LMT_LFBASE | 0x000 | (a) << 12)
0160 #define LMT_LF_LMTCANCEL        (LMT_LFBASE | 0x400)
0161
0162 #endif /* OTX2_REG_H */