octeontx2/nic/otx2_dmac_flt.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /* Marvell RVU Ethernet driver
0003  *
0004  * Copyright (C) 2021 Marvell.
0005  *
0006  */
0007
0008 #include "otx2_common.h"
0009
0010 static int otx2_dmacflt_do_add(struct otx2_nic *pf, const u8 *mac,
0011                    u32 *dmac_index)
0012 {
0013     struct cgx_mac_addr_add_req *req;
0014     struct cgx_mac_addr_add_rsp *rsp;
0015     int err;
0016
0017     mutex_lock(&pf->mbox.lock);
0018
0019     req = otx2_mbox_alloc_msg_cgx_mac_addr_add(&pf->mbox);
0020     if (!req) {
0021         mutex_unlock(&pf->mbox.lock);
0022         return -ENOMEM;
0023     }
0024
0025     ether_addr_copy(req->mac_addr, mac);
0026     err = otx2_sync_mbox_msg(&pf->mbox);
0027
0028     if (!err) {
0029         rsp = (struct cgx_mac_addr_add_rsp *)
0030              otx2_mbox_get_rsp(&pf->mbox.mbox, 0, &req->hdr);
0031         *dmac_index = rsp->index;
0032     }
0033
0034     mutex_unlock(&pf->mbox.lock);
0035     return err;
0036 }
0037
0038 static int otx2_dmacflt_add_pfmac(struct otx2_nic *pf, u32 *dmac_index)
0039 {
0040     struct cgx_mac_addr_set_or_get *req;
0041     struct cgx_mac_addr_set_or_get *rsp;
0042     int err;
0043
0044     mutex_lock(&pf->mbox.lock);
0045
0046     req = otx2_mbox_alloc_msg_cgx_mac_addr_set(&pf->mbox);
0047     if (!req) {
0048         mutex_unlock(&pf->mbox.lock);
0049         return -ENOMEM;
0050     }
0051
0052     req->index = *dmac_index;
0053
0054     ether_addr_copy(req->mac_addr, pf->netdev->dev_addr);
0055     err = otx2_sync_mbox_msg(&pf->mbox);
0056
0057     if (err)
0058         goto out;
0059
0060     rsp = (struct cgx_mac_addr_set_or_get *)
0061         otx2_mbox_get_rsp(&pf->mbox.mbox, 0, &req->hdr);
0062
0063     if (IS_ERR_OR_NULL(rsp)) {
0064         err = -EINVAL;
0065         goto out;
0066     }
0067
0068     *dmac_index = rsp->index;
0069 out:
0070     mutex_unlock(&pf->mbox.lock);
0071     return err;
0072 }
0073
0074 int otx2_dmacflt_add(struct otx2_nic *pf, const u8 *mac, u32 bit_pos)
0075 {
0076     u32 *dmacindex;
0077
0078     /* Store dmacindex returned by CGX/RPM driver which will
0079      * be used for macaddr update/remove
0080      */
0081     dmacindex = &pf->flow_cfg->bmap_to_dmacindex[bit_pos];
0082
0083     if (ether_addr_equal(mac, pf->netdev->dev_addr))
0084         return otx2_dmacflt_add_pfmac(pf, dmacindex);
0085     else
0086         return otx2_dmacflt_do_add(pf, mac, dmacindex);
0087 }
0088
0089 static int otx2_dmacflt_do_remove(struct otx2_nic *pfvf, const u8 *mac,
0090                   u32 dmac_index)
0091 {
0092     struct cgx_mac_addr_del_req *req;
0093     int err;
0094
0095     mutex_lock(&pfvf->mbox.lock);
0096     req = otx2_mbox_alloc_msg_cgx_mac_addr_del(&pfvf->mbox);
0097     if (!req) {
0098         mutex_unlock(&pfvf->mbox.lock);
0099         return -ENOMEM;
0100     }
0101
0102     req->index = dmac_index;
0103
0104     err = otx2_sync_mbox_msg(&pfvf->mbox);
0105     mutex_unlock(&pfvf->mbox.lock);
0106
0107     return err;
0108 }
0109
0110 static int otx2_dmacflt_remove_pfmac(struct otx2_nic *pf, u32 dmac_index)
0111 {
0112     struct cgx_mac_addr_reset_req *req;
0113     int err;
0114
0115     mutex_lock(&pf->mbox.lock);
0116     req = otx2_mbox_alloc_msg_cgx_mac_addr_reset(&pf->mbox);
0117     if (!req) {
0118         mutex_unlock(&pf->mbox.lock);
0119         return -ENOMEM;
0120     }
0121     req->index = dmac_index;
0122
0123     err = otx2_sync_mbox_msg(&pf->mbox);
0124
0125     mutex_unlock(&pf->mbox.lock);
0126     return err;
0127 }
0128
0129 int otx2_dmacflt_remove(struct otx2_nic *pf, const u8 *mac,
0130             u32 bit_pos)
0131 {
0132     u32 dmacindex = pf->flow_cfg->bmap_to_dmacindex[bit_pos];
0133
0134     if (ether_addr_equal(mac, pf->netdev->dev_addr))
0135         return otx2_dmacflt_remove_pfmac(pf, dmacindex);
0136     else
0137         return otx2_dmacflt_do_remove(pf, mac, dmacindex);
0138 }
0139
0140 /* CGX/RPM blocks support max unicast entries of 32.
0141  * on typical configuration MAC block associated
0142  * with 4 lmacs, each lmac will have 8 dmac entries
0143  */
0144 int otx2_dmacflt_get_max_cnt(struct otx2_nic *pf)
0145 {
0146     struct cgx_max_dmac_entries_get_rsp *rsp;
0147     struct msg_req *msg;
0148     int err;
0149
0150     mutex_lock(&pf->mbox.lock);
0151     msg = otx2_mbox_alloc_msg_cgx_mac_max_entries_get(&pf->mbox);
0152
0153     if (!msg) {
0154         mutex_unlock(&pf->mbox.lock);
0155         return -ENOMEM;
0156     }
0157
0158     err = otx2_sync_mbox_msg(&pf->mbox);
0159     if (err)
0160         goto out;
0161
0162     rsp = (struct cgx_max_dmac_entries_get_rsp *)
0163              otx2_mbox_get_rsp(&pf->mbox.mbox, 0, &msg->hdr);
0164
0165     if (IS_ERR_OR_NULL(rsp)) {
0166         err = -EINVAL;
0167         goto out;
0168     }
0169
0170     pf->flow_cfg->dmacflt_max_flows = rsp->max_dmac_filters;
0171
0172 out:
0173     mutex_unlock(&pf->mbox.lock);
0174     return err;
0175 }
0176
0177 int otx2_dmacflt_update(struct otx2_nic *pf, u8 *mac, u32 bit_pos)
0178 {
0179     struct cgx_mac_addr_update_req *req;
0180     struct cgx_mac_addr_update_rsp *rsp;
0181     int rc;
0182
0183     mutex_lock(&pf->mbox.lock);
0184
0185     req = otx2_mbox_alloc_msg_cgx_mac_addr_update(&pf->mbox);
0186
0187     if (!req) {
0188         mutex_unlock(&pf->mbox.lock);
0189         return -ENOMEM;
0190     }
0191
0192     ether_addr_copy(req->mac_addr, mac);
0193     req->index = pf->flow_cfg->bmap_to_dmacindex[bit_pos];
0194
0195     /* check the response and change index */
0196
0197     rc = otx2_sync_mbox_msg(&pf->mbox);
0198     if (rc)
0199         goto out;
0200
0201     rsp = (struct cgx_mac_addr_update_rsp *)
0202         otx2_mbox_get_rsp(&pf->mbox.mbox, 0, &req->hdr);
0203
0204     pf->flow_cfg->bmap_to_dmacindex[bit_pos] = rsp->index;
0205
0206 out:
0207     mutex_unlock(&pf->mbox.lock);
0208     return rc;
0209 }