Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 /* Marvell RVU Ethernet driver
0003  *
0004  * Copyright (C) 2020 Marvell.
0005  *
0006  */
0007 
0008 #include <linux/interrupt.h>
0009 #include <linux/pci.h>
0010 #include <net/tso.h>
0011 
0012 #include "otx2_reg.h"
0013 #include "otx2_common.h"
0014 #include "otx2_struct.h"
0015 #include "cn10k.h"
0016 
0017 static void otx2_nix_rq_op_stats(struct queue_stats *stats,
0018                  struct otx2_nic *pfvf, int qidx)
0019 {
0020     u64 incr = (u64)qidx << 32;
0021     u64 *ptr;
0022 
0023     ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_RQ_OP_OCTS);
0024     stats->bytes = otx2_atomic64_add(incr, ptr);
0025 
0026     ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_RQ_OP_PKTS);
0027     stats->pkts = otx2_atomic64_add(incr, ptr);
0028 }
0029 
0030 static void otx2_nix_sq_op_stats(struct queue_stats *stats,
0031                  struct otx2_nic *pfvf, int qidx)
0032 {
0033     u64 incr = (u64)qidx << 32;
0034     u64 *ptr;
0035 
0036     ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_OCTS);
0037     stats->bytes = otx2_atomic64_add(incr, ptr);
0038 
0039     ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_PKTS);
0040     stats->pkts = otx2_atomic64_add(incr, ptr);
0041 }
0042 
0043 void otx2_update_lmac_stats(struct otx2_nic *pfvf)
0044 {
0045     struct msg_req *req;
0046 
0047     if (!netif_running(pfvf->netdev))
0048         return;
0049 
0050     mutex_lock(&pfvf->mbox.lock);
0051     req = otx2_mbox_alloc_msg_cgx_stats(&pfvf->mbox);
0052     if (!req) {
0053         mutex_unlock(&pfvf->mbox.lock);
0054         return;
0055     }
0056 
0057     otx2_sync_mbox_msg(&pfvf->mbox);
0058     mutex_unlock(&pfvf->mbox.lock);
0059 }
0060 
0061 void otx2_update_lmac_fec_stats(struct otx2_nic *pfvf)
0062 {
0063     struct msg_req *req;
0064 
0065     if (!netif_running(pfvf->netdev))
0066         return;
0067     mutex_lock(&pfvf->mbox.lock);
0068     req = otx2_mbox_alloc_msg_cgx_fec_stats(&pfvf->mbox);
0069     if (req)
0070         otx2_sync_mbox_msg(&pfvf->mbox);
0071     mutex_unlock(&pfvf->mbox.lock);
0072 }
0073 
0074 int otx2_update_rq_stats(struct otx2_nic *pfvf, int qidx)
0075 {
0076     struct otx2_rcv_queue *rq = &pfvf->qset.rq[qidx];
0077 
0078     if (!pfvf->qset.rq)
0079         return 0;
0080 
0081     otx2_nix_rq_op_stats(&rq->stats, pfvf, qidx);
0082     return 1;
0083 }
0084 
0085 int otx2_update_sq_stats(struct otx2_nic *pfvf, int qidx)
0086 {
0087     struct otx2_snd_queue *sq = &pfvf->qset.sq[qidx];
0088 
0089     if (!pfvf->qset.sq)
0090         return 0;
0091 
0092     otx2_nix_sq_op_stats(&sq->stats, pfvf, qidx);
0093     return 1;
0094 }
0095 
0096 void otx2_get_dev_stats(struct otx2_nic *pfvf)
0097 {
0098     struct otx2_dev_stats *dev_stats = &pfvf->hw.dev_stats;
0099 
0100     dev_stats->rx_bytes = OTX2_GET_RX_STATS(RX_OCTS);
0101     dev_stats->rx_drops = OTX2_GET_RX_STATS(RX_DROP);
0102     dev_stats->rx_bcast_frames = OTX2_GET_RX_STATS(RX_BCAST);
0103     dev_stats->rx_mcast_frames = OTX2_GET_RX_STATS(RX_MCAST);
0104     dev_stats->rx_ucast_frames = OTX2_GET_RX_STATS(RX_UCAST);
0105     dev_stats->rx_frames = dev_stats->rx_bcast_frames +
0106                    dev_stats->rx_mcast_frames +
0107                    dev_stats->rx_ucast_frames;
0108 
0109     dev_stats->tx_bytes = OTX2_GET_TX_STATS(TX_OCTS);
0110     dev_stats->tx_drops = OTX2_GET_TX_STATS(TX_DROP);
0111     dev_stats->tx_bcast_frames = OTX2_GET_TX_STATS(TX_BCAST);
0112     dev_stats->tx_mcast_frames = OTX2_GET_TX_STATS(TX_MCAST);
0113     dev_stats->tx_ucast_frames = OTX2_GET_TX_STATS(TX_UCAST);
0114     dev_stats->tx_frames = dev_stats->tx_bcast_frames +
0115                    dev_stats->tx_mcast_frames +
0116                    dev_stats->tx_ucast_frames;
0117 }
0118 
0119 void otx2_get_stats64(struct net_device *netdev,
0120               struct rtnl_link_stats64 *stats)
0121 {
0122     struct otx2_nic *pfvf = netdev_priv(netdev);
0123     struct otx2_dev_stats *dev_stats;
0124 
0125     otx2_get_dev_stats(pfvf);
0126 
0127     dev_stats = &pfvf->hw.dev_stats;
0128     stats->rx_bytes = dev_stats->rx_bytes;
0129     stats->rx_packets = dev_stats->rx_frames;
0130     stats->rx_dropped = dev_stats->rx_drops;
0131     stats->multicast = dev_stats->rx_mcast_frames;
0132 
0133     stats->tx_bytes = dev_stats->tx_bytes;
0134     stats->tx_packets = dev_stats->tx_frames;
0135     stats->tx_dropped = dev_stats->tx_drops;
0136 }
0137 EXPORT_SYMBOL(otx2_get_stats64);
0138 
0139 /* Sync MAC address with RVU AF */
0140 static int otx2_hw_set_mac_addr(struct otx2_nic *pfvf, u8 *mac)
0141 {
0142     struct nix_set_mac_addr *req;
0143     int err;
0144 
0145     mutex_lock(&pfvf->mbox.lock);
0146     req = otx2_mbox_alloc_msg_nix_set_mac_addr(&pfvf->mbox);
0147     if (!req) {
0148         mutex_unlock(&pfvf->mbox.lock);
0149         return -ENOMEM;
0150     }
0151 
0152     ether_addr_copy(req->mac_addr, mac);
0153 
0154     err = otx2_sync_mbox_msg(&pfvf->mbox);
0155     mutex_unlock(&pfvf->mbox.lock);
0156     return err;
0157 }
0158 
0159 static int otx2_hw_get_mac_addr(struct otx2_nic *pfvf,
0160                 struct net_device *netdev)
0161 {
0162     struct nix_get_mac_addr_rsp *rsp;
0163     struct mbox_msghdr *msghdr;
0164     struct msg_req *req;
0165     int err;
0166 
0167     mutex_lock(&pfvf->mbox.lock);
0168     req = otx2_mbox_alloc_msg_nix_get_mac_addr(&pfvf->mbox);
0169     if (!req) {
0170         mutex_unlock(&pfvf->mbox.lock);
0171         return -ENOMEM;
0172     }
0173 
0174     err = otx2_sync_mbox_msg(&pfvf->mbox);
0175     if (err) {
0176         mutex_unlock(&pfvf->mbox.lock);
0177         return err;
0178     }
0179 
0180     msghdr = otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr);
0181     if (IS_ERR(msghdr)) {
0182         mutex_unlock(&pfvf->mbox.lock);
0183         return PTR_ERR(msghdr);
0184     }
0185     rsp = (struct nix_get_mac_addr_rsp *)msghdr;
0186     eth_hw_addr_set(netdev, rsp->mac_addr);
0187     mutex_unlock(&pfvf->mbox.lock);
0188 
0189     return 0;
0190 }
0191 
0192 int otx2_set_mac_address(struct net_device *netdev, void *p)
0193 {
0194     struct otx2_nic *pfvf = netdev_priv(netdev);
0195     struct sockaddr *addr = p;
0196 
0197     if (!is_valid_ether_addr(addr->sa_data))
0198         return -EADDRNOTAVAIL;
0199 
0200     if (!otx2_hw_set_mac_addr(pfvf, addr->sa_data)) {
0201         eth_hw_addr_set(netdev, addr->sa_data);
0202         /* update dmac field in vlan offload rule */
0203         if (netif_running(netdev) &&
0204             pfvf->flags & OTX2_FLAG_RX_VLAN_SUPPORT)
0205             otx2_install_rxvlan_offload_flow(pfvf);
0206         /* update dmac address in ntuple and DMAC filter list */
0207         if (pfvf->flags & OTX2_FLAG_DMACFLTR_SUPPORT)
0208             otx2_dmacflt_update_pfmac_flow(pfvf);
0209     } else {
0210         return -EPERM;
0211     }
0212 
0213     return 0;
0214 }
0215 EXPORT_SYMBOL(otx2_set_mac_address);
0216 
0217 int otx2_hw_set_mtu(struct otx2_nic *pfvf, int mtu)
0218 {
0219     struct nix_frs_cfg *req;
0220     u16 maxlen;
0221     int err;
0222 
0223     maxlen = otx2_get_max_mtu(pfvf) + OTX2_ETH_HLEN + OTX2_HW_TIMESTAMP_LEN;
0224 
0225     mutex_lock(&pfvf->mbox.lock);
0226     req = otx2_mbox_alloc_msg_nix_set_hw_frs(&pfvf->mbox);
0227     if (!req) {
0228         mutex_unlock(&pfvf->mbox.lock);
0229         return -ENOMEM;
0230     }
0231 
0232     req->maxlen = pfvf->netdev->mtu + OTX2_ETH_HLEN + OTX2_HW_TIMESTAMP_LEN;
0233 
0234     /* Use max receive length supported by hardware for loopback devices */
0235     if (is_otx2_lbkvf(pfvf->pdev))
0236         req->maxlen = maxlen;
0237 
0238     err = otx2_sync_mbox_msg(&pfvf->mbox);
0239     mutex_unlock(&pfvf->mbox.lock);
0240     return err;
0241 }
0242 
0243 int otx2_config_pause_frm(struct otx2_nic *pfvf)
0244 {
0245     struct cgx_pause_frm_cfg *req;
0246     int err;
0247 
0248     if (is_otx2_lbkvf(pfvf->pdev))
0249         return 0;
0250 
0251     mutex_lock(&pfvf->mbox.lock);
0252     req = otx2_mbox_alloc_msg_cgx_cfg_pause_frm(&pfvf->mbox);
0253     if (!req) {
0254         err = -ENOMEM;
0255         goto unlock;
0256     }
0257 
0258     req->rx_pause = !!(pfvf->flags & OTX2_FLAG_RX_PAUSE_ENABLED);
0259     req->tx_pause = !!(pfvf->flags & OTX2_FLAG_TX_PAUSE_ENABLED);
0260     req->set = 1;
0261 
0262     err = otx2_sync_mbox_msg(&pfvf->mbox);
0263 unlock:
0264     mutex_unlock(&pfvf->mbox.lock);
0265     return err;
0266 }
0267 EXPORT_SYMBOL(otx2_config_pause_frm);
0268 
0269 int otx2_set_flowkey_cfg(struct otx2_nic *pfvf)
0270 {
0271     struct otx2_rss_info *rss = &pfvf->hw.rss_info;
0272     struct nix_rss_flowkey_cfg_rsp *rsp;
0273     struct nix_rss_flowkey_cfg *req;
0274     int err;
0275 
0276     mutex_lock(&pfvf->mbox.lock);
0277     req = otx2_mbox_alloc_msg_nix_rss_flowkey_cfg(&pfvf->mbox);
0278     if (!req) {
0279         mutex_unlock(&pfvf->mbox.lock);
0280         return -ENOMEM;
0281     }
0282     req->mcam_index = -1; /* Default or reserved index */
0283     req->flowkey_cfg = rss->flowkey_cfg;
0284     req->group = DEFAULT_RSS_CONTEXT_GROUP;
0285 
0286     err = otx2_sync_mbox_msg(&pfvf->mbox);
0287     if (err)
0288         goto fail;
0289 
0290     rsp = (struct nix_rss_flowkey_cfg_rsp *)
0291             otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr);
0292     if (IS_ERR(rsp)) {
0293         err = PTR_ERR(rsp);
0294         goto fail;
0295     }
0296 
0297     pfvf->hw.flowkey_alg_idx = rsp->alg_idx;
0298 fail:
0299     mutex_unlock(&pfvf->mbox.lock);
0300     return err;
0301 }
0302 
0303 int otx2_set_rss_table(struct otx2_nic *pfvf, int ctx_id)
0304 {
0305     struct otx2_rss_info *rss = &pfvf->hw.rss_info;
0306     const int index = rss->rss_size * ctx_id;
0307     struct mbox *mbox = &pfvf->mbox;
0308     struct otx2_rss_ctx *rss_ctx;
0309     struct nix_aq_enq_req *aq;
0310     int idx, err;
0311 
0312     mutex_lock(&mbox->lock);
0313     rss_ctx = rss->rss_ctx[ctx_id];
0314     /* Get memory to put this msg */
0315     for (idx = 0; idx < rss->rss_size; idx++) {
0316         aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
0317         if (!aq) {
0318             /* The shared memory buffer can be full.
0319              * Flush it and retry
0320              */
0321             err = otx2_sync_mbox_msg(mbox);
0322             if (err) {
0323                 mutex_unlock(&mbox->lock);
0324                 return err;
0325             }
0326             aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
0327             if (!aq) {
0328                 mutex_unlock(&mbox->lock);
0329                 return -ENOMEM;
0330             }
0331         }
0332 
0333         aq->rss.rq = rss_ctx->ind_tbl[idx];
0334 
0335         /* Fill AQ info */
0336         aq->qidx = index + idx;
0337         aq->ctype = NIX_AQ_CTYPE_RSS;
0338         aq->op = NIX_AQ_INSTOP_INIT;
0339     }
0340     err = otx2_sync_mbox_msg(mbox);
0341     mutex_unlock(&mbox->lock);
0342     return err;
0343 }
0344 
0345 void otx2_set_rss_key(struct otx2_nic *pfvf)
0346 {
0347     struct otx2_rss_info *rss = &pfvf->hw.rss_info;
0348     u64 *key = (u64 *)&rss->key[4];
0349     int idx;
0350 
0351     /* 352bit or 44byte key needs to be configured as below
0352      * NIX_LF_RX_SECRETX0 = key<351:288>
0353      * NIX_LF_RX_SECRETX1 = key<287:224>
0354      * NIX_LF_RX_SECRETX2 = key<223:160>
0355      * NIX_LF_RX_SECRETX3 = key<159:96>
0356      * NIX_LF_RX_SECRETX4 = key<95:32>
0357      * NIX_LF_RX_SECRETX5<63:32> = key<31:0>
0358      */
0359     otx2_write64(pfvf, NIX_LF_RX_SECRETX(5),
0360              (u64)(*((u32 *)&rss->key)) << 32);
0361     idx = sizeof(rss->key) / sizeof(u64);
0362     while (idx > 0) {
0363         idx--;
0364         otx2_write64(pfvf, NIX_LF_RX_SECRETX(idx), *key++);
0365     }
0366 }
0367 
0368 int otx2_rss_init(struct otx2_nic *pfvf)
0369 {
0370     struct otx2_rss_info *rss = &pfvf->hw.rss_info;
0371     struct otx2_rss_ctx *rss_ctx;
0372     int idx, ret = 0;
0373 
0374     rss->rss_size = sizeof(*rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP]);
0375 
0376     /* Init RSS key if it is not setup already */
0377     if (!rss->enable)
0378         netdev_rss_key_fill(rss->key, sizeof(rss->key));
0379     otx2_set_rss_key(pfvf);
0380 
0381     if (!netif_is_rxfh_configured(pfvf->netdev)) {
0382         /* Set RSS group 0 as default indirection table */
0383         rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP] = kzalloc(rss->rss_size,
0384                                   GFP_KERNEL);
0385         if (!rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP])
0386             return -ENOMEM;
0387 
0388         rss_ctx = rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP];
0389         for (idx = 0; idx < rss->rss_size; idx++)
0390             rss_ctx->ind_tbl[idx] =
0391                 ethtool_rxfh_indir_default(idx,
0392                                pfvf->hw.rx_queues);
0393     }
0394     ret = otx2_set_rss_table(pfvf, DEFAULT_RSS_CONTEXT_GROUP);
0395     if (ret)
0396         return ret;
0397 
0398     /* Flowkey or hash config to be used for generating flow tag */
0399     rss->flowkey_cfg = rss->enable ? rss->flowkey_cfg :
0400                NIX_FLOW_KEY_TYPE_IPV4 | NIX_FLOW_KEY_TYPE_IPV6 |
0401                NIX_FLOW_KEY_TYPE_TCP | NIX_FLOW_KEY_TYPE_UDP |
0402                NIX_FLOW_KEY_TYPE_SCTP | NIX_FLOW_KEY_TYPE_VLAN |
0403                NIX_FLOW_KEY_TYPE_IPV4_PROTO;
0404 
0405     ret = otx2_set_flowkey_cfg(pfvf);
0406     if (ret)
0407         return ret;
0408 
0409     rss->enable = true;
0410     return 0;
0411 }
0412 
0413 /* Setup UDP segmentation algorithm in HW */
0414 static void otx2_setup_udp_segmentation(struct nix_lso_format_cfg *lso, bool v4)
0415 {
0416     struct nix_lso_format *field;
0417 
0418     field = (struct nix_lso_format *)&lso->fields[0];
0419     lso->field_mask = GENMASK(18, 0);
0420 
0421     /* IP's Length field */
0422     field->layer = NIX_TXLAYER_OL3;
0423     /* In ipv4, length field is at offset 2 bytes, for ipv6 it's 4 */
0424     field->offset = v4 ? 2 : 4;
0425     field->sizem1 = 1; /* i.e 2 bytes */
0426     field->alg = NIX_LSOALG_ADD_PAYLEN;
0427     field++;
0428 
0429     /* No ID field in IPv6 header */
0430     if (v4) {
0431         /* Increment IPID */
0432         field->layer = NIX_TXLAYER_OL3;
0433         field->offset = 4;
0434         field->sizem1 = 1; /* i.e 2 bytes */
0435         field->alg = NIX_LSOALG_ADD_SEGNUM;
0436         field++;
0437     }
0438 
0439     /* Update length in UDP header */
0440     field->layer = NIX_TXLAYER_OL4;
0441     field->offset = 4;
0442     field->sizem1 = 1;
0443     field->alg = NIX_LSOALG_ADD_PAYLEN;
0444 }
0445 
0446 /* Setup segmentation algorithms in HW and retrieve algorithm index */
0447 void otx2_setup_segmentation(struct otx2_nic *pfvf)
0448 {
0449     struct nix_lso_format_cfg_rsp *rsp;
0450     struct nix_lso_format_cfg *lso;
0451     struct otx2_hw *hw = &pfvf->hw;
0452     int err;
0453 
0454     mutex_lock(&pfvf->mbox.lock);
0455 
0456     /* UDPv4 segmentation */
0457     lso = otx2_mbox_alloc_msg_nix_lso_format_cfg(&pfvf->mbox);
0458     if (!lso)
0459         goto fail;
0460 
0461     /* Setup UDP/IP header fields that HW should update per segment */
0462     otx2_setup_udp_segmentation(lso, true);
0463 
0464     err = otx2_sync_mbox_msg(&pfvf->mbox);
0465     if (err)
0466         goto fail;
0467 
0468     rsp = (struct nix_lso_format_cfg_rsp *)
0469             otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &lso->hdr);
0470     if (IS_ERR(rsp))
0471         goto fail;
0472 
0473     hw->lso_udpv4_idx = rsp->lso_format_idx;
0474 
0475     /* UDPv6 segmentation */
0476     lso = otx2_mbox_alloc_msg_nix_lso_format_cfg(&pfvf->mbox);
0477     if (!lso)
0478         goto fail;
0479 
0480     /* Setup UDP/IP header fields that HW should update per segment */
0481     otx2_setup_udp_segmentation(lso, false);
0482 
0483     err = otx2_sync_mbox_msg(&pfvf->mbox);
0484     if (err)
0485         goto fail;
0486 
0487     rsp = (struct nix_lso_format_cfg_rsp *)
0488             otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &lso->hdr);
0489     if (IS_ERR(rsp))
0490         goto fail;
0491 
0492     hw->lso_udpv6_idx = rsp->lso_format_idx;
0493     mutex_unlock(&pfvf->mbox.lock);
0494     return;
0495 fail:
0496     mutex_unlock(&pfvf->mbox.lock);
0497     netdev_info(pfvf->netdev,
0498             "Failed to get LSO index for UDP GSO offload, disabling\n");
0499     pfvf->netdev->hw_features &= ~NETIF_F_GSO_UDP_L4;
0500 }
0501 
0502 void otx2_config_irq_coalescing(struct otx2_nic *pfvf, int qidx)
0503 {
0504     /* Configure CQE interrupt coalescing parameters
0505      *
0506      * HW triggers an irq when ECOUNT > cq_ecount_wait, hence
0507      * set 1 less than cq_ecount_wait. And cq_time_wait is in
0508      * usecs, convert that to 100ns count.
0509      */
0510     otx2_write64(pfvf, NIX_LF_CINTX_WAIT(qidx),
0511              ((u64)(pfvf->hw.cq_time_wait * 10) << 48) |
0512              ((u64)pfvf->hw.cq_qcount_wait << 32) |
0513              (pfvf->hw.cq_ecount_wait - 1));
0514 }
0515 
0516 int __otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool,
0517               dma_addr_t *dma)
0518 {
0519     u8 *buf;
0520 
0521     buf = napi_alloc_frag_align(pool->rbsize, OTX2_ALIGN);
0522     if (unlikely(!buf))
0523         return -ENOMEM;
0524 
0525     *dma = dma_map_single_attrs(pfvf->dev, buf, pool->rbsize,
0526                     DMA_FROM_DEVICE, DMA_ATTR_SKIP_CPU_SYNC);
0527     if (unlikely(dma_mapping_error(pfvf->dev, *dma))) {
0528         page_frag_free(buf);
0529         return -ENOMEM;
0530     }
0531 
0532     return 0;
0533 }
0534 
0535 static int otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool,
0536                dma_addr_t *dma)
0537 {
0538     int ret;
0539 
0540     local_bh_disable();
0541     ret = __otx2_alloc_rbuf(pfvf, pool, dma);
0542     local_bh_enable();
0543     return ret;
0544 }
0545 
0546 int otx2_alloc_buffer(struct otx2_nic *pfvf, struct otx2_cq_queue *cq,
0547               dma_addr_t *dma)
0548 {
0549     if (unlikely(__otx2_alloc_rbuf(pfvf, cq->rbpool, dma))) {
0550         struct refill_work *work;
0551         struct delayed_work *dwork;
0552 
0553         work = &pfvf->refill_wrk[cq->cq_idx];
0554         dwork = &work->pool_refill_work;
0555         /* Schedule a task if no other task is running */
0556         if (!cq->refill_task_sched) {
0557             cq->refill_task_sched = true;
0558             schedule_delayed_work(dwork,
0559                           msecs_to_jiffies(100));
0560         }
0561         return -ENOMEM;
0562     }
0563     return 0;
0564 }
0565 
0566 void otx2_tx_timeout(struct net_device *netdev, unsigned int txq)
0567 {
0568     struct otx2_nic *pfvf = netdev_priv(netdev);
0569 
0570     schedule_work(&pfvf->reset_task);
0571 }
0572 EXPORT_SYMBOL(otx2_tx_timeout);
0573 
0574 void otx2_get_mac_from_af(struct net_device *netdev)
0575 {
0576     struct otx2_nic *pfvf = netdev_priv(netdev);
0577     int err;
0578 
0579     err = otx2_hw_get_mac_addr(pfvf, netdev);
0580     if (err)
0581         dev_warn(pfvf->dev, "Failed to read mac from hardware\n");
0582 
0583     /* If AF doesn't provide a valid MAC, generate a random one */
0584     if (!is_valid_ether_addr(netdev->dev_addr))
0585         eth_hw_addr_random(netdev);
0586 }
0587 EXPORT_SYMBOL(otx2_get_mac_from_af);
0588 
0589 int otx2_txschq_config(struct otx2_nic *pfvf, int lvl)
0590 {
0591     struct otx2_hw *hw = &pfvf->hw;
0592     struct nix_txschq_config *req;
0593     u64 schq, parent;
0594     u64 dwrr_val;
0595 
0596     dwrr_val = mtu_to_dwrr_weight(pfvf, pfvf->tx_max_pktlen);
0597 
0598     req = otx2_mbox_alloc_msg_nix_txschq_cfg(&pfvf->mbox);
0599     if (!req)
0600         return -ENOMEM;
0601 
0602     req->lvl = lvl;
0603     req->num_regs = 1;
0604 
0605     schq = hw->txschq_list[lvl][0];
0606     /* Set topology e.t.c configuration */
0607     if (lvl == NIX_TXSCH_LVL_SMQ) {
0608         req->reg[0] = NIX_AF_SMQX_CFG(schq);
0609         req->regval[0] = ((u64)pfvf->tx_max_pktlen << 8) | OTX2_MIN_MTU;
0610         req->regval[0] |= (0x20ULL << 51) | (0x80ULL << 39) |
0611                   (0x2ULL << 36);
0612         req->num_regs++;
0613         /* MDQ config */
0614         parent =  hw->txschq_list[NIX_TXSCH_LVL_TL4][0];
0615         req->reg[1] = NIX_AF_MDQX_PARENT(schq);
0616         req->regval[1] = parent << 16;
0617         req->num_regs++;
0618         /* Set DWRR quantum */
0619         req->reg[2] = NIX_AF_MDQX_SCHEDULE(schq);
0620         req->regval[2] =  dwrr_val;
0621     } else if (lvl == NIX_TXSCH_LVL_TL4) {
0622         parent =  hw->txschq_list[NIX_TXSCH_LVL_TL3][0];
0623         req->reg[0] = NIX_AF_TL4X_PARENT(schq);
0624         req->regval[0] = parent << 16;
0625         req->num_regs++;
0626         req->reg[1] = NIX_AF_TL4X_SCHEDULE(schq);
0627         req->regval[1] = dwrr_val;
0628     } else if (lvl == NIX_TXSCH_LVL_TL3) {
0629         parent = hw->txschq_list[NIX_TXSCH_LVL_TL2][0];
0630         req->reg[0] = NIX_AF_TL3X_PARENT(schq);
0631         req->regval[0] = parent << 16;
0632         req->num_regs++;
0633         req->reg[1] = NIX_AF_TL3X_SCHEDULE(schq);
0634         req->regval[1] = dwrr_val;
0635         if (lvl == hw->txschq_link_cfg_lvl) {
0636             req->num_regs++;
0637             req->reg[2] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, hw->tx_link);
0638             /* Enable this queue and backpressure */
0639             req->regval[2] = BIT_ULL(13) | BIT_ULL(12);
0640         }
0641     } else if (lvl == NIX_TXSCH_LVL_TL2) {
0642         parent =  hw->txschq_list[NIX_TXSCH_LVL_TL1][0];
0643         req->reg[0] = NIX_AF_TL2X_PARENT(schq);
0644         req->regval[0] = parent << 16;
0645 
0646         req->num_regs++;
0647         req->reg[1] = NIX_AF_TL2X_SCHEDULE(schq);
0648         req->regval[1] = TXSCH_TL1_DFLT_RR_PRIO << 24 | dwrr_val;
0649 
0650         if (lvl == hw->txschq_link_cfg_lvl) {
0651             req->num_regs++;
0652             req->reg[2] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, hw->tx_link);
0653             /* Enable this queue and backpressure */
0654             req->regval[2] = BIT_ULL(13) | BIT_ULL(12);
0655         }
0656     } else if (lvl == NIX_TXSCH_LVL_TL1) {
0657         /* Default config for TL1.
0658          * For VF this is always ignored.
0659          */
0660 
0661         /* On CN10K, if RR_WEIGHT is greater than 16384, HW will
0662          * clip it to 16384, so configuring a 24bit max value
0663          * will work on both OTx2 and CN10K.
0664          */
0665         req->reg[0] = NIX_AF_TL1X_SCHEDULE(schq);
0666         req->regval[0] = TXSCH_TL1_DFLT_RR_QTM;
0667 
0668         req->num_regs++;
0669         req->reg[1] = NIX_AF_TL1X_TOPOLOGY(schq);
0670         req->regval[1] = (TXSCH_TL1_DFLT_RR_PRIO << 1);
0671 
0672         req->num_regs++;
0673         req->reg[2] = NIX_AF_TL1X_CIR(schq);
0674         req->regval[2] = 0;
0675     }
0676 
0677     return otx2_sync_mbox_msg(&pfvf->mbox);
0678 }
0679 
0680 int otx2_txsch_alloc(struct otx2_nic *pfvf)
0681 {
0682     struct nix_txsch_alloc_req *req;
0683     int lvl;
0684 
0685     /* Get memory to put this msg */
0686     req = otx2_mbox_alloc_msg_nix_txsch_alloc(&pfvf->mbox);
0687     if (!req)
0688         return -ENOMEM;
0689 
0690     /* Request one schq per level */
0691     for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++)
0692         req->schq[lvl] = 1;
0693 
0694     return otx2_sync_mbox_msg(&pfvf->mbox);
0695 }
0696 
0697 int otx2_txschq_stop(struct otx2_nic *pfvf)
0698 {
0699     struct nix_txsch_free_req *free_req;
0700     int lvl, schq, err;
0701 
0702     mutex_lock(&pfvf->mbox.lock);
0703     /* Free the transmit schedulers */
0704     free_req = otx2_mbox_alloc_msg_nix_txsch_free(&pfvf->mbox);
0705     if (!free_req) {
0706         mutex_unlock(&pfvf->mbox.lock);
0707         return -ENOMEM;
0708     }
0709 
0710     free_req->flags = TXSCHQ_FREE_ALL;
0711     err = otx2_sync_mbox_msg(&pfvf->mbox);
0712     mutex_unlock(&pfvf->mbox.lock);
0713 
0714     /* Clear the txschq list */
0715     for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) {
0716         for (schq = 0; schq < MAX_TXSCHQ_PER_FUNC; schq++)
0717             pfvf->hw.txschq_list[lvl][schq] = 0;
0718     }
0719     return err;
0720 }
0721 
0722 void otx2_sqb_flush(struct otx2_nic *pfvf)
0723 {
0724     int qidx, sqe_tail, sqe_head;
0725     u64 incr, *ptr, val;
0726     int timeout = 1000;
0727 
0728     ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_STATUS);
0729     for (qidx = 0; qidx < pfvf->hw.tot_tx_queues; qidx++) {
0730         incr = (u64)qidx << 32;
0731         while (timeout) {
0732             val = otx2_atomic64_add(incr, ptr);
0733             sqe_head = (val >> 20) & 0x3F;
0734             sqe_tail = (val >> 28) & 0x3F;
0735             if (sqe_head == sqe_tail)
0736                 break;
0737             usleep_range(1, 3);
0738             timeout--;
0739         }
0740     }
0741 }
0742 
0743 /* RED and drop levels of CQ on packet reception.
0744  * For CQ level is measure of emptiness ( 0x0 = full, 255 = empty).
0745  */
0746 #define RQ_PASS_LVL_CQ(skid, qsize) ((((skid) + 16) * 256) / (qsize))
0747 #define RQ_DROP_LVL_CQ(skid, qsize) (((skid) * 256) / (qsize))
0748 
0749 /* RED and drop levels of AURA for packet reception.
0750  * For AURA level is measure of fullness (0x0 = empty, 255 = full).
0751  * Eg: For RQ length 1K, for pass/drop level 204/230.
0752  * RED accepts pkts if free pointers > 102 & <= 205.
0753  * Drops pkts if free pointers < 102.
0754  */
0755 #define RQ_BP_LVL_AURA   (255 - ((85 * 256) / 100)) /* BP when 85% is full */
0756 #define RQ_PASS_LVL_AURA (255 - ((95 * 256) / 100)) /* RED when 95% is full */
0757 #define RQ_DROP_LVL_AURA (255 - ((99 * 256) / 100)) /* Drop when 99% is full */
0758 
0759 static int otx2_rq_init(struct otx2_nic *pfvf, u16 qidx, u16 lpb_aura)
0760 {
0761     struct otx2_qset *qset = &pfvf->qset;
0762     struct nix_aq_enq_req *aq;
0763 
0764     /* Get memory to put this msg */
0765     aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox);
0766     if (!aq)
0767         return -ENOMEM;
0768 
0769     aq->rq.cq = qidx;
0770     aq->rq.ena = 1;
0771     aq->rq.pb_caching = 1;
0772     aq->rq.lpb_aura = lpb_aura; /* Use large packet buffer aura */
0773     aq->rq.lpb_sizem1 = (DMA_BUFFER_LEN(pfvf->rbsize) / 8) - 1;
0774     aq->rq.xqe_imm_size = 0; /* Copying of packet to CQE not needed */
0775     aq->rq.flow_tagw = 32; /* Copy full 32bit flow_tag to CQE header */
0776     aq->rq.qint_idx = 0;
0777     aq->rq.lpb_drop_ena = 1; /* Enable RED dropping for AURA */
0778     aq->rq.xqe_drop_ena = 1; /* Enable RED dropping for CQ/SSO */
0779     aq->rq.xqe_pass = RQ_PASS_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt);
0780     aq->rq.xqe_drop = RQ_DROP_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt);
0781     aq->rq.lpb_aura_pass = RQ_PASS_LVL_AURA;
0782     aq->rq.lpb_aura_drop = RQ_DROP_LVL_AURA;
0783 
0784     /* Fill AQ info */
0785     aq->qidx = qidx;
0786     aq->ctype = NIX_AQ_CTYPE_RQ;
0787     aq->op = NIX_AQ_INSTOP_INIT;
0788 
0789     return otx2_sync_mbox_msg(&pfvf->mbox);
0790 }
0791 
0792 int otx2_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura)
0793 {
0794     struct otx2_nic *pfvf = dev;
0795     struct otx2_snd_queue *sq;
0796     struct nix_aq_enq_req *aq;
0797 
0798     sq = &pfvf->qset.sq[qidx];
0799     sq->lmt_addr = (__force u64 *)(pfvf->reg_base + LMT_LF_LMTLINEX(qidx));
0800     /* Get memory to put this msg */
0801     aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox);
0802     if (!aq)
0803         return -ENOMEM;
0804 
0805     aq->sq.cq = pfvf->hw.rx_queues + qidx;
0806     aq->sq.max_sqe_size = NIX_MAXSQESZ_W16; /* 128 byte */
0807     aq->sq.cq_ena = 1;
0808     aq->sq.ena = 1;
0809     /* Only one SMQ is allocated, map all SQ's to that SMQ  */
0810     aq->sq.smq = pfvf->hw.txschq_list[NIX_TXSCH_LVL_SMQ][0];
0811     aq->sq.smq_rr_quantum = mtu_to_dwrr_weight(pfvf, pfvf->tx_max_pktlen);
0812     aq->sq.default_chan = pfvf->hw.tx_chan_base;
0813     aq->sq.sqe_stype = NIX_STYPE_STF; /* Cache SQB */
0814     aq->sq.sqb_aura = sqb_aura;
0815     aq->sq.sq_int_ena = NIX_SQINT_BITS;
0816     aq->sq.qint_idx = 0;
0817     /* Due pipelining impact minimum 2000 unused SQ CQE's
0818      * need to maintain to avoid CQ overflow.
0819      */
0820     aq->sq.cq_limit = ((SEND_CQ_SKID * 256) / (pfvf->qset.sqe_cnt));
0821 
0822     /* Fill AQ info */
0823     aq->qidx = qidx;
0824     aq->ctype = NIX_AQ_CTYPE_SQ;
0825     aq->op = NIX_AQ_INSTOP_INIT;
0826 
0827     return otx2_sync_mbox_msg(&pfvf->mbox);
0828 }
0829 
0830 static int otx2_sq_init(struct otx2_nic *pfvf, u16 qidx, u16 sqb_aura)
0831 {
0832     struct otx2_qset *qset = &pfvf->qset;
0833     struct otx2_snd_queue *sq;
0834     struct otx2_pool *pool;
0835     int err;
0836 
0837     pool = &pfvf->qset.pool[sqb_aura];
0838     sq = &qset->sq[qidx];
0839     sq->sqe_size = NIX_SQESZ_W16 ? 64 : 128;
0840     sq->sqe_cnt = qset->sqe_cnt;
0841 
0842     err = qmem_alloc(pfvf->dev, &sq->sqe, 1, sq->sqe_size);
0843     if (err)
0844         return err;
0845 
0846     if (qidx < pfvf->hw.tx_queues) {
0847         err = qmem_alloc(pfvf->dev, &sq->tso_hdrs, qset->sqe_cnt,
0848                  TSO_HEADER_SIZE);
0849         if (err)
0850             return err;
0851     }
0852 
0853     sq->sqe_base = sq->sqe->base;
0854     sq->sg = kcalloc(qset->sqe_cnt, sizeof(struct sg_list), GFP_KERNEL);
0855     if (!sq->sg)
0856         return -ENOMEM;
0857 
0858     if (pfvf->ptp && qidx < pfvf->hw.tx_queues) {
0859         err = qmem_alloc(pfvf->dev, &sq->timestamps, qset->sqe_cnt,
0860                  sizeof(*sq->timestamps));
0861         if (err)
0862             return err;
0863     }
0864 
0865     sq->head = 0;
0866     sq->sqe_per_sqb = (pfvf->hw.sqb_size / sq->sqe_size) - 1;
0867     sq->num_sqbs = (qset->sqe_cnt + sq->sqe_per_sqb) / sq->sqe_per_sqb;
0868     /* Set SQE threshold to 10% of total SQEs */
0869     sq->sqe_thresh = ((sq->num_sqbs * sq->sqe_per_sqb) * 10) / 100;
0870     sq->aura_id = sqb_aura;
0871     sq->aura_fc_addr = pool->fc_addr->base;
0872     sq->io_addr = (__force u64)otx2_get_regaddr(pfvf, NIX_LF_OP_SENDX(0));
0873 
0874     sq->stats.bytes = 0;
0875     sq->stats.pkts = 0;
0876 
0877     return pfvf->hw_ops->sq_aq_init(pfvf, qidx, sqb_aura);
0878 
0879 }
0880 
0881 static int otx2_cq_init(struct otx2_nic *pfvf, u16 qidx)
0882 {
0883     struct otx2_qset *qset = &pfvf->qset;
0884     int err, pool_id, non_xdp_queues;
0885     struct nix_aq_enq_req *aq;
0886     struct otx2_cq_queue *cq;
0887 
0888     cq = &qset->cq[qidx];
0889     cq->cq_idx = qidx;
0890     non_xdp_queues = pfvf->hw.rx_queues + pfvf->hw.tx_queues;
0891     if (qidx < pfvf->hw.rx_queues) {
0892         cq->cq_type = CQ_RX;
0893         cq->cint_idx = qidx;
0894         cq->cqe_cnt = qset->rqe_cnt;
0895         if (pfvf->xdp_prog)
0896             xdp_rxq_info_reg(&cq->xdp_rxq, pfvf->netdev, qidx, 0);
0897     } else if (qidx < non_xdp_queues) {
0898         cq->cq_type = CQ_TX;
0899         cq->cint_idx = qidx - pfvf->hw.rx_queues;
0900         cq->cqe_cnt = qset->sqe_cnt;
0901     } else {
0902         cq->cq_type = CQ_XDP;
0903         cq->cint_idx = qidx - non_xdp_queues;
0904         cq->cqe_cnt = qset->sqe_cnt;
0905     }
0906     cq->cqe_size = pfvf->qset.xqe_size;
0907 
0908     /* Allocate memory for CQEs */
0909     err = qmem_alloc(pfvf->dev, &cq->cqe, cq->cqe_cnt, cq->cqe_size);
0910     if (err)
0911         return err;
0912 
0913     /* Save CQE CPU base for faster reference */
0914     cq->cqe_base = cq->cqe->base;
0915     /* In case where all RQs auras point to single pool,
0916      * all CQs receive buffer pool also point to same pool.
0917      */
0918     pool_id = ((cq->cq_type == CQ_RX) &&
0919            (pfvf->hw.rqpool_cnt != pfvf->hw.rx_queues)) ? 0 : qidx;
0920     cq->rbpool = &qset->pool[pool_id];
0921     cq->refill_task_sched = false;
0922 
0923     /* Get memory to put this msg */
0924     aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox);
0925     if (!aq)
0926         return -ENOMEM;
0927 
0928     aq->cq.ena = 1;
0929     aq->cq.qsize = Q_SIZE(cq->cqe_cnt, 4);
0930     aq->cq.caching = 1;
0931     aq->cq.base = cq->cqe->iova;
0932     aq->cq.cint_idx = cq->cint_idx;
0933     aq->cq.cq_err_int_ena = NIX_CQERRINT_BITS;
0934     aq->cq.qint_idx = 0;
0935     aq->cq.avg_level = 255;
0936 
0937     if (qidx < pfvf->hw.rx_queues) {
0938         aq->cq.drop = RQ_DROP_LVL_CQ(pfvf->hw.rq_skid, cq->cqe_cnt);
0939         aq->cq.drop_ena = 1;
0940 
0941         if (!is_otx2_lbkvf(pfvf->pdev)) {
0942             /* Enable receive CQ backpressure */
0943             aq->cq.bp_ena = 1;
0944 #ifdef CONFIG_DCB
0945             aq->cq.bpid = pfvf->bpid[pfvf->queue_to_pfc_map[qidx]];
0946 #else
0947             aq->cq.bpid = pfvf->bpid[0];
0948 #endif
0949 
0950             /* Set backpressure level is same as cq pass level */
0951             aq->cq.bp = RQ_PASS_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt);
0952         }
0953     }
0954 
0955     /* Fill AQ info */
0956     aq->qidx = qidx;
0957     aq->ctype = NIX_AQ_CTYPE_CQ;
0958     aq->op = NIX_AQ_INSTOP_INIT;
0959 
0960     return otx2_sync_mbox_msg(&pfvf->mbox);
0961 }
0962 
0963 static void otx2_pool_refill_task(struct work_struct *work)
0964 {
0965     struct otx2_cq_queue *cq;
0966     struct otx2_pool *rbpool;
0967     struct refill_work *wrk;
0968     int qidx, free_ptrs = 0;
0969     struct otx2_nic *pfvf;
0970     dma_addr_t bufptr;
0971 
0972     wrk = container_of(work, struct refill_work, pool_refill_work.work);
0973     pfvf = wrk->pf;
0974     qidx = wrk - pfvf->refill_wrk;
0975     cq = &pfvf->qset.cq[qidx];
0976     rbpool = cq->rbpool;
0977     free_ptrs = cq->pool_ptrs;
0978 
0979     while (cq->pool_ptrs) {
0980         if (otx2_alloc_rbuf(pfvf, rbpool, &bufptr)) {
0981             /* Schedule a WQ if we fails to free atleast half of the
0982              * pointers else enable napi for this RQ.
0983              */
0984             if (!((free_ptrs - cq->pool_ptrs) > free_ptrs / 2)) {
0985                 struct delayed_work *dwork;
0986 
0987                 dwork = &wrk->pool_refill_work;
0988                 schedule_delayed_work(dwork,
0989                               msecs_to_jiffies(100));
0990             } else {
0991                 cq->refill_task_sched = false;
0992             }
0993             return;
0994         }
0995         pfvf->hw_ops->aura_freeptr(pfvf, qidx, bufptr + OTX2_HEAD_ROOM);
0996         cq->pool_ptrs--;
0997     }
0998     cq->refill_task_sched = false;
0999 }
1000 
1001 int otx2_config_nix_queues(struct otx2_nic *pfvf)
1002 {
1003     int qidx, err;
1004 
1005     /* Initialize RX queues */
1006     for (qidx = 0; qidx < pfvf->hw.rx_queues; qidx++) {
1007         u16 lpb_aura = otx2_get_pool_idx(pfvf, AURA_NIX_RQ, qidx);
1008 
1009         err = otx2_rq_init(pfvf, qidx, lpb_aura);
1010         if (err)
1011             return err;
1012     }
1013 
1014     /* Initialize TX queues */
1015     for (qidx = 0; qidx < pfvf->hw.tot_tx_queues; qidx++) {
1016         u16 sqb_aura = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx);
1017 
1018         err = otx2_sq_init(pfvf, qidx, sqb_aura);
1019         if (err)
1020             return err;
1021     }
1022 
1023     /* Initialize completion queues */
1024     for (qidx = 0; qidx < pfvf->qset.cq_cnt; qidx++) {
1025         err = otx2_cq_init(pfvf, qidx);
1026         if (err)
1027             return err;
1028     }
1029 
1030     pfvf->cq_op_addr = (__force u64 *)otx2_get_regaddr(pfvf,
1031                                NIX_LF_CQ_OP_STATUS);
1032 
1033     /* Initialize work queue for receive buffer refill */
1034     pfvf->refill_wrk = devm_kcalloc(pfvf->dev, pfvf->qset.cq_cnt,
1035                     sizeof(struct refill_work), GFP_KERNEL);
1036     if (!pfvf->refill_wrk)
1037         return -ENOMEM;
1038 
1039     for (qidx = 0; qidx < pfvf->qset.cq_cnt; qidx++) {
1040         pfvf->refill_wrk[qidx].pf = pfvf;
1041         INIT_DELAYED_WORK(&pfvf->refill_wrk[qidx].pool_refill_work,
1042                   otx2_pool_refill_task);
1043     }
1044     return 0;
1045 }
1046 
1047 int otx2_config_nix(struct otx2_nic *pfvf)
1048 {
1049     struct nix_lf_alloc_req  *nixlf;
1050     struct nix_lf_alloc_rsp *rsp;
1051     int err;
1052 
1053     pfvf->qset.xqe_size = pfvf->hw.xqe_size;
1054 
1055     /* Get memory to put this msg */
1056     nixlf = otx2_mbox_alloc_msg_nix_lf_alloc(&pfvf->mbox);
1057     if (!nixlf)
1058         return -ENOMEM;
1059 
1060     /* Set RQ/SQ/CQ counts */
1061     nixlf->rq_cnt = pfvf->hw.rx_queues;
1062     nixlf->sq_cnt = pfvf->hw.tot_tx_queues;
1063     nixlf->cq_cnt = pfvf->qset.cq_cnt;
1064     nixlf->rss_sz = MAX_RSS_INDIR_TBL_SIZE;
1065     nixlf->rss_grps = MAX_RSS_GROUPS;
1066     nixlf->xqe_sz = pfvf->hw.xqe_size == 128 ? NIX_XQESZ_W16 : NIX_XQESZ_W64;
1067     /* We don't know absolute NPA LF idx attached.
1068      * AF will replace 'RVU_DEFAULT_PF_FUNC' with
1069      * NPA LF attached to this RVU PF/VF.
1070      */
1071     nixlf->npa_func = RVU_DEFAULT_PF_FUNC;
1072     /* Disable alignment pad, enable L2 length check,
1073      * enable L4 TCP/UDP checksum verification.
1074      */
1075     nixlf->rx_cfg = BIT_ULL(33) | BIT_ULL(35) | BIT_ULL(37);
1076 
1077     err = otx2_sync_mbox_msg(&pfvf->mbox);
1078     if (err)
1079         return err;
1080 
1081     rsp = (struct nix_lf_alloc_rsp *)otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0,
1082                                &nixlf->hdr);
1083     if (IS_ERR(rsp))
1084         return PTR_ERR(rsp);
1085 
1086     if (rsp->qints < 1)
1087         return -ENXIO;
1088 
1089     return rsp->hdr.rc;
1090 }
1091 
1092 void otx2_sq_free_sqbs(struct otx2_nic *pfvf)
1093 {
1094     struct otx2_qset *qset = &pfvf->qset;
1095     struct otx2_hw *hw = &pfvf->hw;
1096     struct otx2_snd_queue *sq;
1097     int sqb, qidx;
1098     u64 iova, pa;
1099 
1100     for (qidx = 0; qidx < hw->tot_tx_queues; qidx++) {
1101         sq = &qset->sq[qidx];
1102         if (!sq->sqb_ptrs)
1103             continue;
1104         for (sqb = 0; sqb < sq->sqb_count; sqb++) {
1105             if (!sq->sqb_ptrs[sqb])
1106                 continue;
1107             iova = sq->sqb_ptrs[sqb];
1108             pa = otx2_iova_to_phys(pfvf->iommu_domain, iova);
1109             dma_unmap_page_attrs(pfvf->dev, iova, hw->sqb_size,
1110                          DMA_FROM_DEVICE,
1111                          DMA_ATTR_SKIP_CPU_SYNC);
1112             put_page(virt_to_page(phys_to_virt(pa)));
1113         }
1114         sq->sqb_count = 0;
1115     }
1116 }
1117 
1118 void otx2_free_aura_ptr(struct otx2_nic *pfvf, int type)
1119 {
1120     int pool_id, pool_start = 0, pool_end = 0, size = 0;
1121     u64 iova, pa;
1122 
1123     if (type == AURA_NIX_SQ) {
1124         pool_start = otx2_get_pool_idx(pfvf, type, 0);
1125         pool_end =  pool_start + pfvf->hw.sqpool_cnt;
1126         size = pfvf->hw.sqb_size;
1127     }
1128     if (type == AURA_NIX_RQ) {
1129         pool_start = otx2_get_pool_idx(pfvf, type, 0);
1130         pool_end = pfvf->hw.rqpool_cnt;
1131         size = pfvf->rbsize;
1132     }
1133 
1134     /* Free SQB and RQB pointers from the aura pool */
1135     for (pool_id = pool_start; pool_id < pool_end; pool_id++) {
1136         iova = otx2_aura_allocptr(pfvf, pool_id);
1137         while (iova) {
1138             if (type == AURA_NIX_RQ)
1139                 iova -= OTX2_HEAD_ROOM;
1140 
1141             pa = otx2_iova_to_phys(pfvf->iommu_domain, iova);
1142             dma_unmap_page_attrs(pfvf->dev, iova, size,
1143                          DMA_FROM_DEVICE,
1144                          DMA_ATTR_SKIP_CPU_SYNC);
1145             put_page(virt_to_page(phys_to_virt(pa)));
1146             iova = otx2_aura_allocptr(pfvf, pool_id);
1147         }
1148     }
1149 }
1150 
1151 void otx2_aura_pool_free(struct otx2_nic *pfvf)
1152 {
1153     struct otx2_pool *pool;
1154     int pool_id;
1155 
1156     if (!pfvf->qset.pool)
1157         return;
1158 
1159     for (pool_id = 0; pool_id < pfvf->hw.pool_cnt; pool_id++) {
1160         pool = &pfvf->qset.pool[pool_id];
1161         qmem_free(pfvf->dev, pool->stack);
1162         qmem_free(pfvf->dev, pool->fc_addr);
1163     }
1164     devm_kfree(pfvf->dev, pfvf->qset.pool);
1165     pfvf->qset.pool = NULL;
1166 }
1167 
1168 static int otx2_aura_init(struct otx2_nic *pfvf, int aura_id,
1169               int pool_id, int numptrs)
1170 {
1171     struct npa_aq_enq_req *aq;
1172     struct otx2_pool *pool;
1173     int err;
1174 
1175     pool = &pfvf->qset.pool[pool_id];
1176 
1177     /* Allocate memory for HW to update Aura count.
1178      * Alloc one cache line, so that it fits all FC_STYPE modes.
1179      */
1180     if (!pool->fc_addr) {
1181         err = qmem_alloc(pfvf->dev, &pool->fc_addr, 1, OTX2_ALIGN);
1182         if (err)
1183             return err;
1184     }
1185 
1186     /* Initialize this aura's context via AF */
1187     aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox);
1188     if (!aq) {
1189         /* Shared mbox memory buffer is full, flush it and retry */
1190         err = otx2_sync_mbox_msg(&pfvf->mbox);
1191         if (err)
1192             return err;
1193         aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox);
1194         if (!aq)
1195             return -ENOMEM;
1196     }
1197 
1198     aq->aura_id = aura_id;
1199     /* Will be filled by AF with correct pool context address */
1200     aq->aura.pool_addr = pool_id;
1201     aq->aura.pool_caching = 1;
1202     aq->aura.shift = ilog2(numptrs) - 8;
1203     aq->aura.count = numptrs;
1204     aq->aura.limit = numptrs;
1205     aq->aura.avg_level = 255;
1206     aq->aura.ena = 1;
1207     aq->aura.fc_ena = 1;
1208     aq->aura.fc_addr = pool->fc_addr->iova;
1209     aq->aura.fc_hyst_bits = 0; /* Store count on all updates */
1210 
1211     /* Enable backpressure for RQ aura */
1212     if (aura_id < pfvf->hw.rqpool_cnt && !is_otx2_lbkvf(pfvf->pdev)) {
1213         aq->aura.bp_ena = 0;
1214         /* If NIX1 LF is attached then specify NIX1_RX.
1215          *
1216          * Below NPA_AURA_S[BP_ENA] is set according to the
1217          * NPA_BPINTF_E enumeration given as:
1218          * 0x0 + a*0x1 where 'a' is 0 for NIX0_RX and 1 for NIX1_RX so
1219          * NIX0_RX is 0x0 + 0*0x1 = 0
1220          * NIX1_RX is 0x0 + 1*0x1 = 1
1221          * But in HRM it is given that
1222          * "NPA_AURA_S[BP_ENA](w1[33:32]) - Enable aura backpressure to
1223          * NIX-RX based on [BP] level. One bit per NIX-RX; index
1224          * enumerated by NPA_BPINTF_E."
1225          */
1226         if (pfvf->nix_blkaddr == BLKADDR_NIX1)
1227             aq->aura.bp_ena = 1;
1228 #ifdef CONFIG_DCB
1229         aq->aura.nix0_bpid = pfvf->bpid[pfvf->queue_to_pfc_map[aura_id]];
1230 #else
1231         aq->aura.nix0_bpid = pfvf->bpid[0];
1232 #endif
1233 
1234         /* Set backpressure level for RQ's Aura */
1235         aq->aura.bp = RQ_BP_LVL_AURA;
1236     }
1237 
1238     /* Fill AQ info */
1239     aq->ctype = NPA_AQ_CTYPE_AURA;
1240     aq->op = NPA_AQ_INSTOP_INIT;
1241 
1242     return 0;
1243 }
1244 
1245 static int otx2_pool_init(struct otx2_nic *pfvf, u16 pool_id,
1246               int stack_pages, int numptrs, int buf_size)
1247 {
1248     struct npa_aq_enq_req *aq;
1249     struct otx2_pool *pool;
1250     int err;
1251 
1252     pool = &pfvf->qset.pool[pool_id];
1253     /* Alloc memory for stack which is used to store buffer pointers */
1254     err = qmem_alloc(pfvf->dev, &pool->stack,
1255              stack_pages, pfvf->hw.stack_pg_bytes);
1256     if (err)
1257         return err;
1258 
1259     pool->rbsize = buf_size;
1260 
1261     /* Initialize this pool's context via AF */
1262     aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox);
1263     if (!aq) {
1264         /* Shared mbox memory buffer is full, flush it and retry */
1265         err = otx2_sync_mbox_msg(&pfvf->mbox);
1266         if (err) {
1267             qmem_free(pfvf->dev, pool->stack);
1268             return err;
1269         }
1270         aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox);
1271         if (!aq) {
1272             qmem_free(pfvf->dev, pool->stack);
1273             return -ENOMEM;
1274         }
1275     }
1276 
1277     aq->aura_id = pool_id;
1278     aq->pool.stack_base = pool->stack->iova;
1279     aq->pool.stack_caching = 1;
1280     aq->pool.ena = 1;
1281     aq->pool.buf_size = buf_size / 128;
1282     aq->pool.stack_max_pages = stack_pages;
1283     aq->pool.shift = ilog2(numptrs) - 8;
1284     aq->pool.ptr_start = 0;
1285     aq->pool.ptr_end = ~0ULL;
1286 
1287     /* Fill AQ info */
1288     aq->ctype = NPA_AQ_CTYPE_POOL;
1289     aq->op = NPA_AQ_INSTOP_INIT;
1290 
1291     return 0;
1292 }
1293 
1294 int otx2_sq_aura_pool_init(struct otx2_nic *pfvf)
1295 {
1296     int qidx, pool_id, stack_pages, num_sqbs;
1297     struct otx2_qset *qset = &pfvf->qset;
1298     struct otx2_hw *hw = &pfvf->hw;
1299     struct otx2_snd_queue *sq;
1300     struct otx2_pool *pool;
1301     dma_addr_t bufptr;
1302     int err, ptr;
1303 
1304     /* Calculate number of SQBs needed.
1305      *
1306      * For a 128byte SQE, and 4K size SQB, 31 SQEs will fit in one SQB.
1307      * Last SQE is used for pointing to next SQB.
1308      */
1309     num_sqbs = (hw->sqb_size / 128) - 1;
1310     num_sqbs = (qset->sqe_cnt + num_sqbs) / num_sqbs;
1311 
1312     /* Get no of stack pages needed */
1313     stack_pages =
1314         (num_sqbs + hw->stack_pg_ptrs - 1) / hw->stack_pg_ptrs;
1315 
1316     for (qidx = 0; qidx < hw->tot_tx_queues; qidx++) {
1317         pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx);
1318         /* Initialize aura context */
1319         err = otx2_aura_init(pfvf, pool_id, pool_id, num_sqbs);
1320         if (err)
1321             goto fail;
1322 
1323         /* Initialize pool context */
1324         err = otx2_pool_init(pfvf, pool_id, stack_pages,
1325                      num_sqbs, hw->sqb_size);
1326         if (err)
1327             goto fail;
1328     }
1329 
1330     /* Flush accumulated messages */
1331     err = otx2_sync_mbox_msg(&pfvf->mbox);
1332     if (err)
1333         goto fail;
1334 
1335     /* Allocate pointers and free them to aura/pool */
1336     for (qidx = 0; qidx < hw->tot_tx_queues; qidx++) {
1337         pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx);
1338         pool = &pfvf->qset.pool[pool_id];
1339 
1340         sq = &qset->sq[qidx];
1341         sq->sqb_count = 0;
1342         sq->sqb_ptrs = kcalloc(num_sqbs, sizeof(*sq->sqb_ptrs), GFP_KERNEL);
1343         if (!sq->sqb_ptrs)
1344             return -ENOMEM;
1345 
1346         for (ptr = 0; ptr < num_sqbs; ptr++) {
1347             if (otx2_alloc_rbuf(pfvf, pool, &bufptr))
1348                 return -ENOMEM;
1349             pfvf->hw_ops->aura_freeptr(pfvf, pool_id, bufptr);
1350             sq->sqb_ptrs[sq->sqb_count++] = (u64)bufptr;
1351         }
1352     }
1353 
1354     return 0;
1355 fail:
1356     otx2_mbox_reset(&pfvf->mbox.mbox, 0);
1357     otx2_aura_pool_free(pfvf);
1358     return err;
1359 }
1360 
1361 int otx2_rq_aura_pool_init(struct otx2_nic *pfvf)
1362 {
1363     struct otx2_hw *hw = &pfvf->hw;
1364     int stack_pages, pool_id, rq;
1365     struct otx2_pool *pool;
1366     int err, ptr, num_ptrs;
1367     dma_addr_t bufptr;
1368 
1369     num_ptrs = pfvf->qset.rqe_cnt;
1370 
1371     stack_pages =
1372         (num_ptrs + hw->stack_pg_ptrs - 1) / hw->stack_pg_ptrs;
1373 
1374     for (rq = 0; rq < hw->rx_queues; rq++) {
1375         pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_RQ, rq);
1376         /* Initialize aura context */
1377         err = otx2_aura_init(pfvf, pool_id, pool_id, num_ptrs);
1378         if (err)
1379             goto fail;
1380     }
1381     for (pool_id = 0; pool_id < hw->rqpool_cnt; pool_id++) {
1382         err = otx2_pool_init(pfvf, pool_id, stack_pages,
1383                      num_ptrs, pfvf->rbsize);
1384         if (err)
1385             goto fail;
1386     }
1387 
1388     /* Flush accumulated messages */
1389     err = otx2_sync_mbox_msg(&pfvf->mbox);
1390     if (err)
1391         goto fail;
1392 
1393     /* Allocate pointers and free them to aura/pool */
1394     for (pool_id = 0; pool_id < hw->rqpool_cnt; pool_id++) {
1395         pool = &pfvf->qset.pool[pool_id];
1396         for (ptr = 0; ptr < num_ptrs; ptr++) {
1397             if (otx2_alloc_rbuf(pfvf, pool, &bufptr))
1398                 return -ENOMEM;
1399             pfvf->hw_ops->aura_freeptr(pfvf, pool_id,
1400                            bufptr + OTX2_HEAD_ROOM);
1401         }
1402     }
1403 
1404     return 0;
1405 fail:
1406     otx2_mbox_reset(&pfvf->mbox.mbox, 0);
1407     otx2_aura_pool_free(pfvf);
1408     return err;
1409 }
1410 
1411 int otx2_config_npa(struct otx2_nic *pfvf)
1412 {
1413     struct otx2_qset *qset = &pfvf->qset;
1414     struct npa_lf_alloc_req  *npalf;
1415     struct otx2_hw *hw = &pfvf->hw;
1416     int aura_cnt;
1417 
1418     /* Pool - Stack of free buffer pointers
1419      * Aura - Alloc/frees pointers from/to pool for NIX DMA.
1420      */
1421 
1422     if (!hw->pool_cnt)
1423         return -EINVAL;
1424 
1425     qset->pool = devm_kcalloc(pfvf->dev, hw->pool_cnt,
1426                   sizeof(struct otx2_pool), GFP_KERNEL);
1427     if (!qset->pool)
1428         return -ENOMEM;
1429 
1430     /* Get memory to put this msg */
1431     npalf = otx2_mbox_alloc_msg_npa_lf_alloc(&pfvf->mbox);
1432     if (!npalf)
1433         return -ENOMEM;
1434 
1435     /* Set aura and pool counts */
1436     npalf->nr_pools = hw->pool_cnt;
1437     aura_cnt = ilog2(roundup_pow_of_two(hw->pool_cnt));
1438     npalf->aura_sz = (aura_cnt >= ilog2(128)) ? (aura_cnt - 6) : 1;
1439 
1440     return otx2_sync_mbox_msg(&pfvf->mbox);
1441 }
1442 
1443 int otx2_detach_resources(struct mbox *mbox)
1444 {
1445     struct rsrc_detach *detach;
1446 
1447     mutex_lock(&mbox->lock);
1448     detach = otx2_mbox_alloc_msg_detach_resources(mbox);
1449     if (!detach) {
1450         mutex_unlock(&mbox->lock);
1451         return -ENOMEM;
1452     }
1453 
1454     /* detach all */
1455     detach->partial = false;
1456 
1457     /* Send detach request to AF */
1458     otx2_mbox_msg_send(&mbox->mbox, 0);
1459     mutex_unlock(&mbox->lock);
1460     return 0;
1461 }
1462 EXPORT_SYMBOL(otx2_detach_resources);
1463 
1464 int otx2_attach_npa_nix(struct otx2_nic *pfvf)
1465 {
1466     struct rsrc_attach *attach;
1467     struct msg_req *msix;
1468     int err;
1469 
1470     mutex_lock(&pfvf->mbox.lock);
1471     /* Get memory to put this msg */
1472     attach = otx2_mbox_alloc_msg_attach_resources(&pfvf->mbox);
1473     if (!attach) {
1474         mutex_unlock(&pfvf->mbox.lock);
1475         return -ENOMEM;
1476     }
1477 
1478     attach->npalf = true;
1479     attach->nixlf = true;
1480 
1481     /* Send attach request to AF */
1482     err = otx2_sync_mbox_msg(&pfvf->mbox);
1483     if (err) {
1484         mutex_unlock(&pfvf->mbox.lock);
1485         return err;
1486     }
1487 
1488     pfvf->nix_blkaddr = BLKADDR_NIX0;
1489 
1490     /* If the platform has two NIX blocks then LF may be
1491      * allocated from NIX1.
1492      */
1493     if (otx2_read64(pfvf, RVU_PF_BLOCK_ADDRX_DISC(BLKADDR_NIX1)) & 0x1FFULL)
1494         pfvf->nix_blkaddr = BLKADDR_NIX1;
1495 
1496     /* Get NPA and NIX MSIX vector offsets */
1497     msix = otx2_mbox_alloc_msg_msix_offset(&pfvf->mbox);
1498     if (!msix) {
1499         mutex_unlock(&pfvf->mbox.lock);
1500         return -ENOMEM;
1501     }
1502 
1503     err = otx2_sync_mbox_msg(&pfvf->mbox);
1504     if (err) {
1505         mutex_unlock(&pfvf->mbox.lock);
1506         return err;
1507     }
1508     mutex_unlock(&pfvf->mbox.lock);
1509 
1510     if (pfvf->hw.npa_msixoff == MSIX_VECTOR_INVALID ||
1511         pfvf->hw.nix_msixoff == MSIX_VECTOR_INVALID) {
1512         dev_err(pfvf->dev,
1513             "RVUPF: Invalid MSIX vector offset for NPA/NIX\n");
1514         return -EINVAL;
1515     }
1516 
1517     return 0;
1518 }
1519 EXPORT_SYMBOL(otx2_attach_npa_nix);
1520 
1521 void otx2_ctx_disable(struct mbox *mbox, int type, bool npa)
1522 {
1523     struct hwctx_disable_req *req;
1524 
1525     mutex_lock(&mbox->lock);
1526     /* Request AQ to disable this context */
1527     if (npa)
1528         req = otx2_mbox_alloc_msg_npa_hwctx_disable(mbox);
1529     else
1530         req = otx2_mbox_alloc_msg_nix_hwctx_disable(mbox);
1531 
1532     if (!req) {
1533         mutex_unlock(&mbox->lock);
1534         return;
1535     }
1536 
1537     req->ctype = type;
1538 
1539     if (otx2_sync_mbox_msg(mbox))
1540         dev_err(mbox->pfvf->dev, "%s failed to disable context\n",
1541             __func__);
1542 
1543     mutex_unlock(&mbox->lock);
1544 }
1545 
1546 int otx2_nix_config_bp(struct otx2_nic *pfvf, bool enable)
1547 {
1548     struct nix_bp_cfg_req *req;
1549 
1550     if (enable)
1551         req = otx2_mbox_alloc_msg_nix_bp_enable(&pfvf->mbox);
1552     else
1553         req = otx2_mbox_alloc_msg_nix_bp_disable(&pfvf->mbox);
1554 
1555     if (!req)
1556         return -ENOMEM;
1557 
1558     req->chan_base = 0;
1559 #ifdef CONFIG_DCB
1560     req->chan_cnt = pfvf->pfc_en ? IEEE_8021QAZ_MAX_TCS : 1;
1561     req->bpid_per_chan = pfvf->pfc_en ? 1 : 0;
1562 #else
1563     req->chan_cnt =  1;
1564     req->bpid_per_chan = 0;
1565 #endif
1566 
1567 
1568     return otx2_sync_mbox_msg(&pfvf->mbox);
1569 }
1570 EXPORT_SYMBOL(otx2_nix_config_bp);
1571 
1572 /* Mbox message handlers */
1573 void mbox_handler_cgx_stats(struct otx2_nic *pfvf,
1574                 struct cgx_stats_rsp *rsp)
1575 {
1576     int id;
1577 
1578     for (id = 0; id < CGX_RX_STATS_COUNT; id++)
1579         pfvf->hw.cgx_rx_stats[id] = rsp->rx_stats[id];
1580     for (id = 0; id < CGX_TX_STATS_COUNT; id++)
1581         pfvf->hw.cgx_tx_stats[id] = rsp->tx_stats[id];
1582 }
1583 
1584 void mbox_handler_cgx_fec_stats(struct otx2_nic *pfvf,
1585                 struct cgx_fec_stats_rsp *rsp)
1586 {
1587     pfvf->hw.cgx_fec_corr_blks += rsp->fec_corr_blks;
1588     pfvf->hw.cgx_fec_uncorr_blks += rsp->fec_uncorr_blks;
1589 }
1590 
1591 void mbox_handler_nix_txsch_alloc(struct otx2_nic *pf,
1592                   struct nix_txsch_alloc_rsp *rsp)
1593 {
1594     int lvl, schq;
1595 
1596     /* Setup transmit scheduler list */
1597     for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++)
1598         for (schq = 0; schq < rsp->schq[lvl]; schq++)
1599             pf->hw.txschq_list[lvl][schq] =
1600                 rsp->schq_list[lvl][schq];
1601 
1602     pf->hw.txschq_link_cfg_lvl = rsp->link_cfg_lvl;
1603 }
1604 EXPORT_SYMBOL(mbox_handler_nix_txsch_alloc);
1605 
1606 void mbox_handler_npa_lf_alloc(struct otx2_nic *pfvf,
1607                    struct npa_lf_alloc_rsp *rsp)
1608 {
1609     pfvf->hw.stack_pg_ptrs = rsp->stack_pg_ptrs;
1610     pfvf->hw.stack_pg_bytes = rsp->stack_pg_bytes;
1611 }
1612 EXPORT_SYMBOL(mbox_handler_npa_lf_alloc);
1613 
1614 void mbox_handler_nix_lf_alloc(struct otx2_nic *pfvf,
1615                    struct nix_lf_alloc_rsp *rsp)
1616 {
1617     pfvf->hw.sqb_size = rsp->sqb_size;
1618     pfvf->hw.rx_chan_base = rsp->rx_chan_base;
1619     pfvf->hw.tx_chan_base = rsp->tx_chan_base;
1620     pfvf->hw.lso_tsov4_idx = rsp->lso_tsov4_idx;
1621     pfvf->hw.lso_tsov6_idx = rsp->lso_tsov6_idx;
1622     pfvf->hw.cgx_links = rsp->cgx_links;
1623     pfvf->hw.lbk_links = rsp->lbk_links;
1624     pfvf->hw.tx_link = rsp->tx_link;
1625 }
1626 EXPORT_SYMBOL(mbox_handler_nix_lf_alloc);
1627 
1628 void mbox_handler_msix_offset(struct otx2_nic *pfvf,
1629                   struct msix_offset_rsp *rsp)
1630 {
1631     pfvf->hw.npa_msixoff = rsp->npa_msixoff;
1632     pfvf->hw.nix_msixoff = rsp->nix_msixoff;
1633 }
1634 EXPORT_SYMBOL(mbox_handler_msix_offset);
1635 
1636 void mbox_handler_nix_bp_enable(struct otx2_nic *pfvf,
1637                 struct nix_bp_cfg_rsp *rsp)
1638 {
1639     int chan, chan_id;
1640 
1641     for (chan = 0; chan < rsp->chan_cnt; chan++) {
1642         chan_id = ((rsp->chan_bpid[chan] >> 10) & 0x7F);
1643         pfvf->bpid[chan_id] = rsp->chan_bpid[chan] & 0x3FF;
1644     }
1645 }
1646 EXPORT_SYMBOL(mbox_handler_nix_bp_enable);
1647 
1648 void otx2_free_cints(struct otx2_nic *pfvf, int n)
1649 {
1650     struct otx2_qset *qset = &pfvf->qset;
1651     struct otx2_hw *hw = &pfvf->hw;
1652     int irq, qidx;
1653 
1654     for (qidx = 0, irq = hw->nix_msixoff + NIX_LF_CINT_VEC_START;
1655          qidx < n;
1656          qidx++, irq++) {
1657         int vector = pci_irq_vector(pfvf->pdev, irq);
1658 
1659         irq_set_affinity_hint(vector, NULL);
1660         free_cpumask_var(hw->affinity_mask[irq]);
1661         free_irq(vector, &qset->napi[qidx]);
1662     }
1663 }
1664 
1665 void otx2_set_cints_affinity(struct otx2_nic *pfvf)
1666 {
1667     struct otx2_hw *hw = &pfvf->hw;
1668     int vec, cpu, irq, cint;
1669 
1670     vec = hw->nix_msixoff + NIX_LF_CINT_VEC_START;
1671     cpu = cpumask_first(cpu_online_mask);
1672 
1673     /* CQ interrupts */
1674     for (cint = 0; cint < pfvf->hw.cint_cnt; cint++, vec++) {
1675         if (!alloc_cpumask_var(&hw->affinity_mask[vec], GFP_KERNEL))
1676             return;
1677 
1678         cpumask_set_cpu(cpu, hw->affinity_mask[vec]);
1679 
1680         irq = pci_irq_vector(pfvf->pdev, vec);
1681         irq_set_affinity_hint(irq, hw->affinity_mask[vec]);
1682 
1683         cpu = cpumask_next(cpu, cpu_online_mask);
1684         if (unlikely(cpu >= nr_cpu_ids))
1685             cpu = 0;
1686     }
1687 }
1688 
1689 u16 otx2_get_max_mtu(struct otx2_nic *pfvf)
1690 {
1691     struct nix_hw_info *rsp;
1692     struct msg_req *req;
1693     u16 max_mtu;
1694     int rc;
1695 
1696     mutex_lock(&pfvf->mbox.lock);
1697 
1698     req = otx2_mbox_alloc_msg_nix_get_hw_info(&pfvf->mbox);
1699     if (!req) {
1700         rc =  -ENOMEM;
1701         goto out;
1702     }
1703 
1704     rc = otx2_sync_mbox_msg(&pfvf->mbox);
1705     if (!rc) {
1706         rsp = (struct nix_hw_info *)
1707                otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr);
1708 
1709         /* HW counts VLAN insertion bytes (8 for double tag)
1710          * irrespective of whether SQE is requesting to insert VLAN
1711          * in the packet or not. Hence these 8 bytes have to be
1712          * discounted from max packet size otherwise HW will throw
1713          * SMQ errors
1714          */
1715         max_mtu = rsp->max_mtu - 8 - OTX2_ETH_HLEN;
1716 
1717         /* Also save DWRR MTU, needed for DWRR weight calculation */
1718         pfvf->hw.dwrr_mtu = rsp->rpm_dwrr_mtu;
1719         if (!pfvf->hw.dwrr_mtu)
1720             pfvf->hw.dwrr_mtu = 1;
1721     }
1722 
1723 out:
1724     mutex_unlock(&pfvf->mbox.lock);
1725     if (rc) {
1726         dev_warn(pfvf->dev,
1727              "Failed to get MTU from hardware setting default value(1500)\n");
1728         max_mtu = 1500;
1729     }
1730     return max_mtu;
1731 }
1732 EXPORT_SYMBOL(otx2_get_max_mtu);
1733 
1734 int otx2_handle_ntuple_tc_features(struct net_device *netdev, netdev_features_t features)
1735 {
1736     netdev_features_t changed = features ^ netdev->features;
1737     struct otx2_nic *pfvf = netdev_priv(netdev);
1738     bool ntuple = !!(features & NETIF_F_NTUPLE);
1739     bool tc = !!(features & NETIF_F_HW_TC);
1740 
1741     if ((changed & NETIF_F_NTUPLE) && !ntuple)
1742         otx2_destroy_ntuple_flows(pfvf);
1743 
1744     if ((changed & NETIF_F_NTUPLE) && ntuple) {
1745         if (!pfvf->flow_cfg->max_flows) {
1746             netdev_err(netdev,
1747                    "Can't enable NTUPLE, MCAM entries not allocated\n");
1748             return -EINVAL;
1749         }
1750     }
1751 
1752     if ((changed & NETIF_F_HW_TC) && tc) {
1753         if (!pfvf->flow_cfg->max_flows) {
1754             netdev_err(netdev,
1755                    "Can't enable TC, MCAM entries not allocated\n");
1756             return -EINVAL;
1757         }
1758     }
1759 
1760     if ((changed & NETIF_F_HW_TC) && !tc &&
1761         pfvf->flow_cfg && pfvf->flow_cfg->nr_flows) {
1762         netdev_err(netdev, "Can't disable TC hardware offload while flows are active\n");
1763         return -EBUSY;
1764     }
1765 
1766     if ((changed & NETIF_F_NTUPLE) && ntuple &&
1767         (netdev->features & NETIF_F_HW_TC) && !(changed & NETIF_F_HW_TC)) {
1768         netdev_err(netdev,
1769                "Can't enable NTUPLE when TC is active, disable TC and retry\n");
1770         return -EINVAL;
1771     }
1772 
1773     if ((changed & NETIF_F_HW_TC) && tc &&
1774         (netdev->features & NETIF_F_NTUPLE) && !(changed & NETIF_F_NTUPLE)) {
1775         netdev_err(netdev,
1776                "Can't enable TC when NTUPLE is active, disable NTUPLE and retry\n");
1777         return -EINVAL;
1778     }
1779 
1780     return 0;
1781 }
1782 EXPORT_SYMBOL(otx2_handle_ntuple_tc_features);
1783 
1784 #define M(_name, _id, _fn_name, _req_type, _rsp_type)           \
1785 int __weak                              \
1786 otx2_mbox_up_handler_ ## _fn_name(struct otx2_nic *pfvf,        \
1787                 struct _req_type *req,          \
1788                 struct _rsp_type *rsp)          \
1789 {                                   \
1790     /* Nothing to do here */                    \
1791     return 0;                           \
1792 }                                   \
1793 EXPORT_SYMBOL(otx2_mbox_up_handler_ ## _fn_name);
1794 MBOX_UP_CGX_MESSAGES
1795 #undef M
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!